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A Nanowatt Smart Temperature Sensor for Dynamic Thermal Management

Pablo Ituero, Student Member, IEEE, Jos L. Ayala, Member, IEEE, and Marisa Lpez-Vallejo, Member, IEEE
AbstractThe amazing integration densities achieved by current submicron technologies pay the price of increasing static power dissipation with the corresponding rise in heat density. Dynamic Thermal Management (DTM) techniques provide thermal-efcient solutions to balance or equally distribute possible on-chip hot spots. Accurate sensing of on-chip temperature is required by optimally allocating smart temperature sensors in the silicon. In this paper, we introduce an ultra low-power 2 ) CMOS smart (1.0565.5 nW at 5 samples/s) tiny (10250 temperature sensor based on the thermal dependency of the leakage current. The proposed sensor outperforms all previous works, as far as area and power consumption are concerned (more than 85% reduction in both cases), while still meeting the accuracy constraints imposed by target application domains. Furthermore, a specic interface based on the use of a logarithmic counter has been implemented to digitalize the temperature sensing. These facts, in conjunction with the full compatibility of the sensor with standard CMOS processes, allow the easy integration of many of these tiny sensors in any VLSI layout, making them specially suitable for modern DTM implementations.

Index TermsDynamic thermal management (DTM), leakage, sensor, temperature, time-to-digital.

I. INTRODUCTION OLLOWING Moores Law, current submicron technologies have allowed extraordinary integration densities in digital circuits. However, as processes scale down, there is a signicant increase in interconnect current densities and static power dissipation. Given that this power is, in part, converted into heat, an important rise in heat density is also experienced. In other order of things, the International Technology Roadmap for Semiconductors [1] has predicted that traditional design constraints centered around product cost and performance requirements will soon be overtaken by system wear-out failures and lifetime reliability issues [2]. Taking all these facts into account, temperature becomes a rst class design constraint because high temperatures adversely affect circuit reliability and degrade the performance. Specically, electromigrations, time-dependent-dielectric-breakdowns, stress migrations, and thermal cyclings are all

Manuscript received May 13, 2008, accepted June 09, 2008. Current version published November 19, 2008. This work was supported in part by the CICYT project OPTIMA TEC2006-00739 of the Spanish Ministry of Science and Technology. The associate editor coordinating the review of this paper and approving it for publication was Dr. Subhas Mukhopadhyay. P. Ituero and M. Lpez-Vallejo are with the Integrated Systems Laboratory, Department of Electronic Engineering, ETSI Telecomunicacin, Universidad Politcnica de Madrid, 28040 Madrid, Spain (email: pituero@die.upm.es; marisa@die.upm.es). J. L. Ayala is with the Computer Science Faculty at the Complutense University of Madrid, 28040 Madrid, Spain (email: jayala@fdi.ucm.es). Digital Object Identier 10.1109/JSEN.2008.2007692

temperature-activated processes that signicantly reduce the mean time to failure of systems and processor microarchitectures [2]. Designers must face these new challenges by providing thermal-efcient systems that balance or equally distribute possible on-chip hot spots. In this scenario, Dynamic Temperature Management (DTM) techniques [3], [4] arise as a promising solution. DTM relies on accurately sensing and managing on-chip temperature, both in space and time, by optimally allocating smart temperature sensors in the silicon [5]. These sensors, which must be fully compatible with the CMOS processes, must be characterized by low-area, low power, and a digital interface to simplify the monitoring of temperature in a DTM implementation. Other important application of smart temperature sensors is the control of leakage in complex VLSI chips, which has become a serious constraint in deep submicron technologies, where static currents dominate the power consumption equation [6]. Monitoring leakage with smart sensors can be the base of the implementation of leakage-saving techniques [7] or can help adjust dynamic power management policies [8]. Most on-chip temperature sensors are based on the use of Bipolar Junction Transistors (BJTs), whose base-emitter voltage [9]. The imcan be used to obtain the thermal voltage plementation of this kind of temperature sensors in standard CMOS processes can be done making use of lateral and (vertical) substrate transistors. However, these sensors require complicated calibration and their nonlinear dependency with temperature demands sophisticated output interfaces that make the sensors occupy a large area. To eliminate the problems related to BJT-based temperature sensors, a time-to-digital-converterbased sensor was introduced in [10]. This circuit generates a pulse whose width is proportional to the temperature, avoiding the use of expensive ADCs. This time-domain approach results in low area and low voltage smart temperature sensors that have been recently implemented on an FPGA [11]. In this paper, we also propose a time-domain approach, specically we introduce an improved CMOS smart temperature sensor based on the thermal dependency of the leakage current. The main contributions of this work are the following. , and power consumption, Very reduced area, 10250 1.0565.5 nW at 5 samples/s, improving previous implementations in more than 85%. A specic interface has been designed to digitalize the temperature sensing. It converts by means of a logarithmic counter the temperature-dependent exponential voltage drop sensed by the thermal sensor into a linear digital value. Good linearity and accuracy, appropriate to deal with DTM applications. We have carried out exhaustive Monte Carlo

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simulations, which include sensitivity and resolution analysis along with process variations analysis, to precisely characterize the behavior of the sensor. Full compatibility with standard CMOS processes, what allows the easy integration of many sensors in any VLSI layout for DTM. The structure of this paper is the following. Section II provides the reader with a theoretical background on the behavior of leakage currents and their thermal dependencies. In Section III, we put forward our sensor and detail its functioning. The digital interface is described in Section IV. The characterization results are presented in Section V and discussed in Section VI, comparing them with previous works. Finally, Section VII draws the main conclusions. II. TEMPERATURE BEHAVIOR OF LEAKAGE CURRENTS The continuous scaling of CMOS technologies has highlighted the importance of the leakage currents, those that ow even when the transistors are in an off condition. The leakage current is made up of several components, from subthreshold conduction or reverse biased pn junction leakages to tunneling effects. However, the subthreshold conduction far exceeds the rest and characterizes the behavior of the complete leakage current [12]. Subthreshold leakage is the weak inversion conduction current that ows between the source and the drain of a MOS tran. For sistor when gate voltage is below the threshold voltage the purposes of this work, the dependency of the subthreshold current on the device temperature is modeled as follows: (1) is the thermal voltage, is the tranIn this equation, sistor subthreshold swing coefcient, and denote the transistor gate-source and drain-source voltages, respectively. is a technology parameter, dependent on the temperature given by (2) where is the zero bias carrier mobility, the gate oxide capacitance, is the transistor width, and denotes the transistor effective channel length. Finally, in (3), denotes the transistor threshold voltage which can be expressed as follows as a function of the temperature: (3) where is the threshold voltage at a nominal temperature , is the temperature coefcient of the threshold voltage, is the channel-length coefcient of the threshold voltages temperature dependence, is the bulk-bias coefcient of the threshold voltages temperature dependence, and is the transistor body-source voltage. Previous equations show that the dependence of the subthreshold current on the temperature is complex and includes

exponential and quadratic terms. Specically, in the case when , employed by this work, the subthreshold leakage can be modeled as follows:

(4) and are empirical parameters given by the folwhere lowing expressions:

(5)

(6) Also, previous equations show that subthreshold leakage depends primarily on temperature, supply voltage, and body bias voltage. Gate leakage, in contrast, is primarily affected by supply voltage and gate dielectric thickness, but is insensitive to temperature [13]. III. DESCRIPTION OF THE SENSOR with the In order to take advantage of the variations of temperature, this work proposes to measure the time that takes to discharge a capacitance. Intuitively, we can guess that this time will display the same thermal dependencies as the subthreshold current, this will be studied in depth and proved in this section. The structure of the sensor is displayed in Fig. 1. Similarly to what happens in dynamic gates, when the input receives a low-to-high transition and transistor M1 goes from an on to an stores a charge that ideally would off condition, capacitor remain untouched, but that actually will gradually leak away due to leakage currents. Fig. 2 shows the sources of leakage for transistors M1 and M2. Sources (1) and (2) are subthreshold leakages of M2 and M1, respectively. As mentioned before, these two components will dominate the behavior of the sensor. Sources (3) and (4) are reverse-biased diode leakages of M2 and M1, respectively. , whereas sources (2) and (4) Sources (1) and (3) discharge is charged, the transistor M2 drain-source charge it. When equals and its subthreshold current voltage reaches a maximum. At the same time, and equal 0. decreases and so does As the charge leaks away, . In contrast, increases, which yields a rise in . When both currents become equal, the voltage settles to an intermediate value determined by the drop at ratio between the subthreshold current of the NMOS and PMOS devices, actually controlled by the sizing of the transistors. The sizing of the pull-down device is done in such a way that and the settling intermediate voltage is very close to 0 V. In this way, this intermediate voltage is taken far from the switching threshold of the inverter M3M4, is moreover, when the measurement is captured, still very small and can be neglected.

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Fig. 1. Subthreshold current thermal sensor.

Fig. 2. Leakage current mechanisms in the thermal sensor.

charge from a certain voltage culated as

to another voltage

is cal-

(7) This expression represents the dependency of the sensors measurement on the temperature. Simulation results have proven that an exponential behavior provides an appropriate t for this dependency. From (7), the strengths and weaknesses of the sensor can be inferred. For example, the thermal dependency of the threshold voltages of M3 and M4 will vary the value of , so, in order to provide these transistors with an improved stability, their widths and channel lengths must be higher than the minimum of the technology to assure that the manufacturing error is minimized. In Section V, we analyze the impact of statistical errors of the parameters that are more likely to affect the response of the sensor. IV. INTERFACING The output of the sensor yields an analog signalthe duration of a pulsethat decreases exponentially with the temperature. This measurement must be converted into a digital form and transformed in such a way that a linear response to the temperature is obtained. In this section, a simple but effective approach to a digital interface for the sensor will be described. A. Logarithmic Conversion Dealing with exponentially varying data requires an elevated number of bits and interconnection lines and, furthermore, complicates the conversion between the measure and a real temperature. An intuitive way to transform an exponential response to

Fig. 3. Basic functioning of the thermal sensor.

When the voltage at falls below the switching threshold of the inverter M3-M4, the output produces a low-to-high transition. The time between the low-to-high transition at the input (IN signal in Fig. 1) and the low-to-high transition at the output (OUT signal in Fig. 1) or, equivalently, the discharge time of , is the sensors measurement. Fig. 3 shows the functioning of the sensor. and its thermal dependencies The magnitude of , as a matter of fact, if the will control the discharge time of appropriate sizing is done, M2 can be considered the sensing de, vice of the whole system. Given that will remain almost constant during the sensing operation at a to disgiven temperature. Therefore, the time that takes

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Fig. 4. Logarithmic counter schematic.

a linear one is by means of the logarithm operation. In the logarithmic domain the sensors response is expressed by the following equation:

TABLE I NUMBER OF BITS IN COUNTER A AS A FUNCTION OF THE MAXIMUM ERROR OF THE SENSOR

(8) For the range of temperatures of interest and for standard techand , a linear t with negnology values for constants ative slope represents a very good approximation for this response, as experimental data will show. B. Time-to-Digital Conversion We have employed a logarithmic counter [14] to carry out the conversion, as shown in Fig. 4. By this way, the time-to-digital conversion and the linearization, by means of the logarithm in base 2, are performed simultaneously. The logarithmic counter consists of two standard counters, a tree of frequency dividers, and a LUT. Counter A is fed by a clock signal that controls its auto-increment rate; whenever this counter produces a signal, counter B is incremented; the output of counter B controls the frequency divider so that each time it increases, the frequency is divided by two and thus the auto-increment rate of counter A is also divided by two. In this way, counter B stores the logarithmic count and counter A stores a linear count that must be turned into logarithmic decimals by means of the LUT. Random variations in the process and an imperfect exponential response of the sensor will produce errors in the measurements with respect to an ideal linear behavior. In order to opti, will mize the resolution, the maximum error, referred to as x the maximum distance between consecutive measurements . Counter A stores a count in the logarithmic domain as that increases linearly, which implies that in the logarithmic domain this count will have different distances between consecutive numbers. Similarly to the distances between the lines inside a decade in a logarithmic graph paper, the maximum distance between consecutive measurements corresponds to the rst in, being the number terval, and is given by of bits in counter A; this distance decreases until counter A is lled and then reaches the maximum again. By this way, we can establish a relationship between the number of bits in counter A , this is shown and the maximum error as in Table I. Once the number of bits in counter A is xed, we can congure the rest of the parameters of the logarithmic counter. First, the frequency that feeds counter A at the beginning of the process must be set in such a way that the lowest measure at least signal is produced and counter B lls counter A once so a starts to counte.g., if counter A has three bits, the period of the rst clock should be set at most 1/8 of the minimum measurable time. This is necessary to make the distance between the lowest . measure and the next possible measure equal to The number of bits in counter B must be enough to represent the integer part of the maximum measurement. Another factor that must be taken into account is the number of bits at the output of the LUT. Since counter A produces different intervals at the logarithmic domain, depending on our precision and word length requirements, we have to decide the number of bitse.g., if we want to keep the maximum precision, we have to provide the LUT with the necessary bits to measure the minimum difference. Hence, the effective resolution of the sensor will be dependent on the number of LUT bits and bounded by the following expressions [15]: (9) and , the maximum and minimum meabeing the number of bits at the sured temperatures, respectively, the bits of counter B. output of the LUT and Table II illustrates the case of a decimal counter with three bits, the rst three columns give the value of the count, the next column translates this count to the logarithmic domain, and the

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TABLE II PRECISION ANALYSIS FOR LUTS OF TWO TO FOUR OUTPUT BITS

Fig. 5. Implementation of the sensor along with the logarithmic counter.

rest of the columns detail the content of the LUT and the quantization error for LUT sizes of four, three, and two bits. As shown, the maximum interval, the rst, is 0.1699 and the minimum and last is 0.0931. If we want to keep the precision of the last interval, a 5-bit LUT is a good solution with a maximum error of 0.0306. In contrast, if we have strict size requirements we might select the 2-bit LUT at the price of a maximum error of 0.0931. Finally, an intermediate solution is given by the 4-bit LUT with a maximum error of 0.0574. This sets out an interesting tradeoff between area and resolution. Concerning the energy consumption of the logarithmic counter, the tree of frequency dividers and counter A are the parts that produce more signal transitions and thus consume more power. There is little solution to apply to the tree apart from minimizing interconnect capacitances in the physical layout, however, in the case of counter A, we can apply Gray encoding in order to minimize the number of transitions. Moreover, this modication will have no impact in the digital output since this counter feeds the LUT. Finally, Fig. 5 shows the implementation of the sensor along with the logarithmic counter. A clockclock_indrives the input of the sensor, after charging with a narrow low pulse, its low-to-high transition leaves the intermediate node oating and sets when the logarithmic count must start. When, due to the crosses the threshold voltage of inverter leakage process, M3-M4, the logarithmic counter receives a low-to-high transition at the load input, the count ends and is registered. Note that the loading rate of the register, i.e., the conversion rate of the sensor, is equal to the frequency of clock_in. This frequency is bounded by the pulse width of the minimum temperature that the sensor needs to measure. An external control will decide this

Fig. 6. Layout of the system.

conversion rate depending on the precision and power requirements of the system. V. CHARACTERIZATION The circuits proposed in this work have been tested using technology from Austria MicroSystems that ema 0.35 ploys a dual-poly quadruple-metal CMOS process. The experimental work, simulations, and layouts have been carried out in the Cadence environment. Fig. 6 shows the layout of the circuit; the whole implementation takes an area of , i.e., 0.01 . Notice that the sensor just takes , i.e., 843.0 , which supposes an 8.2% of the whole system, this little area of the sensing part will result in interesting possibilities for the calibration, as discussed in Section VI. The range of temperatures employed in the exto 100 . periments covered 20

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Fig. 7. Current and ideal transfer function of the sensor along with the power consumption at 5 samples/s as a function of the temperature.

A. Sensitivity and Resolution Under Nominal Conditions Ideal sensors are designed to be linear or equivalently are designed to have a constant sensitivity throughout the measuring bounds. However, there always exists some curvature in the characteristic curve and this is one of the most important technological bottlenecks of integrated smart temperature sensors [10]. With our theoretical analysis, (8) yields the following function of the temperature for the sensitivity of the sensor: (10) in our technology we obtain a maxFor the nominal value of imum 27% variation from the average. This theoretical gure turned out to precisely match our simulations results. Fig. 7 displays the characteristic curve of the sensor under nominal conditions. The deviation from the linear regression of all the points provides us with the error committed in each value of the error under these conditions measurement. The and the maximum deviation of the sensitivity is 27%. is 0.97 Assuming that the outputs of the sensor at 20 and 100 are and , respectively, then the effective resolution can be . Under nominal conditions, calculated as . the sensor displays an effective resolution of B. Power Consumption As far as the power consumption is concerned, the sensor will display different gures depending on the temperature. The main reason for this is that the counters have to spend more time calculating the data as the time to measure increases, furthermore, the sensor will also consume more power as the discharge time rises. Power results are displayed in Fig. 7, the consumption was simulated at the conversion rate of 5 samples/s. As shown, there is a variation from 1.05 to 65.5 nW, from the maximum to the minimum temperature, respectively. The power consumption decreases signicantly, exponentially in fact, as the temperature grows. In consequence, self-heating effects also diminish at high temperatures.

3 ERROR OF THE SENSOR AS A FUNCTION OF THE PROCESS VARIATIONS

TABLE III

C. Effects of the Process Variability variations, gate oxide thickness Gate length variations, and doping uctuations affect the leakage current and, thus, distort the measurement of the proposed smart temperature sensor. A statistical leakage analysis method for these three parameters was proposed in [16] and the particular case of the gate length variations was deeply studied in [17], where an analytical model was introduced. These previous works found that the variation in gate length has the strongest impact among the process parameters affecting the leakage current since gate oxide thickness is extremely well controlled by modern processes and the effect of the channel doping is fairly small. However, whereas these works aimed at transistors with gate lengths close to the nominal technology value, in the case of the proposed sensor, the dominant leakage current will come from a transistor whose gate length is at least one order of magnitude larger than the nominal value, so the variations in this parameter are expected to be relatively smaller. Apart from these three parameters whose variation will affect the response of the sensor mainly because of their effect in the leakage current, the uctuations in the discharge capacitance due to inaccuracies in the fabrication stage will also impact the resolution of the system. The variations of solid capacitances in the fabrication stage have been reported to achieve up to a 10% [18]. In order to measure the inuence of all these variables on the resolution of the sensor, we performed Monte Carlo analyses for each of them. The experiment consisted in generating normal distributions around the nominal value of a parameter, and simulating the response of the sensor for all and each of the values in the distributions; from the simulations, we obtained a cloud of

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TABLE IV COMPARISON OF RECENT SMART THERMAL SENSORS

measure errors; averaging these errors, nally, we got the decrease in the sensor resolution produced by the parameter. More precisely, we generated distributions of 100 values for each pathe values proposed in [16] for , rameter taking as , and and for the case of the discharge capacitance, we value of 10%. considered a Table III summarizes the results of the statistical leakage analare the ones that most increase the ysis. Variations in error of the sensor, up to 1.97 ; the discharge capaciappear to have a similar impact in the resolutance and ; uctuations, in contrast, have less tion around 1.87 effects in the resolution. From Table III, we can conclude that the sensor without any post-fabrication calibration displays a maximum error of 1.97 . VI. COMPARISON WITH PREVIOUS WORKS AND DISCUSSION Table IV compares our proposal with recent smart thermal sensors described in the literature. As shown, the most outstanding characteristics of the sensor is the area that is nine times smaller than the best predecessor employing the same technology and the power consumption that, for the worse case, outperforms previous works by more than 85%. It is important to remark that whenever there is a time-to-digital conversionsuch as in our work, in [10] or [15]there will always be signicant differences in power consumption between maximum and minimum measured times and an average value is probably a too vague gure of merit. Note that if the minimum temperature requirements change, so does the conversion rate, which is bounded by the longest measure; e.g., if a designer on, then the needs to measure temperatures that go from 40 maximum conversion rate of the sensor is incremented up to 34 samples/s. The smallness and low power consumption of our sensor provide with two main advantages against previous works. First, the sensor is highly insensitive to spatial thermal gradients because of the reduced area of the sensing part. Second, the low-power dissipation makes the system very robust against self-heating issues. Since all the experiments were carried out in a simulation environment, we have not tackled with calibration issues in actual chips, however, some general ideas can be put forward. Considering that the sensing part of the system is very small, we could afford to replicate this part several times for each modulee.g., if we placed four sensors in each system, we would obtain a 22% area increase. Then, for instance, at initial calibration, the system would take measures from all the sensors and select the

one that is closest to the average. Moreover, we could further exploit the smallness of the sensing part if the time-to-digital converter was shared by several sensors with a time multiplexing approache.g., if we needed a conversion rate of 4 samples/s, we could employ up to three sensors, distributed at different points, for the same time-to-digital converter working at 12 samples/s; the area saving for this example would be 62%, without considering interconnections. Predictive models project a signicant increase in the nominal values of the leakage current for future technologies. Namely, to 150 at [23] predicts an evolution from 30 and 32 nm, respectively. In the technology nodes of 130 the case of our sensor, this entails that the discharge time of , inversely proportional to s leakage current, will shrink as much as the nominal leakage current grows with new techs ratio remains nology nodesalways supposing that constant. The ultimate effect is that the conversion rate of the discharge time at the minimum tempersensor, inverse to ature, will grow importantly as the technology processes scale down. We do not have the predictions for all the parameters in, but assuming cluded in and an increment of of just a 2.4% from 130 to 32 nm technology nodes [23], we can state that the sensitivity of the sensor with the temperature, as expressed by (10), will suffer very little variations in future technologies. Concerning the areas of application of the sensor, it is specially suitable for elds that demand to measure working on-chip temperatures at an elevated space granularity, whereas being somehow looser in their accuracy requirements. Such areas of application would cover DTM techniques, for both analog and digital designs; leakage monitoring techniques; and the implementation of reliability-aware policies. Furthermore, the sensing part of our proposal is so tiny and easy to implement that it could possibly be included in any standard-cell library, leaving the interface up to the designers necessities. VII. CONCLUSION In this work, we have presented a tiny ultra low-power smart temperature sensor fully compatible with standard CMOS processes. The sensor is based on measuring the discharge time of a capacitance due to leakage currents, which has an exponential dependency with temperature. To digitize this measure, a specic time-to-digital converter has been designed based on a logarithmic counter. The resulting sensor is characterized by extremely low power and area (1.0565.5 nW at 5 samples/s and ) outperforming previous works more than 85% as 10250 far as area and power consumption are concerned.

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The proposed sensor has been extensively characterized by Monte Carlo simulations performing an in depth analysis of resolution, sensitivity, and process variations. All these characteristics make the sensor specially suitable for dynamic temperature management applications, where a large number of smart temperature sensors must be allocated in the silicon to accurately sense on-chip temperature in order to balance or equally distribute possible on-chip hot spots.

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[17] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol. 12, no. 2, pp. 131139, 2004. [18] J. Kim, R. Trzcinski, J. Plouchart, and M. Kim, Adjustable on-chip sub-capacitor design, wO Patent WO/2007/134,904, Nov. 29, 2007. [19] M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, A CMOS smart temperature sensor with a 3 inaccuracy of 0:1 C from 55 C to 125 C, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 28052815, Dec. 2005. [20] A. Bakker and J. H. Huijsing, Micropower CMOS temperature sensor with digital output, IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 933937, Jul. 1996. [21] A. Bakker and J. Huijsing, A low-cost high-accuracy CMOS smart temperature sensor, in Proc. 25th Eur. Solid-State Circuits Conf., ESSCIRC99, 1999, pp. 302305. [22] M. Tuthill, A switched-current, switched-capacitor temperature sensor in0. 6- m CMOS, IEEE J. Solid-State Circuits, , vol. 33, no. 7, pp. 11171122, 1998. [23] W. Zhao and Y. Cao, New generation of predictive technology model for sub-45 nm design exploration, in Proc. 7th Int. Symp. Quality Electron. Design, ISQED06, 2006, pp. 585590.

Pablo Ituero (S06) received the M.S. degree in telecommunications with a major in electronics from the Universidad Politcnica de Madrid, Spain, in 2005 and the M.S. degree in electrical engineering, specialized in system-on-a-chip design from the Royal Institute of Technology, Stockholm, Sweden, in 2005. He is currently working towards the Ph.D. degree at the Department of Electronic Engineering, Universidad Politcnica de Madrid. His research interests include high-performance processor architectures and low-power, thermal-aware electronic design.

Jos L. Ayala (M98) received the Ph.D. degree (suma cum laude) in electrical engineering from the Politcnica University of Madrid, Spain, in 2005. He is an Associate Researcher at the Complutense University of Madrid. He also holds a visiting researcher position at the Ecole Polytechnique Federale de Lausanne (EPFL). His research interests are in the design of energy and temperature-efcient architectures, from multiprocessor systems-on-chip to smart sensors. From there, his research interests have spread into the eld of thermal modeling, power-aware compilation, and 3-D integration techniques. Dr. Ayala is a member of the Technical Committee of the IEEE Council on Electronic Design Automation (IEEE CEDA).

Marisa Lpez-Vallejo (M00) received the M.S. and Ph.D. degrees from the Universidad Politcnica de Madrid, Spain, in 1993 and 1999, respectively. She is an Associate Professor in the Department of Electronic Engineering, Universidad Politcnica de Madrid. She was with Bell Laboratories, Lucent Technologies as a member of the technical staff. Her research activity is currently focused on low-power and temperature-aware design, CAD for hardware/software codesign of embedded systems, and application-specic high-performance programmable architectures.