Analog Calibration of Channel Mismatches in Time-Interleaved ADCs

Pieter Harpe, Hans Hegt, Arthur van Roermund

Mixed-signal Microelectronics Group, Eindhoven University of Technology, Eindhoven, The Netherlands, email: p.j.a.harpe@tue.nl

Abstract This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADCs. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

I. I NTRODUCTION Time-interleaving multiple analog-to-digital converters (ADCs) [1] is a widely used approach to accommodate the demand for higher sampling rates combined with high accuracy and low power consumption. For example, in g. 1 p parallel ADCs, each with a separate track-and-hold (T&H) circuit, are combined to compose a p times faster ADC.
fs/p T&H 1 ADC 1 Combine

Vin

T&H 2

ADC 2

N-bit @ fs

T&H p

ADC p

Fig. 1.

N -bit p-channel time-interleaved ADC.

Matching errors (which are mainly offsets, gain errors and time-skew errors [2]) between the ideally identical channels limit the performance of the overall ADC, and should be small enough to achieve the nal speed/accuracy target. However, especially for high sampling rates and a large amount of channels p, it is difcult to achieve sufcient matching by design alone. Therefore, solutions were developed that can improve the channel-matching by measuring and correcting the actual errors on-chip (e.g. [3], [4], [5], [6], [7]). Several distinct properties can be found within the currently available techniques, but most of them share one or more of the following disadvantages or limitations:
This work is sponsored by Stichting Technische Wetenschappen.

The method works only for a subset of the three types of mismatch (offsets, gain errors and time-skew errors). The method puts constraints on the input signal (background techniques), or requires input signals with specic accuracy requirements (foreground techniques). The method works only for a 2-channel ADC, or the complexity increases strongly (i.e. faster than a linear increase) as a function of the number of channels. The complexity (and hence the power consumption) of the correction method is such that it becomes unattractive for a power-efcient implementation. The method is based on stochastics and therefore requires a large amount of observations or iterations to achieve a certain level of accuracy. Because of these drawbacks, a new method is proposed here that measures and corrects for offsets, gain errors and time-skew errors. The presented foreground method uses a deterministic test-signal, of which the accuracy and dynamic performance are unimportant, as long as the signal is periodic. Because of the deterministicity, fast convergence of the algorithm is achieved, while the implementation is simple because of the low constraints. The method is implemented in such a way that it can be applied to any number p of parallel channels, without increasing the complexity. Furthermore, the actual correction is performed by means of analog calibration and does not consume additional power. The paper is composed as follows: section II introduces the time-interleaved ADC system, including the test-signal generator and the algorithms for detection and correction of matching errors, followed by simulation results in section III. Finally, conclusions are drawn in section IV.

II. C HANNEL M ISMATCH C ALIBRATION A. System Overview Fig. 2 shows an overview of the setup used to detect and to correct for the mismatch errors in a time-interleaved ADC. A digital signal generator is used to generate a deterministic and periodic test signal, that is applied to the ADC by means of a DAC. The ADC is a p-channel time-interleaved ADC (as in g. 1), of which the gain, offset and time-skew can be adjusted by means of digitally controllable analog parameters. A digital processing block is used to estimate the individual mismatches, and to control the analog parameters in order to

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minimize these errors iteratively. In the subsequent sections, the test-signal generation, the error detection and the correction will be discussed.
test-signal generation on-chip DAC time-int. ADC processing

can be determined separately. Because of this, the channelmismatch information now also becomes available for each channel separately, which simplies the detection algorithm that will be discussed next.
0 Normalized power (dB)

r[n]

Fig. 2.

Detection and correction of channel mismatch errors.

-5 s[n] -10

B. Test-Signal Generation In the presented setup, an on-chip signal generator is used to provide the ADC with a test-signal. By observing the resulting digital response of the ADC, the detection algorithm is able to determine estimations of the offsets, gain-errors and time-skews of the different channels of the ADC. Various input signals (sinusoids, white noise, etc.) could be used as an input signal within the given setup, but here a specic choice has been made to base the input signal on a pseudorandom maximum-length sequence (MLS) [8], because of several benecial properties: An MLS sequence has a wide frequency spectrum (up to the Nyquist frequency), such that the response will be sensitive to time-skew errors. Moreover, the wide spectrum prevents that the system will be optimized for one specic frequency only, which could be the case with a single sinusoidal input signal. An MLS sequence is always periodic, therefore, averaging of multiple measurements is possible if necessary. The hardware implementation is simple. Then, an on-chip DAC is used to convert the sequence to the analog domain. As the DAC will be used as well for other correction methods, presented before in [9], [10], it was designed as a 16-bit sub-binary scaled DAC, with an intrinsic accuracy of less than 6-bit [11]. A 16-bit serial-in parallel-out shift register is used to generate a 16-bit signal s[n] driving the DAC, based on the MLS signal r[n]: each sample moment, the bits in s[n] are shifted one position, and a new bit from r[n] is added: s[n]15:1 s[n]0 = = s[n 1]14:0 r[n] (1)

-15 0 0.1 0.2 0.3 Frequency (relative to Fs) 0.4 0.5

Fig. 3.
1 0.8 0.6 0.4 0.2 0 -0.2

Normalized power spectrum of r[n] and s[n].

Normalized autocorrelation

r[n] s[n] 0 10 20 30 40 Time shift tau 50 60

Fig. 4.

Normalized autocorrelation function for r[n] and s[n].

C. Channel Mismatch Detection The goal of the mismatch detection algorithm is to nd for each ADC channel i estimations for the offset, gain and timeskew error (denoted by Oi , Gi and i , respectively), based on the measured output responses ui [n], such that the feedback algorithm can optimize the overall performance iteratively. Because of the iterative procedure, absolute accuracy of the estimations is not of extreme importance. Note that the length of each response equals the period length m of the original input signal s[n], and that for the detection algorithm, s[n] and the exact waveform produced by the DAC (including mismatches and dynamic behaviour) are unknown signals. Nevertheless, correct estimations can be made by comparing the responses ui [n] with each other. First of all, a single reference channel is chosen arbitrarily (e.g. i = 1 is used throughout this paper), against which the other channels will be compared. This means that Oi , Gi and i will be determined and calibrated relative to channel 1, which is sufcient to minimize the mismatches. Considering the static errors (offset and gain error) rst, one can write (as u1 [n] is assumed to be the ideal response): ui [n] = Oi + Gi u1 [n] , (3)

The shift-register operation inuences the frequency spectrum and the autocorrelation of the signal, but the properties mentioned before remain valid. Figures 3 and 4 show for both r[n] and s[n] the frequency spectrum and the autocorrelation function, respectively. Note that the MLS order M equals 6 in these examples, resulting in a sequence length m of: m = 2M 1 = 63 (2)

When m is chosen relatively prime to the number of channels p, after m p sample moments, each symbol of the sequence s[n] will have been applied exactly once to each channel of the ADC. By reordering the output data, the response ui [n] of each individual channel i of the ADC to the digital input signal s[n]

237

D [tau]

where Oi denotes the actual offset and Gi the actual gain of channel i, relative to channel 1. As for any MLS-generated sequence the DC component tends to go to zero (see g. 3), the offset can be estimated by the average difference between u1 [n] and ui [n]: 1 Oi = m
m1 n=0

0.01

+100ps +10ps +1ps -1ps -10ps -100ps

ui [n]

m1 n=0

u1 [n]

(4)

based on which the gain can be estimated by substituting Oi = Oi in (3), and averaging over the m samples: 1 Gi = m
m1 n=0

-0.01

ui [n] Oi u1 [n]

10

20

(5)

30 40 Time shift tau

50

60

Fig. 5.

D[ ] for various time-skews (1ps, 10ps and 100ps).

100 80

For the estimation of the time-skew error, we use the property that the output signal of the DAC is a time-continuous signal, with a certain settling behaviour around the code transitions. Because of this, a slight time-skew error i of an ADC channel results in a change of the measured response ui [n]. To detect this change in ui [n], crosscorrelation is used: R1,i [ ] is dened as the crosscorrelation between channel 1 and channel i, where the offset and gain of channel i are already corrected by means of the previously estimated values: R1,i [ ] =
m1 n=0

Estimated time-skew error (ps)

60 40 20 0 -20 -40 -60 -80 -100 -100

u1 [n]

ui [n + ] Oi Gi

(6)

-50 0 50 Actual time-skew error (ps)

100

In case channel i is perfectly matched, R1,i [ ] will be equal to the autocorrelation of channel 1: R1,1 [ ]. Hence, the difference Di [ ] will be related to the time-skew error i : Di [ ] = R1,i [ ] R1,1 [ ] (7)

Fig. 6.

Estimated time-skew as a function of the actual time-skew.

D. Analog Mismatch Correction For the actual correction of the offsets, gain errors and timeskew errors, each T&H contains three digitally controllable analog components. With these three parameters gain, offset and timing of each channel can be adjusted. For correction of offset and gain, two programmable current sources (IA,i and IB,i ) are implemented in the T&H as presented in [10]. For the timing correction, a clock-buffer with programmable delay (i ) is included in the chain driving the sampling switch of the T&H. The resolutions of the three controllable parameters were chosen such that the post-correction accuracy of the system can achieve 10-bit accuracy for a 2-channel timeinterleaved ADC operating at fs = 1GSPS. As in [10], the parameter-update functions are simple linear combinations of the error estimations: IA,i [k ] = IA,i [k 1] c1 Gi [k ] c2 Oi [k ] IB,i [k ] = IB,i [k 1] c1 Gi [k ] + c2 Oi [k ] , [k ] = i [k 1] + c3 i [k ] i (9) where c1 , c2 and c3 are constants, and k indicates the iteration of the feedback algorithm. III. S IMULATION R ESULTS To verify the presented channel-mismatch calibration method, simulations were carried out on a transistor-level implementation (in a CMOS0.18m technology) of a 2-channel

The behaviour of Di [ ] as a function of the time-skew i will be dependent on the actual DAC, its transition behaviour and the T&H used in the system. Nevertheless, it is to be expected that in any case, Di [ ] will have a linear relation with the time-skew as long as the time-skew is small enough. This was veried by means of a realistic transistor-level simulation of a DAC and a 2-channel T&H system. The sample frequency of the DAC and the T&H was set to fs = 100MSPS, and various time-skews (1ps, 10ps and 100ps) were added to channel 2 of the T&H. Fig. 5 shows the results for D2 [ ], based on the simulated responses ui [n]. The time-skew i is estimated by a partial summation of D2 [ ]:
15

i = C

Di [ ]
=0

(8)

where C is a constant chosen based on simulated results. Fig. 6 shows the resulting estimation i as a function of i . It appears indeed that the magnitude of D2 [ ] and hence also i are approximately linear functions of the actual time-skew. Note that, as mentioned before, the absolute accuracy of the estimations (4), (5) and (8) is not of extreme importance, because of the iterative error-optimization procedure.

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time-interleaved T&H structure, operating at fs = 1GSPS. A 2-channel system was selected to minimize simulation time, but the method could have been applied equally well to an ADC with more than 2 channels. The THD of a single T&H is around -62dB, limiting the overall performance to 10-bit at most. The quantizers were implemented with ideal 12-bit ADCs, with a full-scale range of Vpp = 1V. First of all, the following combination of mismatch errors was applied to one channel of the ADC: O2 = 1.6mV, G2 = 1.0064 and 2 = 30ps. This set of errors was chosen as they correspond to 8-bit performance while operating at fs = 100MSPS, which is a realistic performance for an intrinsic circuit without 347 correction. Applying a sinusoid with frequency 1024 fs yields the output spectrum of g. 7. The distortion components of the T&H (HD3 and HD5) can be seen as well as the tones due to channel mismatch: a tone at DC due to the offset mismatch, and a second tone due to gain and time-skew mismatch. In this case, the time-skew mismatch is dominant, limiting the overall linearity of the ADC to 29.7dB.
0 -20 Relative power (dB) -40 -60 -80 -100 -120 -Gain/Time-skew 29.7dB -Offset 49.9dB -HD3 64.6dB -HD5 64.6dB Fundamental signal

of the parameters, it will be possible to further reduce the distortion components arising from channel mismatch.
0 -20 Relative power (dB) -40 -60 -80 -100 -120 -Gain/Time-skew 62.5dB -Offset 71.8dB -HD3 62.2dB -HD5 64.6dB Fundamental signal

0.1

0.2 0.3 Frequency (GHz)

0.4

0.5

Fig. 8.

Output power spectrum for the corrected 2-channel ADC.

IV. C ONCLUSION In this paper, a method was presented to measure and correct for offset, gain and time-skew errors in time-interleaved ADCs using a single integrated algorithm. By measuring the response of each individual channel as opposed to measuring the combined response of all channels, the complexity of the error detection algorithm remains constant for any number of channels. The actual correction is performed in the analog domain in such a way that no additional power is consumed. Simulations on a transistor-level implementation working at 1GSPS show that the SFDR improves by almost 30dB within 11 iterations of the algorithm. R EFERENCES
[1] W. C. Black and D. A. Hodges, Time interleaved converter arrays, IEEE J. Solid-State Circuits, vol. 15, no. 12, pp. 1022 1029, Dec. 1980. [2] C. Vogel and H. Johansson, Time-interleaved analog-to-digital converters: Status and future directions, in proc. IEEE ISCAS 2006, May 21 24, 2006, pp. 3386 3389. [3] K. C. Dyer et al., An analog background calibration technique for timeinterleaved analog-to-digital converters, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1912 1919, Dec. 1998. [4] H. Johansson and P. L owenborg, Reconstruction of nonuniformly sampled bandlimited signals by means of digital fractional delay lters, IEEE Trans. Signal Processing, vol. 50, no. 11, pp. 2757 2767, Nov. 2002. [5] S. M. Jamal et al., Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter, IEEE Trans. Circuits Syst. I, vol. 51, no. 1, pp. 130 139, Jan. 2004. [6] C. Vogel, D. Draxelmayr, and F. Kuttner, Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning, in proc. IEEE MWSCAS 2004, pp. 341 344. [7] C. Vogel, D. Draxelmayr, and G. Kubin, Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters, in proc. IEEE ISCAS 2005, 2005, pp. 1394 1397. [8] S. W. Golomb, Shift Register Sequences. Holden-Day, Inc., 1967. [9] P. Harpe, A. Zanikopoulos, H. Hegt, and A. van Roermund, Digital post-correction of front-end track-and-hold circuits in ADCs, in proc. IEEE ISCAS 2006, May 21 24, 2006, pp. 1503 1506. [10] P. Harpe, A. Zanikopoulos, H. Hegt, and A. van Roermund, Analog calibration of mismatches in an open-loop track-and-hold circuit for time-interleaved ADCs, in proc. IEEE ISCAS 2007, May 27 30, 2007. [11] P. J. A. Harpe, J. M. de Meulmeester, J. A. Hegt, and A. H. M. van Roermund, Novel digital pre-correction method for mismatch in DACs with built-in self-measurement, in proc. IEE ADDA 2005, July 25 27, 2005, pp. 25 30.

0.1

0.2 0.3 Frequency (GHz)

0.4

0.5

Fig. 7.

Output power spectrum for the uncorrected 2-channel ADC.

Next, according to the theory presented in this paper, the self-measurement and self-correction algorithms were applied to the ADC. For this purpose, a transistor-level implementation of a DAC (with an intrinsic accuracy of only 6-bit) was used as a test-signal generator. As the sample frequency of the DAC was limited to 100MSPS, during this calibration phase the time-interleaved ADC was also set to operate at fs = 100MSPS. After 11 iterations of the algorithm, the performance of the ADC was veried again. For this purpose, fs was set back to the original value of 1GSPS. The output power spectrum after correction is visualized in g. 8. It can be seen that the distortion components HD3 and HD5 of the T&H remain almost constant, which should be the case, as they are not inuenced by the channel mismatch correction. The distortion components due to offset and gain/time-skew were reduced to -71.8dB and -62.5dB, respectively. As a result, the overall linearity of the ADC improves from 29.7dB to 57.8dB. Based on the nal performance, the post-correction matching accuracy can be derived, yielding O2 = 0.08mV, G2 = 1.0012 and 2 = 0.4ps. The achieved post-correction accuracy is limited by the resolution of the analog parameters. By increasing the resolution

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