Embedded Systems Design with Platform FPGAs Principles & Practices

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Embedded Systems Design with Platform FPGAs

Principles & Practices
Ron Sass and Andrew G. Schmidt http://www.rcs.uncc.edu/rsass University of North Carolina at Charlotte Spring 2011
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C h a p t e r 2 T h e Ta r g e t
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Chapter 2 Learning Objectives
Topics
from transistors to programmable logic to Platform FPGAs writing VHDL for Platform FPGAs Platform FPGA properties from HDL to a bitstream
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Big Picture
a little knowledge can be a very bad thing
often, a very reasonable and legitimate specication written in an HDL language produces a horrible FPGA design despite the efforts of many very talented researchers, high-level synthesis is imperfect real-world consequence: write HDL idiomatically
make conscious effort to think about the end result:

when I write this ... the synthesis tool sees this ... and, ultimately, this is what is implemented ...
Result: must have intimate details of FPGAs structures
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Transistors
FPGAs rely up CMOS transistors important to understand their construct and functionality improves design decisions making for better designs NMOS/PMOS/CMOS transistors
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Transistors
focus on use as a voltage-controlled switch Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
created from 2-D regions in a slab of silicon substrate constructed with excess of positive or negative charge a layer of silicon dioxide placed over substrate to insulate it from metal layer placed above silicon dioxide
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N-Channel MOSFET
Source
Gate
Drain
Drain
Gate (a) (b)
Source
(a) an NMOS transistor in silicon substrate (b) schematic of NMOS transistor
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N-Channel MOSFET
VDD VDD VDD Output VDD
Output Output Input Input Input Input Input Input
(a)
(b)
(c)
an NMOS (a) NAND gate (b) NOR gate (c) AND gate
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P-Channel MOSFET
Source
Gate
Drain
Drain
Gate (a) (b)
Source
(a) an PMOS transistor in silicon substrate (b) schematic of PMOS transistor
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Inverter
VDD
Output Input
schematic symbol of an NMOS inverter
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Complimentary MOS (CMOS) Transistor
combine NMOS and PMOS transistor in steady-stead no appreciable current is owing rule-of-thumb: most energy in a design is consumed when a CMOS gate is changing state
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CMOS NAND
VDD
Output Input
Input
simple CMOS NAND circuit

Embedded Systems Design with Platform FPGAs 12/ 71
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Programmable Logic Devices
p- and n-type location/functionality xed at fabrication how to build devices to be congured after fabrication? need a structure capable of implementing arbitrary combinational circuits, a storage cell (memory), and a mechanism to connect these resources.
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Programmable Logic Arrays
sum-of-products formulation of a Boolean function array of multi-input AND gates array of multi-input OR gates device programmed by breaking unwanted connections at the inputs to the AND and OR gates for manufacturing reasons, approach fell out of favor
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PLA device organization
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Programmable Logic Arrays
PLA functionality increased to include: memory elements, such as D-type Flip-Flops a MUX
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Adding storage to a PLA logic cell:

From PAL array
D CLK
Select
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Complex Programmable Logic Devices
PLAs with routing networks:
Switch Box
Switch Box
Switch Box
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Field-Programmable Gate Array
Modern FPGA consists of: a 2-D array of programmable logic blocks, xed-function blocks, and routing resources implemented in CMOS technology
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Function generators
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Function Generators Example

SRAM Cells 1 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 xy z 1 0 1 0 1 0 1 1 x y z (a) (b) 3-input function generator in (A) truth table and (B) look-up table form for 0 1 0 1 0 1 1 0 1 2 3 8-to-1 4 MUX 5 m l s 7 s b b 6 f
f (x , y , z ) = xy + z
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Function Generators
To generalize, basic n-input function generator consists of: a 2n -to-1 multiplexer (MUX) 2n SRAM (static random access memory) cells i.e. a 3-LUT is a 3-input function generator 4-LUTs and 6-LUTs are more common (3-LUTs are easier to draw by hand!)
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Function Generators
What about more complex functions? use multiple LUTs function decomposed into sub-functions sub-function has subset of inputs each sub-function assigned to one LUT LUTs combined via routing resources to form function
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To congure the FPGA:
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Storage Elements
Most circuits need: function generators (LUTs) storage elements (ip-ops) Can now create sequential circuits!
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Logic Cells
A logic cell combines:
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Logic Cells
low-level building block upon which FPGA designs are built combinational/sequential logic built from logic cells used to compare capacity of different FPGA devices slice
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Logic Blocks
A logic block
combines:
Congurable Logic Block
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Logic Blocks
A switch box is:
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Taken all together, a high-level structure of a simple FPGA:
Logic block Logic cell LUT Logic cell LUT FF FF Switch matrix Logic block Logic cell LUT Logic cell LUT FF FF Switch matrix
Logic block Logic cell LUT Logic cell LUT FF FF
Logic block Logic cell LUT Logic cell LUT FF FF
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Special-Purpose Function Blocks
FPGAs combine programmable logic with additional resources embedded into FPGA fabric. Why? embedded resources consume less resources embedded resources consume less power embedded resources can operate at a higher frequency
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Special-Purpose Function Blocks
Such as: Block RAM Digital Signal Processing Blocks Processors Digital Clock Manager Multi-Gigabit Transceivers
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Block RAM
many designs require use of on-chip memory possible to use using logic cells to build memory elements logic resources quickly consumed as demand grows Block RAM
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Digital Signal Processing Blocks
Digital signal processing (DSP) quickly consumes resources: implement necessary components in FPGA fabric:
multiplier accumulator adder bitwise logical operations (AND, OR, NOT, NAND, etc.)
combine DSP blocks to perform larger operations:

single/double precision oating point addition, subtraction, multiplication division, and square-root
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Processors
Simplify designs, reducing resource and power consumption IBM PowerPC 405 and 440 (in Virtex 4 and 5 FX FPGAs, respectively) conventional RISC processors implement PowerPC instruction set no hardware oating point functions level-1 instruction and data caches memory management unit translation look-aside buffer can connect to FPGA fabric through system bus not all FPGAs have embedded processors
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Digital Clock Manager
How to support designs with multiple clock domains? Digital Clock Manager (DCM): generate different clocks from a reference clock divide reference clock clocks have lower jitter and phase relationship
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Multi-Gigabit Transceivers
High Speed Serial Transceivers are devices that:
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Platform FPGA
Block RAM DSP DCM/PLL/IOBs
Processor blocks I/O & IOBs Ethernet PCIe MGTs
I/O & IOBs
Logic blocks
Block RAM
DSP
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Writing HDL for Platform FPGAs
Assume you are moderately familiar with HDL (VHDL or Verilog) Question: how to write HDL for FPGAs? Answer: Carefully! when writing HDL be careful, not everything is synthesizable briey cover VHDL next
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VHSIC Hardware Description Language

describe digital circuits major styles of writing VHDL: Structural circuits described as logic/function units (AND/OR/NOT, etc.) and signals Data-Flow type of structural has syntactic support to make expressing Boolean logic easier Behavioral circuits use imperative language to describe how outputs relate to inputs via a process a third style is a mix between structural and behavioral behavioral form of VHDL most convenient for programmers structural is useful for black box designs
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VHDL Syntax
entity declaration: describes the components interface followed by one or more declared architectures: the implementation of the interface best to learn by example
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1-bit Full Adder in VHDL

l i b r a r y ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; e n t i t y f a d d e r i s port ( a , b : in s t d _ l o g i c ; cin : in s t d _ l o g i c ; sum : out s t d _ l o g i c ; c o u t : out s t d _ l o g i c ) ; end f a d d e r ; a r c h i t e c t u r e beh of f a d d e r i s begin sum <= a xor b xor c i n ; c o u t <= ( a and b ) or ( b and c i n ) or ( a and c i n ) ; end beh ;
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2-bit Adder in VHDL (1/3)

l i b r a r y ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; e n t i t y f a d d e r 2 b i t i s port ( a , b : i n s t d _ l o g i c _ v e c t o r ( 1 downto 0 ) ; cin : in s t d _ l o g i c ; clk : in s t d _ l o g i c ; rst : in s t d _ l o g i c ; sum : out s t d _ l o g i c _ v e c t o r ( 1 downto 0 ) ; c o u t : out s t d _ l o g i c ) ; end f a d d e r 2 b i t ; a r c h i t e c t u r e beh of f a d d e r 2 b i t i s 2 b i t R e g i s t e r D e c l a r a t i o n f o r A , B , Sum s i g n a l a_reg , b_reg , sum_reg : s t d _ l o g i c _ v e c t o r ( 1 downto 0 ) ; 1 b i t R e g i s t e r D e c l a r a t i o n f o r Cin , Cout signal cin_reg , cout_reg : std_logic ; 1 b i t I n t e r n a l s i g n a l t o connect c a r r y o u t t o c a r r y i n s i g n a l carry_tmp : std_logic ; 1 b i t F u l l Adder Component D e c l a r a t i o n component f a d d e r i s port ( a , b : in s t d _ l o g i c ; cin : in s t d _ l o g i c ; sum : out s t d _ l o g i c ; c o u t : out s t d _ l o g i c ) ; end component f a d d e r ;
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begin VHDL Process t o R e g i s t e r I n p u t s A , B and Cin r e g i s t e r _ p r o c : process ( c l k ) i s begin i f ( ( c l k event ) and ( c l k = 1 ) ) then Synchronous Reset i f ( r s t = 1 ) then I n i t i a l i z e Input Registers a_reg <= " 00 " ; b_reg <= " 00 " ; c i n _ r e g <= 0 ; I n i t i a l i z e Outputs sum <= " 00 " ; cout <= 0 ; else Register Inputs a_reg <= a ; b_reg <= b ; c i n _ r e g <= c i n ; R e g i s t e r Outputs sum <= sum_reg ; cout <= c o u t _ r e g ; end i f ; end i f ; end process r e g i s t e r _ p r o c ;
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I n s t a n t i a t e B i t 1 o f F u l l Adder f a 1 : f a d d e r port map ( a => a_reg ( 1 ) , b => b_reg ( 1 ) , c i n => carry_tmp , sum => sum_reg ( 1 ) , c o u t => c o u t _ r e g ) ; I n s t a n t i a t e B i t 0 o f F u l l Adder f a 0 : f a d d e r port map ( a => a_reg ( 0 ) , b => b_reg ( 0 ) , c i n => c i n _ r e g , sum => sum_reg ( 0 ) , c o u t => carry_tmp ) ; end beh ;
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Finite State Machines in VHDL
useful for a variety of purposes writing style can result in different netlists recommended to follow synthesis guide (i.e. Xilinx Synthesis Technology (XST) User Guide) simple 8-bit Adder with FSM example
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8-bit Adder in VHDL with FSM (1/4)

T r a d i t i o n a l L i b r a r y and Packages used i n a hardware core l i b r a r y ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; use i e e e . s t d _ l o g i c _ a r i t h . a l l ; use i e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t y adderFSM i s generic ( C_DWIDTH : i n port ( a, b : in a_we , b_we : i n clk , r s t : in result : out valid : out end adderFSM ;
natural := 8 ) ; s t d _ l o g i c _ v e c t o r (C_DWIDTH 1 downto 0 ) ; std_logic ; std_logic ; s t d _ l o g i c _ v e c t o r ( 7 downto 0 ) ; std_logic ) ;
a r c h i t e c t u r e beh of adderFSM i s 8 b i t R e g i s t e r / Next D e c l a r a t i o n f o r A and B s i g n a l a_reg , b_reg : s t d _ l o g i c _ v e c t o r ( 7 downto 0 ) ; s i g n a l a_next , b_next : s t d _ l o g i c _ v e c t o r ( 7 downto 0 ) ; F i n i t e S t a t e Machine Type D e c l a r a t i o n type FSM_TYPE i s ( wait_a_b , wait_a , wait_b , add_a_b ) ; I n t e r n a l s i g n a l s t o r e p r e s e n t t h e C u r r e n t S t a t e ( fsm_cs ) and t h e Next S t a t e ( fsm_ns ) o f t h e s t a t e machine s i g n a l fsm_cs : FSM_TYPE : = wait_a_b ; s i g n a l fsm_ns : FSM_TYPE : = wait_a_b ;
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begin F i n i t e S t a t e Machine Process t o R e g i s t e r S i g n a l s f s m _ r e g i s t e r _ p r o c : process ( c l k ) i s begin R i s i n g Edge Clock t o i n f e r F l i p Flops i f ( ( c l k event ) and ( c l k = 1 ) ) then Synchronous Reset / Return t o I n i t i a l S t a t e i f ( r s t = 1 ) then a_reg <= ( others => 0 ) ; b_reg <= ( others => 0 ) ; fsm_cs <= wait_a_b ; else a_reg <= a_next ; b_reg <= b_next ; fsm_cs <= fsm_ns ; end i f ; end i f ; end process f s m _ r e g i s t e r _ p r o c ;
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F i n i t e S t a t e Machine Process f o r Combination L o g i c f s m _ l o g i c _ p r o c : process ( fsm_cs , a , b , a_we , b_we , a_reg , b_reg ) i s begin I n f e r F l i p Flop r a t h e r than Latches a_next <= a_reg ; b_next <= b_reg ; fsm_ns <= fsm_cs ; case ( fsm_cs ) i s S t a t e 0 : Wait f o r e i t h e r A o r B I n p u t denoted by a_we = 1 and / o r b_we = 1 when wait_a_b => C l e a r I n i t i a l Context o f R e g i s t e r s / Outputs a_next <= ( others => 0 ) ; b_next <= ( others => 0 ) ; result <= ( others => 0 ) ; valid <= 0 ; i f ( ( a_we and b_we ) = 1 ) then a_next <= a ; b_next <= b ; fsm_ns <= add_a_b ; e l s i f ( a_we = 1 ) then a_next <= a ; fsm_ns <= w a i t _ b ; e l s i f ( b_we = 1 ) then b_next <= b ; fsm_ns <= w a i t _ a ; end i f ;
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S t a t e 1 : Wait f o r A I n p u t Being i n t h i s s t a t e means B a l r e a d y a r r i v e d when w a i t _ a => result <= ( others => 0 ) ; valid <= 0 ; i f ( a_we = 1 ) then a_next <= a ; fsm_ns <= add_a_b ; end i f ; S t a t e 2 : Wait f o r B I n p u t Being i n t h i s s t a t e means A a l r e a d y a r r i v e when w a i t _ b => result <= ( others => 0 ) ; valid <= 0 ; i f ( b_we = 1 ) then b_next <= b ; fsm_ns <= add_a_b ; end i f ; S t a t e 3 : Perform Add O p e r a t i on and r e t u r n t o wait_a_b when add_a_b => result <= a_reg + b_reg ; valid <= 1 ; fsm_ns <= wait_a_b ; end case ; end process f s m _ l o g i c _ p r o c ; end beh ;
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Sequential Logic Diagram
Input signals
Combinational logic function
R E G
Registered output signals Unregistered output signals
VHDL: fsm_logic_proc fsm_cs signal State register function VHDL: fsm_register_proc fsm_ns signal
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From HDL to Bitstream

Overview of process: synthesis the process of generating the logic conguration for the specied device from HDL source netlist is a computer representation of the a collection of logic units and how they are to be connected mapping (also known as map) the process of grouping gates and assigning functionality to FPGA primitives placement after map the next step in the back-end tool ow is to assign the FPGA primitives in the netlist to specic blocks on a particular FPGA
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From HDL to Bitstream

Overview of process: routing (also known as route) is the process after placement where during which wire segments are selected and passing transistors are set bitgen the process after routing which takes a placed and routed netlist and sets generates a conguration le known as a bitstream that will be used to congure the FPGA device bitstream is the le that includes a header and frames of conguration information needed to set the SRAM cells of the FPGA in order to set the functionality of the device
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Xilinx Synthesis Process

HDL source (VHDL or verilog) .vhd/.v
Project file (list of source) .prj
xst
Xilinx netlist .ngc
Synthesis script .xst
Synthesis report .srp
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Xilinx Synthesis Process
User constraints file .ucf
Standard netlists .edif ngd build Xilinx database netlist .ngd map Native circuit description .ncd par Mapped NCD _map.ngd
Xilinx netlist .ngc
Build report Relatively-placed (hard) macros .nmc .bld
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From HDL to Conguration Bitstream
Lets start with an example, consider the Boolean function: f (w , x , y , z ) = w + x + yz

z y x w G0 G1 G2 f
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Circuit expressed in a netlist. Nets describe how the cells are wired up each gate becomes a cell each primitive cell includes:
type of gate a name for this cell and a set of ports
ports have names and direction complex cells formed with instances of cells and nets hierarchy formed from complex cells with top-level cell encompassing all other cells top-level port cells associated with external pins of FPGA
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Excerpt of netlist:
(edif gates (edifVersion 2 0 0) (external UNISIMS (cell LUT4 (cellType GENERIC) (interface (port I0 (direction INPUT) ) (port I1 (direction INPUT) ) (port I2 (direction INPUT) ) (port I3 (direction INPUT) ) (port O (direction OUTPUT) ) ) ) ) )
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Digital circuit to sequence of bits using previous example: with 4-inputs, cannot implement f in a single 3-LUT solution: two 3-LUTs and routing resources f can be decomposed into two functions:
f (w , x , y , z ) = f2 (w , f1 (x , y , z )) f1 (x , y , z ) = x + yz f2 (w , t ) = w + t
now f1 and f2 can be used to congure two 3-LUTs the output of f1 is routed to the second input of f2
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Example of a 4-input function mapped to two 3-LUTs:

z y x w o G0 G1 G2 f 3-LUT 3-LUT
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After generating the netlist: mapping after MAP another netlist is generated cells now refer to FPGA primitives (LUTs,FFs, etc.)
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After MAP: placement our example, f uses two 3-LUTs during placement tools decide which two 3-LUTs to use and add that information to the netlist try to place cells close by for lowest propagation delay routing place and route often combined and called PAR
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G1 w (zy) x
z y x w 1 3LUT FF 0 1 1 3LUT FF
illustration of f (w , x , y , z ) placed and routed
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After PAR, nal step: convert SRAM cell settings into a linear stream of bits imagine all cells arrayed into two dimensions one column might be some 3-LUTs on the chip the column actually is all SRAM cells of 3-LUTs all columns SRAM cells form giant shift register bitgen
bitstream
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1st bit in bitstream (n+1)th bit 3-LUT 0 0 0 1 1 1 1 1 3-LUT 0 1 1 1 1 1 1 1 nth bit in bitstream 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Last bit in bitstream
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Chapter-In-Review
transistors: NMOS,PMOS,CMOS programmable logic devices writing VHDL for Platform FPGAs Platform FPGA properties from HDL to a bitstream
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Chapter 2 Terms
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Chapter 2 Terms
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Chapter 2 Terms
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Embedded Systems Design with Platform FPGAs Principles & Practices

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The Target

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Chapter 2 Learning Objectives

Embedded Systems Design with Platform FPGAs

make conscious effort to think about the end result:

Result: must have intimate details of FPGAs structures

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Gate (a) (b)

(a) an NMOS transistor in silicon substrate (b) schematic of NMOS transistor

Embedded Systems Design with Platform FPGAs

Output Output Input Input Input Input Input Input

Embedded Systems Design with Platform FPGAs

Gate (a) (b)

(a) an PMOS transistor in silicon substrate (b) schematic of PMOS transistor

Embedded Systems Design with Platform FPGAs

schematic symbol of an NMOS inverter

Embedded Systems Design with Platform FPGAs

Complimentary MOS (CMOS) Transistor

Embedded Systems Design with Platform FPGAs

simple CMOS NAND circuit

Programmable Logic Devices

Embedded Systems Design with Platform FPGAs

Programmable Logic Arrays

Embedded Systems Design with Platform FPGAs

Programmable Logic Devices

PLA device organization

Embedded Systems Design with Platform FPGAs

Programmable Logic Arrays

Embedded Systems Design with Platform FPGAs

Programmable Logic Devices

Adding storage to a PLA logic cell:

Embedded Systems Design with Platform FPGAs

Complex Programmable Logic Devices

PLAs with routing networks:

Embedded Systems Design with Platform FPGAs

Field-Programmable Gate Array

Embedded Systems Design with Platform FPGAs

Field-Programmable Gate Array

Embedded Systems Design with Platform FPGAs

Function Generators Example

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Field-Programmable Gate Array

To congure the FPGA:

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

A logic cell combines:

Embedded Systems Design with Platform FPGAs

Embedded Systems Design with Platform FPGAs

Congurable Logic Block

Embedded Systems Design with Platform FPGAs

A switch box is:

Embedded Systems Design with Platform FPGAs

Field-Programmable Gate Array

Logic block Logic cell LUT Logic cell LUT FF FF

Logic block Logic cell LUT Logic cell LUT FF FF

Embedded Systems Design with Platform FPGAs

Special-Purpose Function Blocks