8085 P

AMIE: EC 405 Microprocessor & Microcontrollers
8085 P
Features, Signal description
8085 features:

8085 is an 8-bit microprocessor. It is capable of addressing 64kbytes of memory. It requires a +5volts of power supply. 8085 operates on 3MHz clock. 8085 A-2 operates on maximum clock frequency 5MHz. It has 16 address lines, out of which 8 address lines are multiplexed with data lines. It is manufactured in NMOS technology It is available in 40 pin dual in line (DIP) package.
8085 Pin diagram:
Composed by Anish Chib for AMIE & Engineering Students

anish.chib@gmail.com, http://linuxbyanish.wordpress.com
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8085 Signal Description:
Address & data lines: Address bus: 8085 has 16-bit address bus AD0-AD7 and A8-A15. In this lower address bus is multiplexed with data bus. A8-A15 lines are unidirectional and AD0-AD7 lines are bidirectional. Data bus: AD7-AD0 is 8-bit bidirectional data bus. It is multiplexed with lower order address bus. ALE: Address latch enable. It is used to de-multiplex AD0-AD7. It is connected to strobe input of latch which is used to separate address and data bus lines. It is issued in first T-state. Control & Status Signals: RD: Read control signal is issued to memory or IO device to read data from it. WR: Write control signal is issued to memory or IO device to write data into it. IO/M: It is a signal which is used to distinguish between IO operation and memory operation. It is also used in generating memory and IO, read and write control signals. S1, S0: these are status signals. Depending on the value on these lines, the type of operation being performed by the processor can be determined. Below table shows that information.

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Power Supply and clock signals: Vcc: +5v power supply line Vss: electrical ground signal. X1, X2: crystal is connected between these pins. The frequency is internally divided by 2. The systems operates generally at 3MHz. Hence 6 MHz clock signal needs to be connected between X1, X2 lines. CLK (out): It is the clock output signal from processor, which can be used to clock other peripherals in the microprocessor based system. READY: This is used when the processor is reading or writing data to a slow peripheral. When this signal goes low processor inserts wait states, until it goes high. Reset Signals: RESET IN: when low signal is applied on this pin, 8085 resets and the microprocessor boots from 0000h location in memory i.e. PC is loaded with 0000h location. RESET OUT: when processor is reset, this signal goes high. This pin is connected to reset input of other peripherals. So when processor is reset, other peripherals are also reset. Serial IO lines: SID: serial input data, used to receive serial data. SOD: serial output data, used to send serial data Interrupt Signals: INTR: interrupt request is general purpose interrupt signal. The interrupting device needs to send the vector address also. INTA: is interrupt acknowledging signal. This signal indicates that processor has accepted the interrupt. RST7.5, RST6.5, RST5.5: These are external vectored interrupts. When these interrupt occurs, processor vectors to a specific location. TRAP: It is a non-mask able interrupt. DMA signals: HOLD: This line is used by DMA controller to request microprocessor for system bus. When this line goes high microprocessor completes its current bus cycle and issues system bus to DMA controller. HLDA: HOLD acknowledging signal. Processor acknowledges DMA request using this signal.

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8085 Architecture
below figure shows the architecture of 8085 microprocessor.
The following are the different blocks in the 8085 processor. ALU: it is 8-bit ALU. It can perform arithmetic and logical operations on 8-bit data. If an operation needs to be performed on 16-bit data, it needs to be broken into two 8-bit parts and each 8-bit operation should be performed on each 8-bit data. It takes operand inputs from accumulator and a temporary register. Result of the operation is stored in accumulator. Depending on the result of operation, flags in flag register values will be changed. Flag register: As already explained contents of flag register will be changed according to the result of ALU operation. Below figure shows the flag register format of 8085.
Sign flag (S): when the result of ALU operation is negative sign flag is set. If the result is positive, then sign flag is reset. i. e. the D7 bit of accumulator is copied into the sign flag, as D7 anyhow contains sign. Zero flag (Z): when the result of ALU operation is zero, Zero flag is set. If the result is nonzero then flag is reset. Auxiliary carry (AC): If an ALU operation results in carry from lower nibble to upper nibble (or) bit D3 to bit D4, Auxiliary flag is set. Else it is reset. This flag is used in BCD arithmetic.
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Parity flag (P): If the result contains even number of ones, the flag is set else it is reset. So the parity flag is odd parity bit. Carry flag (CY): If the arithmetic operation results in carry, CY flag is set, else it is reset. Timing and Control unit: This is responsible for generation of control signals, such as RD, WR to interface peripherals. It also synchronizes all microprocessor operations. Instruction Register and Decoding: Instruction register holds instruction that is fetched from memory. Instruction decoder decodes the opcode (which is part of fetched instruction present in instruction register). Instruction register is not accessible to the programmer. Register Array:
8085 has six general purpose registers B, C, D, E, H, L. They can be used as pairs to hold 16bit data as BC, DE, HL. Accumulator is 8-bit register which holds the results of operations as well as operand on which some operation needs to be performed. Flag register contains five flags, namely S, Z, CY, AC, P flags. 8085 has two 16- bit register PC, SP. PC always consists of address of next instruction to be executed. SP always points to top of stack. i.e. address of top memory location of stack. Stack is a data structure. It is used to store return addresses whenever call to subprograms or an interrupt occurs. Two temporary registers W, Z are also present. These are used to hold temporary results during execution. But these are not accessible to the user. Incrementer and decrementer address latch is for incrementing the PC content for every fetch cycle. Interrupt Controller: 8085 has 5 external interrupts. TRAP, INTR, RST 5.5, RST 6.5, and RST 7.5. Whenever processor gets interrupt it finishes current instruction execution and issues INTA (interrupt acknowledge) signal to the peripheral which raised the interrupt and goes to execute interrupt service routine. Interrupt controller controls the interrupts. Serial I/O control: Serial data can be sent out using SOD pin and serial data can be read from SID pin. It controls serial IO related operations.

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8085 based micrcomputer system
Since 8085 is a microprocessor, it does not consist of on chip memory for program as well as data and also it doesnt have I/O ports to interface external peripherals. All these extra ICs need to be connected to processor. 8085 has lower order address bus multiplexed with data bus as already explained. So to get separate address as well as data bus, they need to be de-multiplexed. To do this 8085 provides ALE (address latch enable) signal. 8085 Asserts ALE signal and issues address of memory location or peripheral during first T-state in any machine cycle. An external octal latch (8282 or 74373) can be used for doing this de-multiplexing. Latch has data input as multiplexed address bus and latch enable signal is connected to ALE signal. So when ALE is asserted by processor latch is enabled and holds the data input content into latch is the address asserted by processor. So output of latch is Address bus (lower order, and higher order address bus is provided by processor). Ad0-AD7 pins cab be directly used as data bus. If the data bus needs to drive multiple devices i.e. more peripherals then external bus drivers or bus buffers are required. They are optional depending on no. of peripherals and their driving current. So they are shown as optional by using dotted lines in the above figure. 8085 issues RD, WR, M/IO control signals. But we require separate signal for reading and writing into memory or IO device. So some extra logic circuit is required for getting individual control signals for memory and IO devices (IOR, IOW, MEMR, MEMW). To store the program as well as data external memory is required. For storing program ROM or EPROM or EEPROM or flash is required. And storing data, RAM is required. For accessing them some address decoding circuitry, which can be implemented using NAND gates or 3 to 8 decoder like 74138 can be used. However this occupies large space on the board. So programmable logic devices like PAL can be used, which occupies very less board space. Data bus, Address bus and control buses combined are called System bus. To access external IO devices IO ports are required, So Programmable peripheral interface chip is required. For serial communication a UART chip is required and for handling the devices on interrupt basis a programmable interrupt controller is required. So this requires around 10-12 chips along with the 8085 processor to completely build a microcomputer system using a processor like 8085. This results in a very large sized board. So this type of design is made
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only when computing requirement is very high. For control dominated applications microcontroller based system can be used as their board size is very less and low cost. Of course todays microcontrollers have extremely high computing power.
8085 bus timings and machine cycles

Before continuing with bus timings and various machine cycles, Let us concentrate on what an instruction is and what are machine cycles and what is T-state. An instruction is a command given to processor to perform some data processing task. An instruction consists of Opcode and operand information (may be immediate data, or reference to operand). Opcode describes what operation needs to be performed by processor. To execute each instruction processor requires some machine cycles. These machine cycles are some basic processing steps to finish an instruction execution. For example to execute an instruction opcode needs to be fetched from memory and then data need to be read from memory. These kinds of operations are called machine cycles. To perform each machine cycle processor requires some no. of T-states. In each T-state microprocessor perform some micro operation of each machine cycle. For example to fetch opcode, processor needs to issue address to memory, and issue read signal, and opcode needs to be stored in instruction register from data bus, All these are some micro operations To perform these operations processor requires some T-states. 8085 microprocessor performs following machine cycles as a whole. All the instructions may not require all the machine cycles. 1. 2. 3. 4. 5. 6. 7. 8. 9. Opcode fetch Memory read Memory write I/O read I/O write Interrupt acknowledge Halt Hold Reset
Opcode Fetch Machine Cycle:

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Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085 fetches opcode of instruction. The following are the sequence of actions that are performed by 8085 to fetch an opcode from memory. This machine cycle consists of 4 T-states.
8085 places 16-bit address from PC on to the address bus (of course lower order address bus is multiplexed with data bus) and issues ALE pulse in first T-state (T1). This is used to de-multiplex the address and data bus. It also issues IO/M signal to 0. This indicates that processor is performing memory related operation. In second T-state (T2) processor issues RD control signal to memory. This enables memory to put data present at the address location given in previous T-state on to data bus. RD control signal is active for two clock pulses. In T3 state memory places opcode on Data bus. Processor reads opcode present on data bus and de-asserts RD signal. Thus data bus goes into high impedance state. In T4 state processor decodes instruction and necessary actions are performed.
Memory Read and Write, IO Read and write Machine cycles

Memory Read machine cycle: This machine cycle is required when an operand is present in memory. This machine cycle requires three T-states. The following are the sequence of actions performed by microprocessor during this machine cycle.

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In the first T-state (T1) 8085 places address on address bus and issues ALE signal. And also IO/M signal is made low, since it is memory related operation. In the second T-state (T2), processor issues RD control signal to memory. In response to this memory places data on data bus. In the third T-state (T3), processor reads data from data bus, and de-asserts RD signal.
Memory Write Machine cycle: This machine cycle is required when the results of operation needs to store in memory. This machine cycle requires three T-states. The following are sequence of actions performed by processor in this machine cycle.

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In first T-state (T1), 8085 processor places 16- bit address on address bus and issues ALE signal. And also it makes IO/M signal to low, indicating it is memory related operation. In second T-state (T2), processor places data to be written on data bus and asserts WR signal to the memory. In the third T-state (T3), memory stores the data and processor de-asserts WR signal.
IO read machine cycle: This machine cycle is required, when data needs to be read from an input device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle.

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In the first T-state (T1) 8085 places port address(for IO mapped addresses port address is 8-bit, but for memory mapped addresses IO device address is 16-bit, but reading from such is performed by memory read machine cycle) on address bus and issues ALE signal. And also IO/M signal is made high, since it is IO related operation. In the second T-state (T2), processor issues RD control signal to IO peripheral. In response to this input device places data on data bus. In the third T-state (T3), processor reads data from data bus, and de-asserts RD signal.
IO write Machine cycle: This machine cycle is required when data needs to be output to an output device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle.
In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO mapped addresses port address is 8-bit, but for memory mapped addresses, IO device address is 16-bit, but writing to such is performed by memory write machine cycle) and issues ALE signal. And also it makes IO/M signal to high, indicating it is IO related operation. In second T-state (T2), processor places data to be written on data bus and asserts WR signal to the peripheral. In the third T-state (T3), peripheral accepts the data and processor de-asserts WR signal.

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Memory interfacing to 8085

8085 has 16 bit address bus; hence it can access 216 no. of memory locations, which is equal to 64KB memory. For any microprocessor memory is required to store program as well as data. Since microprocessor doesnt have on-chip memory, we need to connect it externally. So it requires addressing mechanism. The following are the steps involved in interfacing memory with 8085 processor.
1. First decide the size of memory requires to be interfaced. Depending on this we can say how many address lines are required for it. For example if you want to interface 4KB (212) memory it requires 12 address lines. Remaining address lines can be used in address decoding. 2. Depending on the size of memory required and given address range, construct address decoding circuitry. This address decoding circuitry can be implemented with NAND gates and/or decoders or using PAL (when board size is a constraint). 3. Connect data bus of memory to processor data bus. 4. Generate the control signals required for memory using IO/M, WR, RD signals of 8085 processor. Example: Interface 4KB memory to 8085 with starting address A000H. 1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has 16 address lines. Hence four of address lines are used for address decoding 2. Given that starting address for memory is A000H. So for 4KB memory ending address becomes A000H+0FFFH (4KB) = AFFFH.
A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 are used for generating chip select signal for memory chip. Address decoding circuit using 3X8 decoder:

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A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to 74X138 chip as inputs. When theses lines are 010 output should be 0. This is provided at O2 pin of 74X138 chip. Address decoding circuit using only NAND gates:
A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this is as shown above. Types of address decoding: There are two types of address decoding mechanism, based on address lines used for generating chip select signal. 1. Absolute decoding 2. Partial decoding Absolute decoding: All the higher order lines of microprocessor, left after using the required signals for memory are completely used for generating chip select signal as shown in above example. This type of decoding is called absolute decoding. Partial decoding: Only some of the address lines of microprocessor left after using the required signals for memory are used for generating chip select signal. Because of this multiple address ranges will be formed. If total memory space is not required for the system then, this type of
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address decoding can be used. The advantage of this technique is fewer components are required for memory interfacing because of this board size reduces and in turn cost reduces. Example: Connect 512 bytes of memory to 8085 1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directly connect to address bus of memory. 2. In the remaining A9-A15 for example only A15-A12 are used for generating chip select signal. A11-A9 are dont care signals.
Because of the dont care signals the address range can be 0000 to 01FF 0200 to 03FF 0400 to 05FF 0600 to 07FF 0800 to 09FF 0A00 to 0BFF 0C00 to 0DFF 0E00 to 0FFF Address decoding circuit:
IO interfacing to 8085

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There are two techniques through which devices can be interfaced to microprocessor. 1. Memory mapped I/O 2. Peripheral mapped I/O or I/O mapped I/O Memory mapped I/O: I/O devices are interfaced using address from memory space. That means IO device address are part of addresses given to memory locations.8085 uses 16-bit address to memory interfacing. So any address between 0000H-FFFFH can be given to each peripheral. But the addresses given to peripheral cant be used for memory. Memory control signals are used as read and write control signals for peripherals. And all the operations that can be performed on memory can also be performed on peripherals. No need of using IO instructions such as IN, OUT. IO mapped IO: In this method separate address space is given to IO devices. Each IO device is given a 8-bit address. Hence maximum 256 devices can be interfaced to the processor. The address range for the IO devices is 00H-FFH. IO control signals are used to perform read, write operations. For reading data from IO device or writing data to IO device IN, OUT instructions needs to be used. Arithmetic and logical operations cant be performed directly on IO devices as in memory mapped IO. IO devices can be interfaced, by using buffers for simple IO i.e. by using address decoding circuit to enable buffer. For handshake IO or to interface more peripherals ICs like 8255 peripheral programmable interface (PPI) can be used.
8085 addressing modes

Addressing modes define the way operands are specified in the instruction. In 8085 there are four addressing modes. 1.immediate addressing mode 2.register addressing mode 3.direct addressing mode 4.indirect addressing mode immediate addressing mode: in this operand is specified in the instruction it self. Example: MVI A,55H Register addressing mode: in this addressing mode operand is stored in a register. And that register is specified in the instruction Example: MOV C,A direct addressing mode: Operand is stored in the memory. The address of operand is specified in the instruction. Example: IN 10H
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indirect addressing mode: Operand is stored in the memory. The address of operand is held in a register and the register is specified in the instruction. Example: LXI H,1020H MOV A,M ; indirect addressing mode Here M points to(contains) address 1020H, At his address operand is stored. By executing this instruction, the content of 1020H is loaded into accumulator A
8085 data transfer instructions

Algorithm is step by step procedure for solving a problem. Flow chart is pictorial representation of algorithm. Program is defined as set of instructions written in sequence. Data transfer instructions: These instructions copy the contents from source location to destination location. These instructions does not affect any flags. The following are different types of data transfer instructions. 1. Move immediate MVI Rd, data transfers 'data' value into register Rd. Ex: MVI A,50H 2. Move instruction MOV Rd,Rs here Rd is destination register, Rs is source register. Transfers data in Rs into Rd. Rs content will not be changed. Ex: MOV B,A 3.IN instruction IN port_address this instructions reads data from IO device connected at specified port address and loads accumulator with that data. Ex: IN 10H 4.OUT instruction OUT port_address This instruction sends content of accumulator to IO device connected at specified port address. Ex: OUT 05H 5.LXI instruction LXI Rp,data This instruction loads 16-bit immediate data into specified register pair(Rp) LXI B,16-bit data ; loads BC with 16-bit data LXI D, 16-bit data; loads DE with 16-bit data LXI H,16-bit data; loads HL with 16-bit data LXI SP, 16-bit data; loads stack pointer with immediate data
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Ex: LXI H,2050H LXI SP,1090H 6.LDAX instruction-Load accumulator indirect LDAX B/D This instruction loads Accumulator with memory location pointed by content of B or D LDAX B; loads accumulator with content of memory location pointed by BC pair LDAX D; loads accumulator with content of memory location pointed by DE pair 7.LDA instruction-Load accumulator direct LDA 16-bit address This instruction loads accumulator with the content of memory location specified in the instruction. Ex: LDA 2005H this instruction loads accumulator with content of [2005H] 8.STAX instruction-Store accumulator indirect STAX B/D This instruction stores the content of accumulator into memory location pointed by B or D register pair. Ex: STAX B; stores accumulator content in memory location pointed by BC pair STAX D; stores accumulator content in memory location pointed by DE pair 9.STA instruction-Store accumulator direct STA 16-bit address This instruction stores accumulator content in 16-bit address location specified in the instruction Ex: STA 1020H; stores accumulator content in 1020H address
8085 arithmetic instructions

1.ADD instruction-Addition instruction ADD R; A=A+R ADD M; A=A+[HL] This instruction performs addition of content of specified register or memory location pointed by register pair HL and stores the result in accumulator Ex: ADD B; A=A+B 2.ADI instruction- Add immediate data ADI data This instruction adds 8-bit data to accumulator and places the result in accumulator 3.SUB instruction subtract SUB R; A=A-R SUB M; A=A-[HL] This instruction subtracts content of register R or content of memory location pointed by HL register pair from accumulator and stores the result in accumulator.
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4. SUI instruction- subtract immediate data SUI data this instruction subtracts 8-bit data from accumulator and stores the result in accumulator 5.INR instruction- increments 8-bit data INR R; increments register R content by 1. INR M; increments content of memory location pointed by HL register pair by 1 This instruction operates on 8-bit data 6.DCR instruction- decrements 8-bit data DCR R; decrements register R content by 1 DCR M; decrements content of memory location pointed by HL register pair by 1 This instruction operates on 8-bit data 7.INX instruction- increments 16-bit data INX Rp; increments register pair Rp INX B; increments register pair BC INX D; increments register pair DE INX H; increments register pair HL INX SP; increments stack pointer SP by 1 This instruction increments 16-bit data by 1
8.DCX instruction- decrements 16-bit data DCX Rp; decrements register pair Rp DCX B; decrements register pair BC DCX D; decrements register pair DE DCX H; decrements register pair HL DCX SP; decrements stack pointer SP by 1 This instruction decrements 16-bit data by 1
8085 Logical instructions

Flags affected: After preforming these instructions carry flag will reset(except CMA) and sign, zero, parity flags are affected and these flags status depends on the result present in accumulator. 1.ANA instruction-logical And with accumulator ANA R this instructions performs bit wise AND operation between content of specified register and the accumulator and stores the result in accumulator. 2.ANI instruction-logical AND immediate data with accumulator ANA 8-bit data This instruction performs bit wise AND operation between 8-bit immediate data and accumulator content and stores the result in accumulator
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3.ORA instruction-logical OR with accumulator ORA R This instruction performs bit wise OR operation between content of accumulator and specified register and stores result in accumulator. 4.ORI instruction-logical OR with immediate data ORI 8-bit data This instruction performs bit wise OR operation between content of accumulator and 8-bit immediate data specified in the instruction and stores the result in accumulator. 5.XRA instruction-logical exclusive OR operation with accumulator XRA R This instruction performs bit wise exclusive OR operation between content of accumulator and specified register in the instruction and stores the result in accumulator. 6.XRI instruction-Logical exclusive OR with 8-bit data XRI 8-bit data This instruction performs bit wise logical exclusive OR between immediate data and accumulator and stores the result in accumulator. 7.CMA instruction-complement accumulator This instruction performs bit wise inversion of content of accumulator and result will be stored in accumulator. 8.RLC instruction-rotate accumulator left This instruction rotates left the content of accumulator by one bit. The MSB of accumulator is shifted out and copied into LSB. Copy of MSB is kept in carry flag also.
9.RAL instruction-rotate accumulator left through carry This instruction rotates left the content of accumulator along with carry by one bit. This instruction shifts the MSB of accumulator out and copies it into carry flag and content of carry flag is stored in LSB.
10.RRC instruction- rotate accumulator right This instruction rotates the content of accumulator right by one bit. This instruction shifts the LSB of accumulator out and copies that into MSB. Copy of LSB is also stored in the carry flag

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11.RAR instruction- rotate accumulator right through carry This instruction rotates the content of accumulator through carry right by one bit. This instruction shifts the LSB of accumulator out and copies it into carry and content of carry is stored in the MSB.
12.CMP instruction- compare with accumulator CMP R ; compare the content of specified register R with accumulator CMP M ; compare content of memory location pointed by HL register pair with accumulator. Depending on the content of R or M carry flag and zero flag are affected. This in turn subtracts content of R/M from accumulator but result is not stored any where, only flags are affected ACC < R/M CY flag is set, Z flag is reset ACC = R/M - CY flag is reset, Z flag is set ACC > R/M CY is reset, Z flag is reset 13.CPI instruction- compare immediate data with accumulator CPI 8-bit data This instruction compares 8-bit data with the content of accumulator( this in turn subtracts 8bit data from accumulator but result is not stored any where, only flags are affected). Depending on the content Carry flag and Zero flag are affected. ACC < 8-bit data CY flag is set, Z flag is reset ACC = 8-bit data - CY flag is reset, Z flag is set ACC > 8-bit data CY is reset, Z flag is reset
8085 Branch, Stack related and Machine control instructions

Branch operations: unconditional branch JMP 16-bit This instruction causes PC to load with the 16-bit address specified in the instruction unconditionally. So the Processor jumps for executing from the address location specified in the instruction. Conditional jump instructions: This instructions jumps to the specified location in the instruction depending on the certain conditions indicated by flags. Except AC(auxiliary carry) remaining flags are used for decision making in these conditional branch instructions 1.JC 16-bit ; jump if carry(if CY=1) 2.JNC 16-bit ; jump if no carry(if CY=0) 3.JZ 16-bit ;jump if zero(if Z=1) 4.JNZ 16-bit ; jump if no zero(if Z=0) 5.JP 16-bit ; jump if positive(if S=0) 6.JM 16-bit ; jump if minus(if S=1)
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7.JPE 16-bit ; jump on even parity(if P=1) 8.JPO 16-bit ; jump on odd parity(if P=0)
unconditional CALL instruction: Subroutines can be implemented using CALL instruction. Subroutines are a way for code reuse. When it is required to perform certain operations more frequently then those operations can be written as a subroutine. Whenever those operations are required simply call the subroutine. CALL 16-bit This instruction causes processor to start executing from the specified location in the instruction. When this instruction is executed processor stores the PC content on the stack and decrements the stack pointer by 2. It loads PC with 16-bit address specified in the instruction. Unconditional RET instruction: This instruction is used to return from the subroutine. When this instruction is executed by the processor it copies the top of stack into PC and increments the stack pointer by 2. Conditional CALL instruction: This instruction calls the subroutine depending on the certain conditions indicated by flags. CC call subroutine if CY=1(Call if carry) CNC call subroutine if CY=0(call if no carry) CZ call subroutine if Z=1(call if zero) CNZ call subroutine if Z=0(call if no zero) CM call subroutine if S=1(call if minus) CP call subroutine if S=0(call if plus) CPE call subroutine if P=1(call if even parity) CPO call subroutine if P=0(call if odd parity) Conditional RET instruction: This instruction returns from the subroutine depending certain conditions indicated by flags. RC return if CY=1(Return on carry) RNC return if CY=0(return on no carry) RZ return if Z=0(return on zero) RNZ - return if Z=1(return on no zero) RM return if S=1(return on minus) RP return if S=0(return on plus) RPE return if P=1(return on even parity) RPO return if P=0(return on odd parity) Restart instructions: RST n These instructions are like software interrupts to 8085. When these instructions are executed processor vectors(jumps) to a specific location called restart location. The following list gives restart location for different RST instructions. 'n' value -- Vector location RST 0 -- 0000H
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RST 1 -- 0008H RST 2 -- 0010H RST 3 -- 0018H RST 4 -- 0020H RST 5 -- 0028H RST 6 -- 0030H RST 7 -- 0038H To get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is 0018H. Stack related instructions: PUSH instruction: PUSH Rp This instruction stores the content of register pair Rp(16-bit) into stack. Stack is Last in first out data structure. Example: PUSH B; push BC pair on to stack PUSH D; push DE pair on to stack PUSH H; push HL pair on to stack PUSH PSW; push PSW(Accumulator+Flag register) on to stack When this instruction is executed by the processor first it decrements SP by 1 and stores higher byte of the specified register pair, Then it again decrements SP by 1 and stores lower byte of the specified register pair. SP always points to top of stack. 8085 Maintains a stack which grows downwards .i.e. Higher address to lower address. And SP points to already stored location. POP instruction: POP Rp This instruction is used to retrieve data from stack. i.e. Is 16-bit data from top of stack is stored in the specified register pair. Example: POP B; store data from top of stack in BC pair POP D; store data from top of stack in DE pair POP H; store data from top of stack in HL pair POP PSW; store data from top of stack in Accumulator and Flag register When this instruction is executed by the processor, it copies a byte from top of stack into lower byte of register pair and increments SP by 1, Then it again copies a byte from top of stack into higher byte of the register pair specified in the instruction and increments SP by 1. Machine control instructions: HLT instruction Halt When this instruction is executed by the processor it stops executing and enters into wait state. Address and data bus of the processor are kept in high impedance state. NOP instruction No operation This instructions performs nothing except wasting processor time. This instruction is used for writing delays.

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EI instruction- Enable interrupts This instruction is used to enable the interrupts DI instruction- disable interrupts This instruction is used to disable the interrupts
8085 interrupts
An interrupt is a signal or condition that causes processor to stop its normal execution flow and makes it to jump to some other location for processing the interrupt. 8085 has 4 mask-able interrupts and 1 non-mask-able interrupts. Mask able interrupts can be disabled be DI instruction. Among four mask-able interrupts one is non-vectored interrupt, that is processor cannot go to a fixed location as in case of vectored interrupt, the external device which caused interrupts needs to specify the vector address. 8085 interrupt response process: interrupts should be enabled by using EI instruction, then only processor responds to all mask able interrupts.

When microprocessor is executing a program, it checks for INTR line during execution of each instruction. If INTR is high then processor completes executing the current instruction, disables the interrupts and sends a INTA signal INTA is used by the external hardware to specify the restart instruction to processor( since INTR is a non-vectored interrupt). When microprocessor receives the RST instruction, it saves PC content on stack and PC is loaded with the vector address. Microprocessor executes the instructions at vector address. The interrupts should be enabled if required in the ISR(interrupt service routine) At the end of interrupt service routine, RET instruction loads the PC from the stack. So processor comes back to the instruction where it was interrupted previously.
Restart instructions: RST n These instructions are like software interrupts to 8085. When these instructions are executed processor vectors(jumps) to a specific location called restart location. The following list gives restart location for different RST instructions. 'n' value -- Vector location -- hex code RST 0 -- 0000H -- C7 RST 1 -- 0008H -- CF RST 2 -- 0010H -- D7 RST 3 -- 0018H -- DF RST 4 -- 0020H -- E7 RST 5 -- 0028H -- EF
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RST 6 -- 0030H --F7 RST 7 -- 0038H --FF To get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is 0018H. 8085 has 5 external interrupts. As already mentioned in this 4 are vectored interrupts and 1 is non-vectored interrupt. RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored interrupt. TRAP is a non mask able interrupt.
Interrupt Priority: when more than one interrupts occur at the same time, then processor responds to them according to the following priority TRAP(highest) RST 7.5 RST 6.5 RST 5.5 INTR (lowest) Interrupt vector locations: TRAP 0024H(it is same as RST 4.5) RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH To get the vector location for RST interrupts, interrupt value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 5.5 instruction, multiply 5.5*8=44. 44 in hexadecimal notation is 2CH. So vector address is 002CH. Trigger levels: TRAP is level and edge triggered RST 7.5 is positive edge triggered RST 6.5, RST 5.5 are level triggered. Masking of interrupts: SIM instruction sets mask pattern for RST 5.5, RST 6.5, RST 7.5. SIM instructions reads accumulator bit pattern and accordingly masks the interrupts. The bit pattern is shown in below figure. It also resets D flip-flop of RST 7.5 interrupt. And it also implements serial I/O.

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Reading pending interrupts: RIM instruction is used to read pending interrupts. After executing this instruction accumulator is loaded with the interrupt status signals. The pattern is shown in below figure. This instruction is also used to receive serial data.

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Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work. Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor. The processor will check the interrupts always at the 2nd Tstate of last machine cycle. If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral. The vectored address of particular interrupt is stored in program counter. The processor executes an interrupt service routine (ISR) addressed in program counter. It returned to main program by RET instruction.
INTERRUPT STRUCTURE
Types of Interrupts: It supports two types of interrupts.

Hardware Software
Software interrupts:
The software interrupts are program instructions. These instructions are inserted at desired locations in a program. The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows. Interrupt number * 8 = vector address For RST 5,5 * 8 = 40 = 28H Vector address for interrupt RST 5 is 0028H

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The Table shows the vector addresses of all interrupts.

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Hardware Interrupts Hardware interrupts:
An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts (1) (2) (3) (4) (5) TRAP RST 7.5 RST 6.5 RST 5.5 INTR
TRAP: This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

TRAP bas the highest priority and vectored interrupt. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged. In sudden power failure, it executes a ISR and send the data from main memory to backup memory. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). There are two ways to clear TRAP interrupt.

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1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal) RST 7.5:

The RST 7.5 interrupt is a maskable interrupt. It has the second highest priority. It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized. Maskable interrupt. It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization of interrupt.
Enabled by EI instruction.
RST 6.5 and 5.5:
The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized. Maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.
Enabled by EI instruction. The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:
INTR is a maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.

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Enabled by EI instruction. Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR. It has lowest priority. It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state until it recognized.
The following sequence of events occurs when INTR signal goes high. 1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled. 3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor. 4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.

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8085 Pin diagram:

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8085 Signal Description:

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8085 based micrcomputer system

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8085 bus timings and machine cycles

Opcode Fetch Machine Cycle:

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Memory Read and Write, IO Read and write Machine cycles

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Memory interfacing to 8085

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8085 addressing modes

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8085 data transfer instructions

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8085 arithmetic instructions

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8085 Logical instructions

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8085 Branch, Stack related and Machine control instructions

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AMIE: EC 405 Microprocessor & Microcontrollers

AMIE: EC 405 Microprocessor & Microcontrollers

Composed by Anish Chib for AMIE & Engineering Students

AMIE: EC 405 Microprocessor & Microcontrollers

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AMIE: EC 405 Microprocessor & Microcontrollers

Composed by Anish Chib for AMIE & Engineering Students

AMIE: EC 405 Microprocessor & Microcontrollers

Types of Interrupts: It supports two types of interrupts.

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AMIE: EC 405 Microprocessor & Microcontrollers

The Table shows the vector addresses of all interrupts.

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AMIE: EC 405 Microprocessor & Microcontrollers

Hardware Interrupts Hardware interrupts:

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