Вы находитесь на странице: 1из 4

A Novel High Efficiency and Linearity Power Amplifier with Over-Voltage Protection

Haitao Zhang 1,2, Huai GaoI, Yintat Ma3, Andy Forbes2, Ray Pavio2 and Guann-Pyng Li'
1.Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697
2. TriQuint Semiconductor, 2 Executive Drive, Chelmsford, MA 01824 3. Rockwell Scientific Company, 1049 Camino Dos Rios, Thousand Oaks, CA 91360

Abstract This paper presents a power amplifier (PA) design to improve linearity by using a novel power cell compensating the main nonlinear sources from the power devices and to improve the overall efficiency by a dynamic DC biasing circuit. An overvoltage protection circuit to ease output mismatch induced problems is included in this PA design. As a case study, this power amplifier is implemented with InGaP/GaAs HBT operating at 1880MHz. The CDMA standard is used to evaluate its linearity and efficiency. The P1dB is improved from 3OdBm to 32dBm and the cumulated output current is much improved in a wide output power range. The ACPR and ALTR at 28dBm output power level are improved by 5dB and 12dB with the novel PA respectively. The over-voltage protection circuit works well under output mismatch conditions. Index Terms - MMIC power amplifiers, nonlinear distortion, over-voltage protection, load mismatch protection, heterojunction bipolar transistors, monolithic microwave integrated circuits.

I. INTRODUCTION

In many transceivers of portable communication systems, the power amplifier (PA) is the most power consuming block. The power amplifier should be not only efficient but also highly linear. For example, to fulfill the spectral re-growth and in-channel error vector requirements, extreme linearity is needed in the CDMA user equipment. In general, the maximum power efficiency can be achieved only when the PA is transmitting peak output power. The efficiency worsens as the output power backs off from the peak. As a result, a PA with high efficiency covering a large dynamic power range is strongly in need. Some existing techniques to improve efficiency, such as Class E PA, Doherty PA and Envelope Elimination and Restoration(EER) [1-2], suffer from the linearity, narrow bandwidth or complicated digital circuit design, which limits their applications in the modern portable equipment. On the other hand, while several methods of onchip linearization techniques such as feedforward, feedback and predistortion[3-4] for improving the gain compression have been reported, they are facing to various degrees the issues of complexity or low efficiency. In addition to efficiency and linearity issues, RF power amplifiers are commonly subjected to a high voltage stress at the output stage, since their peak waveforms at high output power can be as high as three times the bias voltage as in the cases for power saturated power amplifier and output mismatch conditions. For the case of PAs being implemented with bipolar technology, excessive collector voltage that surpasses the transistor breakdown voltage, such as BVceo, can damage or degrade the performance of the transistor. To alleviate the excessive

voltage stress on transistors, over-voltage protection circuits [5] are worthwhile exploring for protecting this high efficiency and linearity PA without degrading its performance. In this paper, an InGaP/GaAs HBT two-stage power amplifier operating at 1880MHz is proposed and shown in Fig.l. It is consisted of the driver stage and the output stage. The driver is operating at class A, and the output stage is operating at class AB. The bias circuit is consisted of a current mirror which can provide constant current bias over a wide temperature variation. The driver stage and the output stage are parallel connected unit HBT cells. The power cell based on the composite transistor design is used in the second stage of PA to improve the linearity without sacrificing noticeable additional current consumption and chip area. As the input power varies, the power detector at the input port of the PA controls the DC biasing current of the two stages to improve the PA efficiency especially at low power operation conditions. An over-voltage protection circuit based on ESD protection circuit design is connected at the output port of the second stage of PA to ensure safe operation of the PA.
II. COMPACT COMPOSITE TRANSISTOR

It is well known that there are two major distortion attributes in HBTs: transconductance (gm) and base-collector capacitor (CBC). Illustrated in Fig.2, composite transistors, including power cell and compensation block, are designed to improve linearity with a conventional processing technology by compensating those two main nonlinear sources [6]. As the input power increases, transconductance decreases causing gain compression. Based on the concept of negative feedback in control theory, the compact composite transistors stabilize the input voltage dramatically through the BE junction of the transistor in the linearization, which boosts the average output current. Thus it will drastically decrease the nonlinearity of transconductance and the gain compression as a function of the input power. Phase distortion is largely attributed to variation of CBC during the device operating cycle over its load line. The phase distortion can be alleviated if the effective CBC is independent of the output swing. Since the emitter of HBT is heavily doped, the CBE of the HBT2 in the compensation block is independent of output power and is connected in parallel with the CBC of the output power transistors. Consequently, the effective capacitance of the linearization block can maintain a relatively constant value when the device is under large signal swing. Since both amplitude and phase distortion are alleviated by using the composite transistors, the

1-4244-0688-9/07/$20.00 C 2007 IEEE

147

Authorized licensed use limited to: ISRO - ISRO Satellite Centre. Downloaded on June 08,2010 at 11:42:28 UTC from IEEE Xplore. Restrictions apply.

PIN_ID=Input Port

linearity of the power amplifier can be improved. Moreover, as a result of current re-distribution between the compensation block and power cell, the reduction in collector current at high Vce is also effectively lessened in the composite transistor, resulting in an improved output power and power added efficiency. The overall layout penalty from the compensation
:
I

Input

Port

:2

<>Resistor

Fig. 2.
4.5

The schematic of composite transistor

3.5

0.5

-15

-10

.'v~
Fig. 1.
O

NET="Biasing Network"

El

3 NET="Biasing Network'
ID=VCC

NET="Power Detector"

PIN_ID=Output Pori

NET="Input Matching Network"

NET="1st Stage"

NET="Power Detector"

NET="2nd Stage"

NET="Output Matching Network"

Schematic of a power amplifier with over voltage protection circuit

Vcc
BJT1

R3
BJT2

02
R4

> R5

mpe-nsafton
Block

Output Port

:/

Input Port

Dl

Output Port

i, Rl
~~~~Power
Cell
R2

C2

Fig. 4. The schematic of power detector

probability of demanding to transmit at the highest output


level is much lower than that at the lower power levels. To emphasize this point, the CDMA development group (CDG) curve is shown in Fig.3 as an example, illustrating that the overall efficiency is mostly controlled by the low power level efficiency. A power detector, shown in Fig.4, is inserted at the input of PA as the control circuit for the power cells, which adjusts the base biasing current based on input power level and can be implemented on the same chip as PA without suffering too much chip area penalty. RI and Cl are used as attenuator and DC block. The R2 supply the DC current path for DI and the C2 is used to filter the AC signal to ground. The rest of the components are used as the biasing circuit for Dl. As the input power increases, the current flowing through Dl will follow it because of the intrinsic DC property of the diode. As a result, the voltage at the output port of the detector will increase. It is noted that the power detector is inserted at the input rather than output port because of lower insertion loss and lowering power handling requirement being achieved in the current design of the power detector. Under this design, the power efficiency is improved over a large dynamic power range.
power

3.

CD

_uv

__

-5

5 10 Pout (dBm)

15

20

25

30

Fig..3.

CDG curve

block is less than 2% of the whole chip area.


III. POWER DETECTOR

PA is typically designed to achieve the highest efficiency only when delivering the highest output power. However, the

148
Authorized licensed use limited to: ISRO - ISRO Satellite Centre. Downloaded on June 08,2010 at 11:42:28 UTC from IEEE Xplore. Restrictions apply.

IV. OVER-VOLTAGE PROTECTION CIRCUIT

Given the facts that GaAs HBT is vulnerable to overvoltage stress, an over-voltage protection circuit is used to clip the peak voltage to prevent damaging the power amplifier during transient. An over-voltage protection circuit is basically a fast voltage-clamping device. For RF power amplifier applications, the basic requirements of over-voltage protection circuits should be low capacitance loading, low leaking current, and high output power handling capability. The over-voltage protection circuit should not affect the circuit performance under normal conditions, where the output voltage does not reach the value to turn on the protection circuit. The over-voltage protection circuit should also be compact in size that does not increase power amplifier chip area. Additionally, limiting the collector voltage with the over-voltage protection circuit not only prevents device breakdown but also avoids huge current flow through to onset collector current collapse.
M A IN

Fig. 6.

Layouts of power amplifier with composite transistors, power detector and over-voltage protection circuit V. POWER AMPLIFIER DESIGN

CIRCUIT
D3

D2

D4 R1

I
Proposed over-voltage protection circuit

rID 1 QQ00(Thk4U, ,.7f ID I power ampiiiier at IOOUsVIvTLz was and fabricated for verification of designed design concepts proposed here. Two versions of power amplifiers were fabricated. One version has the composite transistor, power detector and over-voltage protection circuit and the other is a standard two stage PA without any added on features. The layout of the first version is shown in Fig. 6, which occupies an area of Ix 0.8 mml about the same as the standard one. It is noticed that the over-voltage protection circuit does not penalize the layout area, since it is small in size and is set
S Parameters X DB(AS(P,1)1)

tA An IPPF an -inJaIr/uaAS

20 15 10

CDMAPA

CDMA PA CDMA PA

DB(AS(2,2)1)

Fig. 5.

-,ODB(IS(2,1)1)
-10
-15 -20 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
2

The proposed over-voltage protection circuit shown in Fig. 5 is based on the ESD protection circuit design concept of using a low power conducting diode string serving as a threshold trigger to turn on a high power conducting switch [5]. The basic operation principle of the protection circuit can be found elsewhere [7]. For a negative over-voltage on the pad, the reverse diode (D3) turns on and sinks the overvoltage current. For positive operating waveform, the reverse diode may not be needed. This approach is compact in size and only requires an area of 100gm x 100tm, i.e. the size of a typical bonding pad. In our design, the harmonics generation due to the voltage clamping circuit would be filtered out by the low-pass output matching network.

2.05 2.1

2.15 2.2

Frequency (GHz)

Fig. 7. S-parameters measurement result of the PA with composite transistor between the pads. The circuit is biased with 3.4V voltage source. From Fig. 7, the measured small signal gain is 17.7 dB with the composite transistor. SIt and S22 of both circuits are lower than -1OdB in frequency band of 100 MHz. Fig. 8 shows the measurement results of output power and cumulated output current as a function of the input power for the two versions of power amplifiers respectively. The measured output power at 1 dB gain compression is improved from 30 dBm to 32dBm. The cumulated output current is much decreased by using the dynamic biasing circuit. The ACPR and ALTR are evaluated

149
Authorized licensed use limited to: ISRO - ISRO Satellite Centre. Downloaded on June 08,2010 at 11:42:28 UTC from IEEE Xplore. Restrictions apply.

using CDMA modulation protocols and are illustrated in Fig. 9. They are improved by 5dB and 12 dB at 28dBm output power respectively with the new design. When the output is matched to 50 Ohm and the input power increases to 15dBm, the power amplifier is driven into power saturation. The output voltage of the PAs with and without over-voltage protection circuit shows similar saturation power, demonstrating that the over-voltage protection circuit will not affect the RF performance under matched condition. When the output terminal is under open and short conditions, and when the input power increases above 16dBm and beyond, the waveform exhibits voltage clipping below the transistor breakdown voltage. On the other hand, the PAs without protection burned out because of high output voltage.
250|

Versioni_
_ __ _ _ __ _ _ __ _

225

25

~~~~~~~~~~~~~~~~~~200
175
D150

20-

E
__

-A~~~~~~~~~~~~~~~
_125
_ _ _ _ _ _

E E aD E
U

composite transistor is used to compensate for the nonlinear sources from the power cell and the linearity of the PA is improved greatly as a result. In order to improve the overall efficiency of the PA, the power detector inserted at the input port of the PA is used to control the DC biasing current of the PA under different power levels and does not degrade the power gain of the PA. To make power amplifiers more robust at over-voltage operation conditions such as impedance mismatches, an over-voltage protection circuit is introduced successfully in the design. As a case study, an 1880 MHz InGaP/GaAs power amplifier with the over-voltage protection circuit was fabricated and measured. The PIdB is improved from 30dBm to 32dBm and the cumulated output current is much improved in a wide output power range. The ACPR and ALTR at 28dBm output power level are improved by 5dB and 12dB with the novel PA. The over-voltage protection circuit demonstrated its capability to protect this power amplifier output terminal by clamping its voltage below device breakdown voltage.
REFERENCES [1] Narisi Wang; Xinli Peng; Yousefzadeh, V.; Maksimovic, D.; Pajic, S.; Popovic, Z.; "Linearity of X-band class-E power amplifiers in EER operation," in IEEE Transactions on Microwave Theory and Techniques, Volume 53, Issue 3, Part 2, March 2005, pp.'096 1102 [2] Srirattana, N.; Raghavan, A.; Heo, D.; Allen, P.E.; Laskar, J.; Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications," in IEEE Transactions on Microwave Theory and Techniques, Volume 53, Issue 3, March 2005, pp.852- 860 [3] Peter Asbeck, G. Hanington, P.F. Chen and L.Larson, "Efficiency and linearity improvement in power amplifiers for wireless communications," in IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual , 1-4 Nov. 1998, pp.15-18 [4] Larose, C.L.; Ghannouchi, F.M.; "Optimization of feedforward amplifier power efficiency on the basis of drive statistics," in IEEE
Issue: 1 , Jan. 2003, pp.41 - 54 [5] Y. Ma, G. P. Li, "Low Loading Capacitance On-Chip ESD Protection Circuit for Telecom Integrated Circuits Implemented by Heterojunction Bipolar Transistors Technology," US pending patent # 60/349,899. [6] Huai Gao, Haitao Zhang, G.P. Li, A Compact Composite Transistor as a Novel RF Power Cell for High Linearity Power Amplifiers, IEEE Microwave and Optical Technology Letters, June 2005 [7] Y. Ma, H. Zhang, G. Li, "A Compact Over-Voltage Protection Circuit for HBT Power Amplifiers," in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2006.
,

_100

-5
__ _ _ _ _ __ _ _ _ _ _25 _ _

~~~~~~~~~~~~~~~~~~~~50

-35

-30

-25

-20

-15

-10 -5 Pin (dBm)

10

15

20

Fig. 8. Measured result of the output power and cumulated output current as a function of input power. VersionI: PA with composite transistor, power detector and over-voltage protection; version2: conventional PA.

-40 -50 -60 -70 -80 -90


14
-

4---mAl
m

-40 -50 -60 -80 -90


,

a-1

rs"Immm!JR!
16 18

-tp..Vm
20 22 24 Pout (dBm)

.-.-j
26

-70 F

Transactions on Microwave Theory and Techniques, Volume: 51

28

30

-Version 2

Fig. 9. Measurement result ACPR and ALTR as a function of output power. Versionl: PA with composite transistor, power detector and over-voltage protection; version2: conventional PA.
VI. CONCLUSION

A novel PA is designed based on composite transistor power cell, dynamic biasing, and over-voltage protection circuit. The

150
Authorized licensed use limited to: ISRO - ISRO Satellite Centre. Downloaded on June 08,2010 at 11:42:28 UTC from IEEE Xplore. Restrictions apply.