ECE Department ICA LAB

Experiment No: 5 II/IV CSE&IT (I Semester) Page 1 of 5

Study of Flip-flops using ICs

AIM: To verify the truth tables of RS flip-flop, JK flip-flop, D flip-flop, and T flipflop using ICs. APPARATUS REQUIRED: 1. Flip-flops trainer kit 2. Regulated power supply 3. Connecting wires. 4. Patch cords. Theory: The flip-flops which find wide applications are 1. RS flip-flop 2. JK flip-flop 3. D flip-flop 4. T flip-flop RS flip-flop: The basic flip-flop may be realised by across coupling two inverting gates either NAND or NOR. The truth table for this flip-flop is

The output of RS flip-flop is not effected by multiple pulses at the single input. This property can be utilised to eliminate contact bouncing of keyboard switches and to eliminate glitches in digital data which otherwise cause malfunctioning of digital circuitry.

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Experiment No: 5 Procedure: 1. Connect S, R terminals to the logic input switches. 2. Leave the clock and D inputs open. 3. Connect Q and Q` terminals to logic output indicators. 4. Set the S, R signals by means of the switches as per truth table 1. Verify the Q and Q` outputs. JK flip-flop: The JK flip-flop shown in figure 2 eliminates the indeterminate state which occurs when S = R = 1 in a clocked RS gives the truth table for JK flip-flop. II/IV CSE&IT (I Semester) Page 2 of 5

Inactive: The J and K inputs are control inputs that means they determine what the circuit will do on the positive clock edge. When J and K are low, both input gates are disabled and the circuit is inactive all time including the rising edge of the clock. Reset: When J is low and K is high, the upper gate is disabled so there is no way to set the flip-flop. The only possibility is reset. When Q is high, the lower gate passes a reset trigger as soon as the positive clock edge arrives. This forces Q to become low. Therefore J = 0 and K = 1 means that a raising clock edge resets the flip-flop. Set: When J is high and is low, the lower gate is disabled; so its impossible to reset the flip-flop as follows. When Q is low, Q` is high therefore, the upper gate passes a set trigger on the positive clock edge. This drives Q into the high state, that is, J = 1 and K= 0 means that the next positive clock edge sets the flip-flop. Toggle: When J and K are both high, it is possible to set or reset the flip-flop depending on the current state of the output. Truth table:

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Experiment No: 5 II/IV CSE&IT (I Semester) Page 3 of 5

Procedure: 1. Connect S, R, J and K terminals to the logic input switches. 2. Connect clock terminals to bounceless pulser high or low. 3. Connect Q and Q` terminals to logic output indicators. 4. Set the S, R, J and K signals by means of the switches as per truth table 2. 5. Verify the outputs. D flip-flop: This is essentially a 1-bit delay circuit. This is ideally started as a temporary store for binary information. The D flip-flop can be realised from JK flip-flop as shown in figure 3.

Truth Table:

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Experiment No: 5 II/IV CSE&IT (I Semester) Page 4 of 5

Procedure: 1. Connect S, R, and D terminals to the logic input switches. 2. Connect clock terminals to bounceless pulser high or low. 3. Connect Q and Q` terminals to logic output indicators. 4. Set the S, R, and D signals by means of the switches as per truth table 3. 5. Verify the outputs. T flip-flop: The toggle of T flip-flop is extremely important in frequency scaling down operation. When a clock pulse arrives at T input, the output of the flip-flop toggles and hence the name. Its realisation using JK flip-flop is shown in figure 4.

Truth Table:

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Experiment No: 5 II/IV CSE&IT (I Semester) Page 5 of 5

Procedure: 1. Connect S and R terminals to the logic input switches. 2. Set J and K permanently to high by means of input switches. 3. Connect clock terminal (T) to bounceless pulser high or low. 4. Connect Q and Q` terminals to logic output indicators. 5. Set the S, R signals by means of the switches as per truth table 4. 6. Verify the outputs. Result: