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******************************** layout tools can use design constraints identified during timing analysis , and simulation tools can

use the post-layout delay data

***************************************** high impedance is nothing but open-circuit , depending upon technology(nand,nor technology) , corresponding wire becomes either logic-0 orlogic-1 ********************************************** why we need to drive all inputs & inouts before reset ? just we want to conform that whether there are any x's propagating even when po rts are given Low or High Note : 1) if any one of input is z, then output of combo logic is X , so there is a chance to load X in ff , so output of ff may become as X, so we may interpet as ff is entering into high impedance . 2) Due to power and area constraints, not all storage elements in a larg e design can be reset directly; some will be reset indirectly by loading values computed from other registers t hat have been reset **************************** SDF is a file contains delays(timing info)based on fan-in,load,location(intercon nect delay) or based on wire load models. i think, if we do STA at post-synthesis(logic synthesis) level , we need to use wire-load models & technology library . if we do GLS then, also i think we need to use wire-load models for delays & tec hnology library. ****************************************** Why time borrowing ? In certain designs (particularly processor architectures), have some stages whic h are time hogs (like multiplier). The succeeding stage (say, store) hardly requires any time when compared to a mu ltiply stage. For the sake of one time hogging section of the pipeline, one cannot penalize th e entire pipeline. So, if we can borrow extra time required for the multiply stage, from the succeed

ing less time consuming store stage, we can have an efficient pipeline in terms of TIMING. ****************************************** What is Time Stealing ? Time Stealing can be deployed when a specific logic partition needs additional t ime. The additional time required, should be deterministic at the time of the design. Then one can adjust the clock phase of capture FF (FF2), so that data arrival t ime at the capture edge of FF2, will not violate setup **************************************************** Difference between Time Stealing and Time Borrowing: Time Stealing will not AUTOMATICALLY use the left over slack from previous stage . It is forced to steal from the succeeding stage, and leave less time to the succ eeding stage. It is designer s responsibility to make sure the succeeding stage delay is < CLK_P ERIOD PHASE_SHIFT. In Time Borrowing, latch transparency helps in making use of the slack left in p revious cycle ripple through the pipe automatically, without interfering with clock phases. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------What we need to check in GLS: 1) check timescale is correct or not 2) a) check PLI/DLL configurations are correct or not & clock is togging correct ly or not with respect to configurations(check duty cycle,arrival time ...) b) check the clock generation logic(e.g: gated clock), that is generating the clear clock or not(i.e phase , duty cycle,whether minimum width maintained or n ot...) 3) GLS with zero-delay mode: a) To find the filp-flops/latches which are not initialized with any values during reset/set . b) Since logic equivalence check behaves just like synthesis tool, we need to run in zero-delay mode in order to find simulation and synthesis mismatch c) To conclude that , DFT insertion is correct d) if u want to check a multicycle path/false path/asynchronosus path in ful l timing mode , run the testcase in zero delay mode to check whether this testcase is activating the required(our targeted path) path or not. Note: i) Concentrate on zero-delay loop backs, race conditions ii) Concentrate on initial values of inputs,inouts before occurence of r eset. iii) concentrate on flipflops/lathces that are not initialized with any v alues during reset/set , if any flipflop or latch is not initialized ,then we ca n a X's. see the chip initialization sequence & observe the sequence under full-timing si mulation & also in zero-delay ideal clock simulation See whether IO timings are correctly implemented or not

check whether every filpflop is initalized or not during reset condition case 1: synchronous reset all fipflops should initialize at almost same time case 2: Asynchronous reset a) reset active period is minimum(glitch) now also, all fipflops should initialize at almost same time b) reset active perios is maximum now also, all fipflops should initialize at almost same time e.g : output of one flipflop is an input to another filpflop , since first f/f g ot reset in advance , so first ff gets default value , and if data propagates faster than rese t, then system enter into different state ..

first minute verification : 1) Better to do lint , if we have RTL 2) find synchoronizers and disable the timing for synchronizers 3) replace clock port in assertions and monitors , with the clock tree 4) What should be the default value , if we want to drive the inputs before res et/set 5) check timescale correct or not 6) sta cannot find glitches ..since sta is not dynamic in nature. logic equivalence check behaves just like synthesis ....so it may not find misma tches between rtl & gate level netlist