B.

Electrical Description The 618M-3( )/4( ) is a completely solid-state vhf communications transceiver consisting of a power supply, frequency synthesizer, receiver, modulator, and transmitter. The vhf synthesizer, having only one crystal-controlled oscillator, derives accurate RF output frequencies through the use of solid-state phase lock loop and switching circuits. The vhf receiver has voltage-variable capacitors in the RF preselector to eliminate mechanical tuning. The receiver is single conversion and has a carrier-to-noise ratio and carrier override squelch. The transmitter has several stages of RF amplification that use RF broadband techniques to eliminate mechanical tuning. The modulator circuit can amplify a carbon mic or data input to the level required to amplitude modulate the transmitter. A solid-state transmit-receiver (tr) switch provides the switching speed and reliability necessary for data link operations. C. Controls and Indicators Figure 9 lists al controls and indicators and describes the function of each. SQUELCH DISABLE Pushbutton switch that disables squelch action for low signal levels. TRANSMIT POWER Indicator light that shows when transmitter output power is greater than 10 watts. PHONE jack Provides connection point for headset. MIC jack Provides connection point for microphone. Controls and Indicators Figure 9 5. Theory of Operation A. General The 618M-3/4 and 618M-3A/4A transceivers contain nearly identical circuits. The following discussion should be considered applicable to all versions of both transceivers unless otherwise noted. The 618M-3( )/4( ) theory of operation is divided into three sections: transceiver block diagram level, functional level for both receive and transmit modes, and functional level for the frequency synthesizer. B. Overall Block Diagram Theory of Operation (Refer to figure 10 for the 618M-3/4; to figure 11 for the 618M-3A/4A.) The 618M-3( )/4( ) transceiver is controlled by vhf frequency synthesizer A7. The synthesizer interprets the two-out-of-five frequency information from a vhf control to provide all internal RF signals required by the vhf receiver and transmitter. In the receive mode, a dc tuning voltage, high-band control (618M-3A/4A only), and RIP injection frequency is applied to vhf receiver A3. The 618M-3/4 vhf receiver uses a lowband preselector to select the desired frequency, while the 618M-3A/4A has a low and high-band preselector. When a frequency above the low-band preselector range is selected, the synthesizer provides a high-band control signal to switch preselectors. The 618M-3( )/4() transceivers CPN 622-1181-003, -005, -006, -008, -010; CPN 622-1396-203, -205, 206, -208, -209, -210; CPN 822-0731-003, -005, -006, -008, -010; and CPN 822-0732-203, -205, -206, -208, -209, -210 have an RF attenuator assembly to prevent cross-modulation problems when low isolation between vhf communication antennas exists. The attenuator senses RF level at the preselector input and provides attenuation when a high signal level is present. The 20-MHz IF is AGC controlled and provides the required selectivity and signal amplification. The AM detected audio is amplified to provide a SELCAL output and input to receiver audio circuits. The detected audio is amplitude and bandpass limited and applied to the output amplifier. Squelch circuits disable the output amplifier if proper signal-to-noise ratio or carrier level are not present.

When the ptt control is applied, the synthesizer removes the receiver injection and provides transmitter excitation at the selected frequency. Power is applied to the transmitter by the +16-V dc transmit series regulator, and the broadband amplifiers raise the synthesizer excitation to 20 watts minimum output. The RF output is low-pass filtered and applied through the transmit/receive switch to the antenna. During receive mode, the t/r switch output is routed through high-pass filter A11 (618M-4/4A only) prior to being supplied to receiver A3. The high-pass filter removes low frequency noise present in the received RF. The high-pass filter is disabled during transmit when ptt is active. The AM modulator A4 is a variable voltage series regulator power supply that accepts microphone and data inputs. Carrier modulation is detected by a sidetone detector and applied through the receiver audio amplifier to the aircraft audio system. C. Functional Theory of Operation (Refer to figures 12 and 801 for the 618M-3; figures 14, and 803 for the 618M-4; figures 13 and 802 for the 618M-3A; and figures 15 and 804 for the 618M-4A.) Receive Mode (a) Transmit/Receive Switch Operation RF signals from the antenna are applied through forward biased A1 A6CR603 to the preselector circuits in vhf receiver A3. In the receive mode no voltage is applied from the +16 VDC XMT power supply to the base of A1 Q501. A1 Q501 is turned off causing A1 Q502 to be turned on. A10502 provides the ground path through L200 required to forward bias A1 A6CR603. (b) Receiver Preselector Operation 1. 618M-3/4 Transceiver Low-band preselector circuit A3A1 selects the desired signal from the spectrum present at the antenna to provide an input to the balanced mixer. The preselector circuit is a 3-pole filter consisting of air-wound high-Q coils tuned by voltagevariable capacitance diodes. The synthesizer tuning voltage applied to diodes varies from 6.7 V dc at 118.000 MHz to 14.0 V dc at 135.975 MHz. 2. 618M-3/4 Transceiver With RF Attenuator The 618M-3 transceivers CPN 622-1181-003, -005, -006, -008, -010 and 618M-4 transceivers CPN 822-0731-003, -005, -006, -008, -010 contain an RF attenuator assembly, A3A4. The RF attenuator prevents preselector detuning and receiver overloading in the presence of a high-level undesirable signal. The attenuator consists of an isolation amplifier, a detector, and a switch with associated diode attenuator. With no RF signal applied, A3A4U1 noninverting input is biased slightly more positive than the inverting input. The output of A3A4U1 ride at a positive offset voltage, which reverse biases A3CR5. The low-band preselector circuits operate normally with only minimal loss caused by the attenuator wiring. RF signals applied to the low-band preselector are also coupled to the RF attenuator isolation amplifier A3A4Q1. The RF output from the isolation amplifier is rectified by A3A4 CR1 and CR2 to provide a negative voltage to the noninverting input of A3A4U1. When the RF input is greater than 1 volt, the output from A3A4U1 goes negative, forward biasing A3CR5. The RF voltage at the high side of A3A1 L203 is coupled through A3R6 and C5 to ground, providing 16 dB of attenuation. Operating in this condition, an on frequency signal of 19 V or greater is required to provide a 6-dB signal-to-noise ratio output from the vhf receiver. 3. 618M-3A/4A Transceiver The 618M-3A/4A transceiver requires two preselector circuits to cover the operating range. Low-band preselector A3A2 is used from 116.000 to 135.975

MHz and the high-band preselector A3A3 from 136.000 to 151.975 MHz. The preselectors are switched by the high-low band preselector switch that is controlled by the synthesizer high-band control signal. In the frequency range from 116.000 to 135.975 MHz, the synthesizer applies a logic 0 to the base of A3Q201. A3Q201 is turned on, causing A3Q202 to be turned off. A3Q201 forward biases A3A2CR200 and CR210 by applying positive voltage through A3L202 and L225. The high-band preselector is disabled by negative voltage applied through A3L201 and L226, reverse biasing A3A3CR201 and CR211. When a high-band frequency is selected, the conditions reverse and the low-band preselector is disabled. 4. 618M-3A/4A Transceiver With RF Attenuator The 618M-3A transceivers CPN 622-1396-203, -205, -206, -208, -209, -210 and 618M-4A transceivers CPN 822-0732-203, -205, -206, -208, -209, -210 contain an RF attenuator assembly, A3A4. The RF attenuator prevents preselector detuning and receiver overloading in the presence of a high-level undesirable signal. The attenuator consists of an isolation amplifier, a detector, and a switch with associated diode attenuator.
With no RF signal applied, A3A4U1 noninverting input is biased slightly more positive than the inverting input. The output of A3A4U1 rides at a positive offset voltage, which reverse biases A3CR5 and A3CR6. The low-band and high-band preselector circuits operate normally with only minimal loss caused by the attenuator wiring.

(c)

(d)

RF signals applied to either the low-band or the high-band preselector are coupled to the RF attenuator isolation amplifier A3A401. The RF output from the isolation amplifier is rectified by A3A4 CR1 and CR2 to provide a negative voltage to the noninverCing input of A3A4U1. When the RF input is greater than 0.25 volt, the output from A3A4U1 goes negative, slightly forward biasing pin diodes A3CR5 and A3CR6. The current through CR5 and CR6 is controlled by A3R6 and A3R7. The RF voltage at the high side of A3A1 L203 and A3A1 L208 is coupled through CR5 and CR6 and capacitors CI and C2 to ground. This attenuates a 1-V signal by 16 dBm on the -203, -205, -206 radios. The -208, -209, -210 radios will provide 6 dBm of attenuation to a 400-mV signal and 16 dBm of attenuation to a 1.5-V signal. Operating in this condition, an on frequency signal of 19 [tV or greater is required to provide 6-dB signal-to-noise ratio output from the vhf receiver. Balanced Mixer Operation The balanced mixer mixes the preselector output with the synthesizer injection to produce a 20-MHz difference frequency for amplification by the 20-MHz IF amplifier. The mixer uses two dual gate MOS field-effect transistors. The mixing function provided by the FETs is unique in that the injection frequency applied to gate no 2 modulates the transfer characteristic of input gate no 1. This action provides high gain (20 dB) at the conversion frequency. The mixer output circuit is adjusted to resonate at 20 MHz by A3C222. 20-MHz IF and Detector Operation The 20-MHz IF consists of two bandpass filters and five stages of amplification. The bandpass filters control receiver selectivity and the amplifiers provide a maximum gain of 100 dB The gain of the first three IF amplifiers is controlled by an AGC voltage. AM detection is provided by A3CR203. The resulting audio and dc component is buffer amplified by A3U201 and applied to the AGC, squelch, and audio circuits. The AGC voltage is derived by low-pass filtering and amplifying the dc voltage developed in detection. Figure 16 shows typical AGC voltage versus input signal level. The AGC voltage is applied to gate no 2 of the first three IF amplifier stages, which are dual-gate MOS field-effect transistors. The 618M-3A CPN 622-1396-

(e)

(f)

010,-011 and 618M-4A CPN 822-0832-010,-011 include an AGC monitor circuit. AGC monitor output can be read externally by connecting a 1000-ohm, 250-VtA meter to the AGC monitor output. The output level is adjustable by A3R1 and A3R2. SELCAL Output The 618M-3( )/4( ) transceivers provide an audio output for driving external SELCAL equipment. The audio output from the detector buffer is applied through amplifier A3U201 and A3T214 to the rear connector. The output level is adjustable by A3R323. The circuit is capable of providing a 100-mW output from 300 to 11 000 Hz with maximum level variation of 6 dB. Audio Circuit Operation The audio output circuit consists of a noise limiter, compressor, active filter, and power amplifier. 1. Noise Limiter and Compressor Detected audio is applied to the audio compressor circuit through a pulse type noise limiter consisting of A3CR238 and CR239. The compressor is designed to hold audio output level within 3 dB with a received signal modulation change from 40 to 90 percent. The compressor consists of two amplifiers with a variable voltage divider circuit. Amplifier A3U219 provides a voltage gain of 6.5 to drive the active filter circuit. The output from A3U219 is sampled and amplified (voltage gain of 10) by A3U220. The output level of A3U220 is adjustable by A3R319. The output from A3U220 is rectified (voltage-doubler) by A3CR232 and CR233 to provide a positive voltage to charge A3C333. When the audio signal reaches the level required to positively charge A3C333, A3CR231, and CR230, start to conduct. As A3CR31 and CR230 begin to conduct, a low-audio impedance path through A3CR231 and A3C333 to ground and through A3CR230 to ground is formed. The audio positive half-cycle is conducted through A3CR230 to ground while the negative half-cycle is conducted through A3CR231 and A3C333 to ground. if the detected audio level increases, A3CR231 and CR230 are forward biased further, providing an even lower impedance to ground. This variable voltage divider action reduces the audio input to A3U219 to maintain a nearly constant output. The compressor has an attack time of approximately 30 milliseconds and release time of 1 second. 2. Active Filter Operation Audio output from the compressor circuit is applied to the active filter that consists of A3U207A, U207B, and U202A. The active filter uses three stages of active lowpass resonant filters. The three filters add to provide a virtually flat response (1 dB) to frequencies from 300 Hz to 2.5 kHz and cuts off sharply above 2.5 kHz (refer to figure 17). The filter employs dc blocking capacitors that roll off the low frequencies below 300 Hz. 3. Audio Power Amplifier The power amplifier consists of two stages of amplification and an output impedance matching transformer. The first amplifier A3U202B provides a voltage gain of 7 to drive output amplifier A3U203. Amplifier A3U203 raises the audio level (voltage gain of 18) to the required 100-mW output level. The signal is then coupled through A3T203 to provide a 600-ohm balanced output to the rear connector. Output amplifier A3U203 is also wired to be disabled by the receiver squelch circuit. The amplifier is shut off when a negative voltage (approximately -0.3 V dc) from the squelch Schmitt trigger is applied to the cathode of A3CR209. The

amplifier is enabled when approximately +3 V dc is applied to the cathode of A3CR209.

(g)

Squelch Circuit Operation (Refer to figure 18.) The squelch circuit consists of three sensors and a switch to turn off/on the audio power amplifier A3U203. The sensors are a carrier-to-noise ratio circuit with a squelch tail clipper and a carrier override sensor. 1. Squelch Switch The squelch switch consists of operational amplifier A3U206 and associated components. A3U206 is connected in a high-gain configuration with positive feedback to provide a Schmitt trigger switching function. Primary inputs to the squelch switch are from the carrier-to-noise ratio sensor and squelch tail clipper. When no RF carrier is applied, a positive voltage from the carrier-to-noise ratio sensor is coupled to the inverting input of A3U206. A3U206 output is negative, shutting off the audio power amplifier A3U203. When the carrier-to-noise ratio is greater than 6 dB, the positive voltage is removed from inverting input of A3U206. A3U206 output switches positive, enabling the audio power amplifier. In this condition, the squelch tail clipper sensor output is required to prevent a burst of noise from being amplified when the carrier is removed. The squelch tail clipper senses carrier removal and provides a positive voltage to A3U206 inverting input to shut off the audio power amplifier while the carrier-to-noise squelch sensor recovers.

The secondary input to the squelch switch is from the carrier override squelch sensor. This function is required when the carrier-to-noise ratio sensor attempts to suppress the audio output due to detected noise such as inaudible heterodynes. When the RF carrier is 20 V or greater, the carrier override squelch sensor provides a positive voltage to the noninverting input of A3U206. Because this output is more positive than the carrier-to-noise squelch sensor, the A3U206 output switches positive, enabling the audio power amplifier.

(2)

An external squelch control can be connected to the transceiver. This control varies the positive bias on the noninverting input of A3U206 to control squelch threshold. 2. Carrier-to-Noise Ratio Squelch Sensor The sensor uses normal receiver-generated noise to provide an output voltage that causes the squelch switch to suppress the receiver audio output. The sensor consists of a high-pass filter, noise amplifier, and integrator with a shunt diode clipper. Receiver noise from the detector is applied to the sensor high-pass filter. The filter rejects audio frequencies below 8 kHz to prevent normal voice transmissions from affecting the sensor. The filter output is applied to high-gain (voltage gain of 15) noise amplifier A3U205. A3C292 couples the noise signal at the output of A3U205. A3CR207 provides shunt rectification of the noise signal. The positive voltage is filtered by A3R287 and A3C288 and applied to squelch switch A3U206, which disables the audio output. Pressing SQUELCH DISABLE switch S211 enables the audio output by grounding the sensor circuit through diodes A3CR215, A3CR206, and A3CR242. The ptt input accomplishes the same result, allowing sidetone audio to be amplified by the receiver audio power amplifier. When an RF signal is received, the IF AGC action reduces receiver noise. SQ THRESHOLD ADJ potentiometer A3R277 is adjusted to enable the audio output with a 6-dB or better signal-to-noise ratio. 3. Squelch Tail Clipper The squelch tail clipper circuit prevents a burst of noise from being heard at the end of a received transmission before the carrier-to-noise ratio sensor recovers. The circuit consists of a low-pass filter and a high-gain amplifier. While an RF signal is being received, a positive voltage with detected audio is applied to the low-pass filter from the detector buffer A3U201. The filter rejects the input and amplifier A3U221 output rides near 0 V dc as biased by A3R334 and A3CR240. When the RF signal is removed, the positive voltage falls rapidly to zero. This negative transition is coupled through the filter to the inverting input of A3U221. A3U221 output goes positive and the audio output is disabled by the squelch switch A3U206. The condition is maintained long enough for the AGC and carrier-to-noise ratio squelch sensor to recover. 4. Carrier Override Squelch Sensor The carrier override squelch sensor has the unique capability of being able to override the carrier-to-noise squelch sensor. When the received signal is 20 V (typical) or greater, the circuit will turn on the audio amplifier even though the carrier-to-noise squelch might not have. The circuit consists of operational amplifier A3U208 and associated components. The sensor threshold is set by adjusting A3R303 CARRIER SQUELCH control to provide proper bias to the noninverting terminal of A3U208. When a 20 V or greater signal is received, AGC input voltage to A3U208 inverting input is negative with respect to the noninverting input. The output of A3U208 switches positive and the audio power amplifier is enabled. (h) High-Pass Filter A11 Operation 618M-4/4A transceivers contain a high-pass filter A11 between the t/r switch output and the receiver A3 input. The high-pass filter removes low-frequency noise contained on the received RF input. During receive mode, the ground from A1 0501 is supplied to the junction of A11 C1 and A11 J1 enabling the received RF to pass from the t/r switch to the RF input of the receiver. Transmit Mode (Refer to figures 19, 805, and 806.) (a) Transmit Mode Switching

When the ptt control is applied to the transceiver, the synthesizer provides transmitter excitation, power is applied to the transmitter amplifiers, the modulator is activated, the transmitter is connected to the antenna, and the receiver squelch is defeated allowing the audio amplifier to be used for sidetone amplification. Two of the switching functions result directly from the ptt control; the others occur indirectly. The ptt control closes relay K211 and grounds the carrier-to-noise squelch sensor input to Schmitt trigger A3U206. This action allows the detected sidetone audio to be amplified by the receiver audio power amplifier and applied to the rear connector sidetone output pins. The ptt control also enables the +16 V dc XMT series regulator power supply. The +16 V dc XMT voltage directly powers the first three transmitter amplifiers, enables the modulator by establishing the operating bias level at the base of modulator predriver circuit, and disables the fourth and fifth receiver IF amplifiers to remove receiver noise. The +16-V dc XMT voltage also causes the antenna and synthesizer transmit/receive switching to take place. A1 Q501 is turned on by the +16 V dc XMT voltage. The resulting logic 0 applied to the synthesizer (SYNTH T/R) removes the 20-MHz offset and enables the transmitter drive output. Transmit receive diode Al A6CR602 is forward biased by the logic 0 from Al Q501 applied through A1 A6L608, A1 A6L617, and the low-pass filter. The receiver is disconnected from the antenna by the reverse of conditions stated in paragraph C.(1)(a). (b) Transmitter Operation The transmitter is capable of providing 20 watts minimum output from 116.000 to 151.975 MHz. Only the range from 118.000 to 135.975 MHz is used in the 618M3/4 transceiver. The transmitter consists of five stages of amplification to raise the synthesizer 1.1Vac output to 20 watts. All stages use broadband tuned circuits to eliminate mechanical tuning. The first three stages (A1 Q504, A1 A6Q601, and A1 Q602) are powered directly by the +16 V dc XMT series regulator. Variable capacitor Al A6C636 provides interstage impedance and matching, and is adjusted for maximum RF output at the low end of the transceiver frequency range. The last two stages (A1 Q603 and A1 Q604) are powered by modulator A4 and raise the RF carrier to 20 watts minimum. Output impedance matching is accomplished by variable capacitor A1 A6C610. The capacitor is adjusted to provide maximum output power at the high end of the transceiver frequency range. The RF output is low-pass filtered and applied through transmit receive diode Al A6CR603 to the antenna. The transceiver also provides a sidetone and transmitter power output indication. The RF output is sampled through Al A6C611 and detected by sidetone detector A1 A6CR601. The detected modulation is applied through the receiver audio power amplifier to the rear connector to provide the sidetone audio output. When the transmitter output is greater than 10 watts, the TRANSMIT POWER lamp lights. The sidetone detector output is used to control the lamp driver circuit. The positive voltage from the sidetone detector is applied to the noninverting input of A1A6U601. When the detected voltage exceeds the +0.3-V dc bias at the inverting input, the Al A6U601 output goes positive, turning A1 0605 on, which lights the lamp. The lamp flickers slightly when the RF output is modulated with voice peaks.

The 618M-3 CPN 622-1181-003 and 618M-4 CPN 822-0731-003 (SB 14 optional) sidetone is provided by a constant level audio signal from the collector of A4Q408 of the modulator. This signal is applied to sidetone audio board A9 and is turned on and off by lamp driver Al A6U601. The lamp driver is switched by the dc output of sidetone detector A1 CR601. The lamp may dim slightly when the RF output is modulated with voice peaks. (c) Modulator A4 The AM modulator A4 acts as a variable voltage series regulator power supply that accepts microphone and data inputs. The modulator provides +13.5 V dc nominal to the transmitter driver and power amplifier stages. The modulator output voltage swings from +0.5 to +27 V dc to provide 90-percent AM modulation. The modulator contains a compressor and limiter circuit to prevent overmodulation. 1. Preamplifier Microphone and data inputs are transformer coupled, low-pass filtered, and applied to the preamplifier. The preamplifier, consisting of A2Q404 and A4041 1, provides a voltage gain of 20 to drive the predriver stage. 2. Predriver The predriver stage establishes the modulator nominal output voltage, provides signal voltage gain of 7, and contains modulation limiter circuits. The modulator nominal output voltage is controlled by the voltage applied to the base of A4Q405. When the ptt control turns on the +16-V dc XMT series regulator, the voltage is applied across A4R423, the PA B+ ADJ resistor. A4Q405 base voltage can be varied from approximately +2.3 to +3.0 V dc to control the nominal output voltage of the modulator. Nominal voltages and peak-to-peak signal amplitudes are shown in figure 20. Negative signal peaks are limited in the collector circuit at A4Q406. The limiting level is established by the +16 V dc XMT voltage applied across A4R472, optional A4CR432, and A4VR405 to ground. The network provides +5.2-V dc (A4CR432 not shorted) bias to the anode of A4CR431. Negative signal peaks are prevented from going below +3.9 V dc by A4VR405. NOTE: Diode A4CR432 is bypassed in production as required to achieve modulation percentage without negative clipping. 3. Driver and Power Amplifier The driver and power amplifier stages, consisting of A4Q407 through A4Q410, provide the power gain required to operate the transmitter driver and power amplifier. Nominal voltages and signal amplitudes are shown in figure 20. 4. Compressor (Refer to figure 21.) The compressor circuit is capable of maintaining a nearly constant carrier modulation without clipping with an input signal ranging from 0.125 to 2.5 volts rms. The compressor consists of modulation detector A4CR407, control amplifiers A4Q412 and A4Q41 Q, and bridge attenuator diodes A4Q412, A4Q413, A4Q415, and A4Q416. When the modulator output amplitude is below the compressor threshold, A4Q412 is turned off. A4Q416 is turned on (saturated) and the resulting low collector-toemitter voltage drop reverse biases the attenuator diodes. The modulator input signal is not affected by the attenuator diodes. When the modulator output amplitude is above the compressor threshold, the compressor circuit begins to function. The positive half-cycles applied from detector A4CR407 to A4Q412 base exceed the emitter bias, which is set by COMPRESSOR THRESHOLD ADJ resistor A4R436. A4Q412 begins to conduct,

discharging A4C416.:.A4Q416 conduction decreases, resulting in an equal rise in collector voltage and decrease in emitter voltage. The diodes in the bridge attenuator are forward biased and form a voltage divider to reduce the modulator input signal amplitude. If the modulator input signal amplitude increases, A4Q416 conduction decreases further. This action increases the forward bias of the attenuator bridge diodes, providing a lower impedance to ground for the modulator input signal. The compressor circuit, during transmit, has an approximate attack time of 2 milliseconds and recovery time of 4 seconds. When the transceiver switches from transmit to receive, the compressor recovery time is greatly reduced. Capacitor A4C416 is rapidly charged by +20 V dc applied through R331, C334, and the contacts of K212 to the base circuit of A4Q416. (3) Synthesizer The synthesizer uses a single phase-locked loop to generate, in 25-kHz steps, the receiver injection frequencies in the range of 116.000 to 155.975 MHz, and transmitter drive frequencies in the range of 116.000 to 151.975 MHz. A 3.2-MHz crystal oscillator serves as the frequency standard and provides the necessary stability. The synthesizer also generates a dc tuning voltage to track the receiver preselector to the selected channel frequency. (a) Synthesizer Functional Description (Refer to figure 25.) Frequency selection is made at a remote control unit. The control unit supplies standard ARINC two-out-of-five frequency information to the synthesizer, where it is filtered, buffered, and then converted into binary-coded-decimal (bcd) format. Figures 22 and 23 show the conversion of two-out-of-five to bcd. The logic levels are also changed by the converter from ground and open (logic 0 and 1) to G and +5 V dc (logic 0 and 1). The bcd data from the converter is applied to the high-low band select logic circuit, the 20-MHz offset logic circuit, and the variable divider circuit. The high-low band select logic determines in which band the selected operating frequency is located. Low band is from 116.000 to 135.975 MHz; high band is from 136.000 to 151.975 MHz. The output from the high-low band select logic circuit is logic 1 for high band and logic 0 for low band. The high-band logic output is applied to the 618M-3A/4A receiver for switching preselector circuits and to the synthesizer vco select logic circuit. The vco select logic circuit combines the SYNTH T/R signal from the transmitter with the high-low band information, and enables the applicable vco. Refer to figure 24 for illustration of vco selection versus operating frequency and mode. The output of the operating vco is applied to a buffer and output amplifier whose output is switched to the receiver injection output connector or to the transmitter drive output connector as appropriate. The vco output is also routed through a buffer amplifier to the variable divider circuit. The variable divider (paragraph (b)) is digitally controlled by the bcd information from the converter and, in the receive mode, by the signals from the 20-MHz offset logic circuit. The division ratio of the variable divider is selectable from 4640 to 6239, depending on the bcd information and operating mode of the radio. The division ratio selected always produces an output frequency of 25 kHz. For each 25-kHz change in operating frequency, the division ratio changes by 1. The variable divider output is applied to the frequency/phase detector where it is compared with another 25-kHz signal that is derived from a frequency standard circuit.

The frequency standard circuit consists of a 3.2-MHz crystal oscillator. The 3.2MHz signal is applied to a fixed divide-by-128 countdown divider whose 25-kHz output is applied to the frequency/phase detector. The frequency/phase detector consists of a combination of set-reset flip-flops. The 25-kHz input from the variable divider sets the phase detector output high. The 25kHz input from the fixed divider resets the phase detector output low. Switching occurs on the leading edge of the pulses. This results in an output whose pulse width or duty cycle is proportional to the phase difference between the two input pulses. The output of the frequency/phase detector controls a switch that switches the input to a low-pass filter between +16 and +5.2 V dc. The pulses are-filtered to a dc voltage level proportional to the duty cycle of the pulses. This dc voltage is developed across a capacitor and applied to varactors in the operating vco circuit and through a tracking amplifier to the receiver preselector. The net result of this action is that the phase difference between the 25-kHz reference and the output of variable divider controls the vco frequency. As the phase difference increases, the tuning voltage increases, and the vco frequency increases. The condition for phase lock occurs when the phase difference becomes constant at the value necessary to produce a vco frequency that, when divided, produces 25 kHz at the phase detector. The division ratio of the variable divider determines the vco frequency where phase lock occurs. Should either the division ratio of the variable divider change or the vco frequency drift, the phase difference will change, causing the vco frequency to change until the phase-lock condition is again met. The frequency/phase detector provides a signal to the loss-of-lock circuit when the synthesizer becomes unlocked. During normal operation, the pulses alternate between the set and reset inputs. But when two or more consecutive pulses occur on either the set or reset inputs, the loss-of-lock circuit produces an output. This condition occurs when the variable divider output is greater than or less than 25 kHz This always happens whenever a new operating frequency is first selected. Whenever the phase loop is unlocked, the synthesizer transmit switch inhibits the drive frequency signal to the transmitter. (b) Synthesizer Variable Divider Operation (Refer to figure 26.) The variable divider provides a 25-kHz output to the frequency/phase detector for each vco input in the range from 116.000 to 155.975 MHz. In order to accomplish this, the division ratio is selectable from 4640 to 6239. The required vco frequency in bcd format presets the various counters in the variable divider. The 10-MHz digit presets variable counter U6 so that it always divides by 11, 12, 13, 14, or 15 (10 plus the 10-MHz digit). U6 has a bus output that becomes logic 1 when al interna flip-flops of U6 are at logic 0. Decade counter U7 normally divides by 10 except for the first time, when it is preset by the 1-MHz digit. At that time, U7 divides by 10 + N, where N is the value of the 1-MHz digit. For example, if the 1-MHz digit is 7, U7 divides by 17 the first time and divides by 10 each subsequent time. U7 has a bus output that is the same as U6. Decade counter U11 normally divides by 10 except for the times that it divides by 11, which can be from 0 to 39 times. The number depends on how many 25-kHz increments are set into counters U8 and U9 by the 0.1-, 0.01-, and 0.001-MHz bed data. If, for example, the selected vco frequency is 1 XX.375 MHz, U8 and U9 would be set to 15 (1 for each 25-kHz increment in 0.375 MHz). Logic combiner U10 senses the count in U8 and U9 and supplies to U11 a logic 0, causing U11 to

divide by 11. Decade counter U11 then divides by 11 for 15 times as 1.18 and U9 count down to zero. When the count reaches zero, U10 supplies a logic 1 to U11 and, from then on, it divides by 10. Thus, the complete sequence of events that occurs to produce a single output from the variable divider is as follows. A negative-going load signal from U10 is applied to counters U6, U7, U8, and U9, which causes the bed data to preset the counters. Counter U11 divides by 11 until U8 and U9 count down to zero, then U11 divides by 10. The fixed-divider part of U8 divides the U11 output by 4. Counter U7 divides the U8 output the first time by 10 + N and then each subsequent time by 10. Counter U6 divides the U7 output by 1 X where X is the 10-MHz digit. By monitoring the outputs of U6, U7, and U8, logic combiner U10 senses the 2-state; that is, when only two more pulses are needed to complete the division cycle. U10 is then preset to produce an output pulse, two input pulses later. This output pulse is applied to the frequency/phase detector; and as a load pulse, to the variable counter. The division cycle is then repeated. The following examples illustrate how the variable divider functions. 1. 130.000-MHz Example For a vco frequency of 130.000 MHz, the division ratio must be 5200 to produce a 25-kHz output. This frequency in bed format presets the