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Moore FSM
Output Is a Function of Present State Only
Inputs Next State function Next State clock reset Present State Register Present State Inputs
Mealy FSM
Output Is a Function of a Present State and Inputs
Next State function Next State clock reset Present State Register Present State
Output function
FSM Design Using VHDL
Outputs
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Output function
FSM Design Using VHDL
Outputs
4
Moore Machine
transition condition 1 state 1 / output 1 state 2 / output 2
Mealy Machine
transition condition 1 / output 1 state 2 transition condition 2 / output 2
state 1
transition condition 2
19-Feb-11
Mealy FSM Has Richer Description and Usually Requires Smaller Number of States
Smaller circuit area
FSM Design Using VHDL 7
1/0 S1
1/0
0 S1: 1 observed
S2: 10 observed
Meaning of states:
S1: 1 observed
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19-Feb-11
Example: four states S0,S1,S2,S3 Binary state encoding: 00,01,10,11 One-hot state encoding: 1000,0100,0010,0001 Binary state encoding: CPLD One-hot state encoding: FPGA, rich resources in registers.
FSM Design Using VHDL 13
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19-Feb-11
(three processes)
0110 Detector Moore FSM No overlapping when S01=> COM: process (CS,X) is
begin case CS is when IDLE => if (X = 0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = 0') then NS<=S0; else NS<=S01; end if;
if (X = 0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = 0') then NS<=S0110; else NS<=IDLE; end if; when S0110=> NS<=IDLE; end case; end process COM;
FSM Design Using VHDL
architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=1 ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;
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FSMs in VHDL
Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed
State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process
27 FSM Design Using VHDL 28
OR
Z<=1 when CS=S0110 else 0; end architecture NOOV;
Moore FSM
process(clock, reset)
Inputs Next State function Next State clock reset Present State Register Present State clock reset Inputs
Mealy FSM
process(clock, reset)
Next State function Next State Present State Register Present State
concurrent statements
Output function
FSM Design Using VHDL
Outputs
29
concurrent statements
Output function
FSM Design Using VHDL
Outputs
30
19-Feb-11
0 1 S2 / 1
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19-Feb-11
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Present state A B C
Next state w = 0 A A A w = 1 B C C
Output z 0 0 1
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Moore FSM
process(clock, reset)
Input: w Next State function Next State clock resetn Present State Register Present State: y
concurrent statements
Output function
FSM Design Using VHDL
Output: z
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ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN
FSM Design Using VHDL 42
19-Feb-11
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Moore FSM
process Input: w (w, y_present) process (clock, resetn) concurrent statements
Next State function
Next State: y_next clock resetn Present State Register Present State: y_present
Output function
FSM Design Using VHDL
Output: z
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19-Feb-11
Mealy FSM
process(clock, reset)
Input: w Next State function Next State clock resetn Present State Register Present State: y
Present state A B
Next state w = 0 A A w = 1 B B
Output w = 0 0 0
z w = 1 0 1
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concurrent statements
Output function
FSM Design Using VHDL
Output: z
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ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN
FSM Design Using VHDL
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