VHDL Lab Programs

ECAD AND VLSI LAB MANUAL
IV B-TECH, ECE 1ST SEMESTER
Sri Indu College of Engineering & Technology
Dept. of ECE-ECAD & VLSI Lab
ECAD AND VLSI LAB

SYLLABUS
LIST OF EXPERIMENTS:
ECAD PROGRAMS:
1.HDL CODE TO REALIZE AL THE LOGIC GATES. 2. DESIGN OF 2 TO 4 DECODER 3. DESIGN OF 8 TO 3 ENCODER 4. DESIGN OF 8 TO 1 MULTIPLEXER 5. DESIGN OF 4 BIT BINARY TO GRAY CODE CONVERTER 6. DESIGN OF MULTIPLEXER/DEMULTIPLEXER,COMPARATOR 7. DESIGN OF FULL ADDER USING 3 MODELLING STYLES. 8. DESIGN OF FLIPFLOPS :SR, D, JK, T. 9. DESIGN OF 4-BIT BINARY ,BCD COUNTERS (SYNCHRONOUS/ASYNCHRONOUS RESET) OR ANY SEQUENCE COUNTER 10.FINITE STATE MACHINE DESIGN.
EXPERIMENT: 1 LOGIC GATES

AIM: To design all the logic gates using three different modeling styles and verify the functionalities along with their synthesis and simulation reports. APPARATUS : Xilinx 9.2 installed PC. THEORY: AND: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB OR: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation. NOT: The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way. NAND: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion. NOR: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion. EX-OR: The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation. EX-NOR: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion. Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
TRUTH TABLE: a b Y[0] Y[1] Y[2] Y[3] Y[4] ) 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 Y[5] (xor ) 0 1 1 0 1 0 0 1 Y[6] (xnor)
(not) (and) (or)
(nand) (nor
VERILOG CODE: LOGIC GATES USING DATAFLOW MODELING STYLE `resetall `timescale 1ns/10ps module logicgatesdf(a,b,y) ; input a,b; output [0:6]y; wire a,b; assign y[0] = ~a; assign y[1] = a&b; assign y[2] = a|b; assign y[3] = ~(a&b); assign y[4] = ~(a|b); assign y[5] = a^b; assign y[6] = ~(a^b); endmodule // input declarations //output declarations //input as wires //not gate //and gate //or gate //nand gate //nor gate //xor gate //xnor gate
LOGIC GATES USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module logicgatesst(a,b,y); Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
input a,b; output [0:6]y; not g1(y[0],a); and g2(y[1],a,b); or g3(y[2],a,b); nand g4(y[3],a,b); nor g5(y[4],a,b); xor g6(y[5],a,b); xnor g7(y[6],a,b); endmodule
// input declarations // output declarations // not gate //and gate //or gate //nand gate //nor gate //xor gate //xnor gate
LOGIC GATES USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module logicgatesbh(a, b, y); input a; input b; output [0:6] y; wire a; wire b; reg [0:6]y; always@(a or b) begin if(a==1'b0) begin if(b==1'b0) begin // {y[0],y[3],y[4],y[6]}=1'b1; //{y[1],y[2],y[5]}=1'b0; y[1]=1'b0;y[2]=1'b0; y[5]=1'b0; end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab y[0]=1'b1;y[3]=1'b1;y[4]=1'b1;y[6]=1'b1;
else begin // // {y[0],y[2],y[3],y[5]}=1'b1; y[0]=1'b1;y[2]=1'b1;y[3]=1'b1;y[5]=1'b1; {y[1],y[4],y[6]}=1'b0; y[1]=1'b0;y[4]=1'b0; y[6]=1'b0; end end else if(a==1'b1) begin if(b==1'b0) begin // {y[0],y[1],y[4],y[6]}=1'b0; //{y[2],y[3],y[5]}=1'b1; y[2]=1'b1;y[3]=1'b1; y[5]=1'b1; end else begin // // { y[0],y[3],y[4],y[5]}=1'b0; y[0]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0; {y[1],y[2],y[6]}=1'b1; y[1]=1'b1;y[2]=1'b1; y[6]=1'b1; end end end endmodule LOGIC GATES TEST BENCH `resetall Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab y[0]=1'b0;y[1]=1'b0;y[4]=1'b0;y[6]=1'b0;
`timescale 1ns/10ps module logicgatesdf_tb; reg a; reg b; wire [0:6]y; logicgatesdf U_0( .a (a), .b (b), .y (y) ); initial begin a = 0; #10 a = 0; #10 a = 1; #10 a = 1; end initial begin #50 $finish; end endmodule b = 0; b = 1; b = 0; b = 1; // output as wire in test bench // input as reg in test bench
OUTPUT WAVEFORMS: AND GATE:
OR GATE:
NOT GATE:
EX-OR GATE:
NAND GATE:
NOR GATE:
XNOR GATE:
Result : The truth tables of all logic gates are verified
EXPERIMENT: 2 ADDERS
2.1. HALF ADDER AIM: To design a half adder along with a verilog code in all the three models and verify its functionality and check its simulation report. named as carry. APPARATUS : Xilinx 9.2 installed PC. THEORY: A half adder has two inputs, generally labelled A and B, and two outputs, the sum S and carry C. S is the two-bit XOR of A and B, and C is the AND of A and B. Essentially the output of a half adder is the sum of two one-bit numbers, with C being the most significant of these two outputs. A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits.The drawback of this circuit is that in case of a multibit addition, it cannot include a carry.
BLOCK DIAGRAM:
TRUTH TABLE: a 0 0 1 1 b 0 1 0 1 carry 0 0 0 1 Sum 0 1 1 0
a, b are inputs and carry, sum are outputs VERILOG CODE: HALF ADDER USING DATAFLOW MODELING STYLE `resetall `timescale 1ns/10ps module hl_df(a,b,sum,carry) ; input a; input b; output sum; output carry; assign sum= a^b; assign carry= a&b; endmodule HALF ADDER USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module hl_st(a,b,sum,carry) ; input a; input b; output sum; output carry; xor g1(sum,a,b); //sum Dept. of ECE-ECAD & VLSI Lab //output declarations //input declarations //sum //carry //output declarations //input declarations
and g2(a,b); endmodule
//carry
HALF ADDER USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module hl_bh(a,b,sum,carry); input a; input b; output sum; output carry; wire a; wire b; reg sum; reg carry; always@(a or b) begin if(a==b) begin sum=1'b0; end else begin sum=1'b0; end end always@(a or b) begin if(a==b==1'b1) begin carry=1'b1; end Sri Indu College of Engineering & Technology // carry description Dept. of ECE-ECAD & VLSI Lab //sum description //output as reg //input as wires //output declarations //input declarations
else begin carry=1'b0; end end endmodule HALF ADDER TEST BENCH `resetall `timescale 1ns/10ps module hl_bh_tb; reg a; reg b; wire sum; wire carry; hl_bh U_0( .a .b (a), (b),
.sum (sum), .carry (carry) ); initial begin a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; end endmodule // hl_bh_tb
OUTPUT WAVEFORMS:
HALF ADDER:
Result : The truth table of half adder is verified and output wave forms has been observed.
2.2 FULL ADDER AIM: To design a FULL ADDER along with a verilog code in all the three models and verify its functionality and check its simulation report. APPARATUS : Xilinx 9.2 installed PC. THEORY: A full adder has three inputs - A, B, and a carry in C, such that multiple adders can be used to add larger numbers. To remove ambiguity between the input and output carry lines, the carry in is labelled Ci or Cin while the carry out is labelled Co or Cout. A full adder is a logical circuit that performs an addition operation on three binary digits. The full adders produces a sum and carry value, which are both binary digits
BLOCK DIAGRAM:
TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1
Where a, b, cin are the inputs and sum, carry are outputs VERILOG CODE: FULL ADDER USING DATAFLOW MODELING STYLE `resetall `timescale 1ns/10ps module fa_df(a,b,c,sum,carry); input a; input b; input c; output sum; output carry; assign sum= a ^b^c; assign carry= (a&b)|(b&c)|(a&c); endmodule FULL ADDER USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module fl_st(a,b,cin,sum,carry) ; input a,b,cin; output carry,sum; wire w0,w2,w3; xor g1(w0,a,b); xor g2(sum,w0,cin); and g3(w3,a,b); and g4(w2,w0,cin); or g5(carry,w3,w2); endmodule //carry //sum // input variables // output variables // internal variables declaration //sum //carry //output declarations //input declarations
FULL ADDER USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module fa_behv(a,b,cin, sum, carry); input a; input b; input cin; output sum; output carry; reg sum,carry; wire a,b,cin; always@(a or b or cin) begin case({a,b,cin}) 3'b000:begin sum=1'b0; 3'b001:begin sum=1'b1; 3'b010:begin sum=1'b1; 3'b011:begin sum=1'b0; 3'b100:begin sum=1'b1; 3'b101:begin sum=1'b0; 3'b110:begin sum=1'b0; 3'b111:begin sum=1'b1; default:begin sum=1'b0; endcase end endmodule FULL ADDER TEST BENCH `resetall `timescale 1ns/10ps module fa_behv_tb; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab carry=1'b0; carry=1'b0; carry=1'b0; carry=1'b1; carry=1'b0; carry=1'b1; carry=1'b1; carry=1'b1; carry=1'b0; end end end end end end end end end //output as reg //input as wires // behavioral description of full adder //output declarations //input declarations
reg a ,b; reg cin; wire sum; wire carry; fa_behv U_0( .a .b (a), (b),
.cin (cin), .sum (sum), .carry (carry) ); initial begin a=1'b0;b=1'b0;cin=1'b0; #10 a=1'b0;b=1'b0;cin=1'b1; #10 a=1'b0;b=1'b1;cin=1'b0; #10 a=1'b0;b=1'b1;cin=1'b1; #10 a=1'b1;b=1'b0;cin=1'b0; #10 a=1'b1;b=1'b0;cin=1'b1; #10 a=1'b1;b=1'b1;cin=1'b0; #10 a=1'b1;b=1'b1;cin=1'b1; end initial begin #100 $finish; end endmodule // fa_behv_tb
OUTPUT WAVEFORMS: FULL ADDER:
2.3 4-BIT BINARY PARALLEL ADDER AIM: To design a 4-BIT BINARY PARALLEL ADDER in all the three models and verify its functionality and check its simulation report. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM: A[3] B[3] A[2] B[2] A[1] B[1] A[0] B[0] Cin
FULL ADDER S[3] Cout
FULL ADDER S[2]
FULL ADDER S[1]
FULL ADDER S[0]
S[3] TRUTH TABLE:

A 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 B 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0
S[2]
S[1]
S[0]
Cin Sum(s) Cout Cin Sum Cout 0 0 0 0 0 0 0 0 0 0000 0010 0100 0110 1000 1010 1100 1110 0000 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 000 1 001 1 010 1 011 1 100 1 101 1 110 1 111 1 000 1 0 0 0 0 0 0 0 0 1
100 1 101 0 101 1 110 0 110 1 111 0 111 1
100 1 101 0 101 1 110 0 110 1 111 0 111 1
0 0 0 0 0 0 0
0010 0100 0110 1000 1010 1100 1110
1 1 1 1 1 1 1
1 1 1 1 1 1 1
001 1 010 1 011 1 100 1 101 1 110 1 111 1
1 1 1 1 1 1 1
Where a,b,cin are the inputs and sum,carry are outputs VERILOG CODE: 4-BIT BINARY PARALLEL ADDER USING BEHAVIORAL MODELING `resetall `timescale 1ns/10ps module bit4pladbh(a,b,cin,sum,cout) ; input [0:3]a; input [0:3]b; input cin; output [0:3]sum; output cout; wire [0:3]a; wire [0:3]b; wire cin; reg [0:3]sum; reg cout; always@(a or b or cin) begin if(cin==1'b0) begin case({a,b}) Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
8'b00000000: begin sum=4'b0000; cout=1'b0;end 8'b00010001: begin sum=4'b0010; cout=1'b0;end 8'b00100010: begin sum=4'b0100; cout=1'b0;end 8'b00110011: begin sum=4'b0110; cout=1'b0;end 8'b01000100: begin sum=4'b1000; cout=1'b0;end 8'b01010101: begin sum=4'b1010; cout=1'b0;end 8'b01100110: begin sum=4'b1100; cout=1'b0;end 8'b01110111: begin sum=4'b1110; cout=1'b0;end 8'b10001000: begin sum=4'b0000; cout=1'b1;end 8'b10011001: begin sum=4'b0010; cout=1'b1;end 8'b10101010: begin sum=4'b0100; cout=1'b1;end 8'b10111011: begin sum=4'b0110; cout=1'b1;end 8'b11001100: begin sum=4'b1000; cout=1'b1;end 8'b11011101: begin sum=4'b1010; cout=1'b1;end 8'b11101110: begin sum=4'b1100; cout=1'b1;end 8'b11111111: begin sum=4'b1110; cout=1'b1;end endcase end else begin case({a,b}) 8'b00000000: begin sum=4'b0001; cout=1'b0;end 8'b00010001: begin sum=4'b0011; cout=1'b0;end 8'b00100010: begin sum=4'b0101; cout=1'b0;end 8'b00110011: begin sum=4'b0111; cout=1'b0;end 8'b01000100: begin sum=4'b1001; cout=1'b0;end 8'b01010101: begin sum=4'b1011; cout=1'b0;end 8'b01100110: begin sum=4'b1101; cout=1'b0;end 8'b01110111: begin sum=4'b1111; cout=1'b0;end 8'b10001000: begin sum=4'b0001; cout=1'b1;end 8'b10011001: begin sum=4'b0011; cout=1'b1;end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
8'b10101010: begin sum=4'b0101; cout=1'b1;end 8'b10111011: begin sum=4'b0111; cout=1'b1;end 8'b11001100: begin sum=4'b1001; cout=1'b1;end 8'b11011101: begin sum=4'b1011; cout=1'b1;end 8'b11101110: begin sum=4'b1101; cout=1'b1;end 8'b11111111: begin sum=4'b1111; cout=1'b1;end endcase end end endmodule 4-BIT BINARY PARALLEL ADDER USING STRUCTURAL MODELING `resetall `timescale 1ns/10ps module bit4pladst(a,b,cin,s,cout); input [0:3]a; input [0:3]b; input cin; output [0:3]s; output cout; wire [0:2]p; fa_st g1(s[0],p[0],a[0],b[0],cin); fa_st g2(s[1],p[1],a[1],b[1],p[0]); fa_st g3(s[2],p[2],a[2],b[2],p[1]); fa_st g4(s[3],cout,a[3],b[3],p[2]); endmodule FULL ADDER DESIGN USED IN 4-BIT BINARY PARALLEL ADDER `resetall `timescale 1ns/10ps Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
module fa_st(sum,cout,a,b,cin); input a; input b; input cin; output sum; output cout; wire w0,w2,w3; xor g1(w0,a,b); xor g2(sum,w0,cin); and g3(w3,a,b); and g4(w2,w0,cin); or g5(carry,w3,w2); endmodule FOUR BIT BINARY PARALLEL ADDER USING DATAFLOW MODELING `resetall `timescale 1ns/10ps module bit4pladdf (a,b,cin,sum,carry); //input port declaration input [0:3]a; input [0:3]b; input cin; output [0:3]sum; output carry; wire [0:3]a; wire [0:3]b; wire cin,carry; wire [0:3]sum; assign {carry,sum}=a+b+cin; endmodule BIT 4 BINARY PARALLEL ADDER TEST BENCH Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab //port wires // output port declaration // carry //sum // internal variables declaration
`resetall `timescale 1ns/10ps module bit4pladbh_tb; reg [0:3] a; reg [0:3] b; reg wire .a .b cin; cout; (a), (b), wire [0:3] sum; bit4pladbh U_0(
.cin (cin), .sum (sum), .cout (cout) ); initial begin #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 a = 4'b0000; a = 4'b0001; a = 4'b0010; a = 4'b0011; a = 4'b0100; a = 4'b0101; a = 4'b0110; a = 4'b0111; a = 4'b1000; a = 4'b1001; a = 4'b1010; a = 4'b1011; a = 4'b1100; b=4'b0000; b=4'b0001; b=4'b0010; b=4'b0011; b=4'b0100; b=4'b0101; b=4'b0110; b=4'b0111; b=4'b1000; b=4'b1001; b=4'b1010; b=4'b1011; b=4'b1100; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; cin=1'b0; Dept. of ECE-ECAD & VLSI Lab
a = 4'b1101; b=4'b1101;
#5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 #5 end initial
a = 4'b1110; a = 4'b1111; a = 4'b0000; a = 4'b0001; a = 4'b0010; a = 4'b0011; a = 4'b0100; a = 4'b0101; a = 4'b0110; a = 4'b0111; a = 4'b1000; a = 4'b1001; a = 4'b1010; a = 4'b1011; a = 4'b1100; a = 4'b1101; a = 4'b1110; a = 4'b1111;
b=4'b1110; b=4'b1111; b=4'b0000; b=4'b0001; b=4'b0010; b=4'b0011; b=4'b0100; b=4'b0101; b=4'b0110; b=4'b0111; b=4'b1000; b=4'b1001; b=4'b1010; b=4'b1011; b=4'b1100; b=4'b1101; b=4'b1110; b=4'b1111;
cin=1'b0; cin=1'b0; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b1; cin=1'b0; cin=1'b1; cin=1'b1;
begin #160 $finish; end endmodule
EXPERIMENT: 3 SUBTRACTORS
3.1 HALF SUBTRACTOR AIM: To design a HALF SUBTRACTOR and to write a verilog code in all three models to verify the functionality and check out the output waveforms or simulation report. APPARATUS : Xilinx 9.2 installed PC. THEORY: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X(minuend) and Y(subtrahend) and two outputs D (difference) and B (borrow). The Unit that performs 1-bit subtraction with borrow-in is defined as a fullsubtractor. It has input bits A, B and Bin(borrow in) and the output bits D(difference)and Bout (borrow out) . BLOCK DIAGRAM:
TRUTH TABLE: a b Borr 0 1 0 0 Diff 0 1 1 0
0 0 0 1 1 0 1 1
a, b are inputs and borr, diff are the outputs.
Diff = a xor b Borr = ab

HALF SUBTRACTOR USING DATAFLOW MODELING STYLE `resetall `timescale 1ns/10ps module HS_DF(a,b,borr,diff); input a; input b; output diff; output borr; assign diff= a^b; assign borrow= (~a)&b; endmodule HALF SUBTRACTOR USING STRUCTURAL MODELING STYLE: `resetall `timescale 1ns/10ps module HS_ST(a,b,diff,borr) ; input a; input b; wire c; output diff; output borr; xor g1(diff,a,b); not g2(c,a); and g3( borr,c,b); endmodule HALF SUBTRACTOR USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab // borrow // difference //internal variable //output variables //input variables // difference //borrow //output variables // input variables
module HS_BH (a,b,borr,diff); input a; input b; output diff; output borr; wire a; wire b; reg diff; reg borr; always@(a or b) begin if (a==b) begin diff= 1'b0; end else begin diff=1'b1; end end always@(a or b) begin if (a==1'b0 && b==1'b1) begin borr= 1'b1; end else begin borr=1'b0; end end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab // behavioral description of half subtractor //output as reg // input as wires //output declarations //input declarations
endmodule HALF SUBTRACTOR TEST BENCH `resetall `timescale 1ns/10ps module HS_ST_tb; reg a; reg b; wire diff; wire borr; HS_ST U_0( .a .b (a), (b),
.diff (diff), .borr (borr) ); initial begin a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; end initial begin #40 $finish; end endmodule
OUTPUT WAVEFORMS: HALF SUBTRACTOR
RESULT : Thus the half subtractor has designed and verified the functionality and the output waveforms are observed.
3.2 FULL SUBTRACTOR AIM: To design a full subtractor and to write a verilog code in all three models to verify the functionality and check out the output waveforms or simulation report. APPARATUS : Xilinx 9.2 installed PC. THEORY: The Unit that performs 1-bit subtraction with borrow-in is defined as a fullsubtractor.It has input bits A,B and Bin(borrow in) and the output bits D(difference)and Bout (borrow out) BLOCK DIAGRAM:
TRUTH TABLE:
a b c 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bor r 0 1 1 1 0 0 0 1 Diff 0 1 1 0 1 0 0 1
a, b, c, denote inputs and diff, borr denote outputs.
VERILOG CODE
Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
FULL SUBTRACTOR USING DATA FLOW MODELING STYLE `resetall `timescale 1ns/10ps module fullsubdata (a,b,cin,diff,borr); input a,b,cin; output diff,borr; assign diff=a^b^cin; assign borr=((~a)&(b|cin)|(b&cin)); endmodule FULL SUBTRACTOR USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module fullsubst (a,b,cin,borr,diff); input a,b,cin; output borr,diff; wire d,e,f,g; xor g1(diff,a,b,cin); or g2(d,b,cin); and g3(e,b,cin); not g4(f,a); and g5(g,f,d); or g6(borr,g,e); FULL SUBTRACTOR USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module fullsuBH (a,b,c,borr,diff); input a; input b; input c; output diff; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
output borr; reg diff,borrow; always@(a or b or c) begin case({a,b,c}) 3'b000: 3'b001: 3'b010: 3'b011: 3'b100: 3'b101: 3'b110: 3'b111: default: endcase end endmodule FULL SUBTRACTOR TEST BENCH: `resetall `timescale 1ns/10ps module fullsubdata_tb; reg a ,b; reg cin; wire diff; wire borr; fullsubdata U_0( .a .b (a), (b), begin diff=1'b0; begin diff=1'b1; begin diff=1'b1; begin diff=1'b0; begin diff=1'b1; begin diff=1'b0; begin diff=1'b0; begin diff=1'b1; begin diff=1'b0; borr=1'b0; borr=1'b1; borr=1'b1; borr=1'b1; borr=1'b0; borr=1'b0; borr=1'b0; borr=1'b1; borr=1'b0; end end end end end end end end end
.cin (cin), .borr (borr), .diff (diff) Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
); initial begin a=1'b0;b=1'b0;cin=1'b0; #10 a=1'b0;b=1'b0;cin=1'b1; #10 a=1'b0;b=1'b1;cin=1'b0; #10 a=1'b0;b=1'b1;cin=1'b1; #10 a=1'b1;b=1'b0;cin=1'b0; #10 a=1'b1;b=1'b0;cin=1'b1; #10 a=1'b1;b=1'b1;cin=1'b0; #10 a=1'b1;b=1'b1;cin=1'b1; end initial begin #100 $finish; end endmodule // FULL SUBTRACTOR:
RESULT : Thus the full subtractor has designed and verified the functionality and the output waveforms are observed.
EXPERIMENT: 4 DECODERS
4.1. 2 TO 4 LINE DECODER AIM: To design a 2x4 decoder and to write its verilog code in dataflow, behavioral and structural models, verify the functionality and its output in the simulation report. APPARATUS : Xilinx 9.2 installed PC. THEORY: The 74138 decodes one-of-eight lines based upon the conditions at the three binary select inputs and the three enable inputs. Two active low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. BLOCK DIAGRAM
TRUTH TABLE:
a b D0 D1 D2 D3 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1
Here a,b are two inputs and D0,D1,D2,D3 denote the outputs of the decoder which implies minterms of two input variables.
VERILOG CODE: 2X4 DECODER USING DATA FLOW MODELING STYLE `resetall `timescale 1ns/10ps module decoder24data(a,b,dout) ; input a,b; output [0:3]dout; assign dout[0]=(~a)&(~b); assign dout[2]=a&(~b); assign dout[1]=(~a)&b; assign dout[3]=a&b; endmodule 2X4 DECODER USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module decoder24st(a,b,dout) ; input a,b; output[0:3]dout; wire abar,bbar; not g1(abar,a); not g2(bbar,b); and g3(dout[0],abar,bbar); and g4(dout[1],abar,b); and g5(dout[2],a,bbar); and g6(dout[3],a,b); endmodule 2X4 DECODER USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module dec24_bh (a,b,D) ; input a,b; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
output [0:3]D; reg [0:3]D; always@(a or b) begin case({a,b}) 2'b00:D[0]=1'b1; 2'b01:D[1]=1'b1; 2'b10:D[2]=1'b1; 2'b11:D[3]=1'b1; default:D=4'b0000; endcase end endmodule 2 TO 4 LINE DECODER TEST BENCH: decoder24_bh U_0( .a .b ); //apply stimulus initial begin #5 a=1'b0;b=1'b0; #5 a=1'b0;b=1'b1; #5 a=1'b1;b=1'b0; #5 a=1'b1;b=1'b1; end initial begin #100 $finish; End Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab (a), (b),
.dout (dout)
4.2-3X8 LINE DECODER AIM: To design a 3*8 decoder and to write its verilog code in dataflow, behavioral and structural models, verify the functionality and its out put in the simulation report APPARATUS : Xilinx 9.2 installed PC. THEORY: The 74138 decodes one-of-eight lines based upon the conditions at the three binary select inputs and the three enable inputs. Two active low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. BLOCK DIAGRAM:
TRUTH TABLE:
a 0 0 0 0 1 1 1 1
b 0 0 1 1 0 0 1 1
c 0 1 0 1 0 1 0 1
D0 1 0 0 0 0 0 0 0
D1 0 1 0 0 0 0 0 0
D2 0 0 1 0 0 0 0 0
D3 0 0 0 1 0 0 0 0
D4 0 0 0 0 1 0 0 0
D5 0 0 0 0 0 1 0 0
D6 0 0 0 0 0 0 1 0
D7 0 0 0 0 0 0 0 1
Here a,b,c are the inputs and D0 to D7 are the outputs. 3TO8 LINE DECODER USING STRUCTURAL MODELING STYLE `resetall Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
`timescale 1ns/10ps module dec38st(a,b,c,dout) ; input a,b,c; output [0:7]dout; wire abar,bbar,cbar; not g1(abar,a); not g2(bbar,b); not g3(cbar,c); and g4(dout[0],abar,bbar,cbar); and g5(dout[1],abar,bbar,c); and g6(dout[2],abar,b,cbar); and g7(dout[3],abar,b,c); and g8(dout[4],a,bbar,cbar); and g9(dout[5],a,bbar,c); and g10(dout[6],a,b,cbar); and g11(dout[7],a,b,c); endmodule 3TO8 LINE DECODER USING DATA FLOW MODELING STYLE `resetall `timescale 1ns/10ps module dec38data (a,b,c,dout); input a,b,c; output [0:7]dout; assign dout[0]=(~a)&(~b)&(~c); assign dout[1]=(~a)&(~b)&c; assign dout[2]=(~a)&b&(~c); assign dout[3]=(~a)&b&c; assign dout[4]=a&(~b)&(~c); assign dout[5]=a&(~b)&c; assign dout[6]=a&b&(~c); Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
assign dout[7]=a&b&c; endmodule 3 TO 8 DECODER USING BEHAVIORAL MODELING STYLE module dec_behv(a,,b,c, D); input a,b,c; output [7:0] D; reg [7:0]D; always@(a or b or c) begin case({a,b,c}) 3'b000:D=8'b10000000; 3'b001:D=8'b01000000; 3'b010:D=8'b00100000; 3'b011:D=8'b00010000; 3'b100:D=8'b00001000; 3'b101:D=8'b00000100; 3'b110:D=8'b00000010; 3'b111:D=8'b00000001; default: D=8'b00000000; endcase end endmodule 3 TO 8 LINE DECODER TEST BENCH `resetall `timescale 1ns/10ps module dec38bh_tb; reg reg reg a; b; c;
wire [0:7] dout; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
dec38bh U_0( .a .b .c ); //apply stimulus initial begin #5 a=1'b0;b=1'b0;c=1'b0; #5 a=1'b0;b=1'b0;c=1'b1; #5 a=1'b0;b=1'b1;c=1'b0; #5 a=1'b0;b=1'b1;c=1'b1; #5 a=1'b1;b=1'b0;c=1'b0; #5 a=1'b1;b=1'b0;c=1'b1; #5 a=1'b1;b=1'b1;c=1'b0; #5 a=1'b1;b=1'b1;c=1'b1; end initial begin #100 $finish; end endmodule (a), (b), (c),
.dout (dout)
OUTPUT WAVEFORM:
EXPERIMENT: 5
ENCODERS
5.1. 4: 2 LINE ENCODER AIM: To design a 4:2 line encoder using behavioral, structural and data flow modeling styles and verified using the test bench APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
TRUTH TABLE:
D0 D1 D2 D3 X Y 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1
Here D0,D1,D2,D3 are the inputs and the X,Y are the outputs.
VERILOG CODE: 4 TO 2 LINE ENCODER USING BEHAVIORAL MODEL Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
module encoder42bh (D,X,Y); input [0:3]D; output X,Y; reg X,Y; always@(D) begin case(D) 4'b1000:begin X=1'b0;Y=1'b0;end 4'b0100:begin X=1'b0;Y=1'b1;end 4'b0010:begin X=1'b1;Y=1'b0;end 4'b0001:begin X=1'b1;Y=1'b1;end default:begin X=1'bz;Y=1'bz;end endcase end endmodule 4TO2 LINE ENCODER USING STRUCTURAL MODELING STYLE: `resetall `timescale 1ns/10ps module encoder42st(din,a,b) ; input [0:3]din; output a,b; or g1(a,din[2],din[3]); or g2(b,din[1],din[3]); endmodule 4TO2 LINE ENCODER USING DATAFLOW MODELING STYLE: `resetall `timescale 1ns/10ps module encoder42data(din,a,b) ; input [0:3]din; output a,b; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
assign a=(din[2])|(din[3]); assign b=(din[1])|(din[3]); endmodule 4TO 2 LINE ENCODER TEST BENCH `resetall `timescale 1ns/10ps module encoder42st_tb; reg [0:3] din; wire wire a; b;
encoder42st U_0( .din (din), .a (a), .b (b) ); //apply stimulus initial begin #5 din=4'b1000; #5 din=4'b0100; #5 din=4'b0010; #5 din=4'b0001; end initial begin #100 $finish; end endmodule // encoder42st_tb
5.2 . 8 : 3 LINE ENCODER Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
AIM: To design a 8 : 3 line encoder using behavioral, structural and data flow modeling styles and verified using the test bench. APPARATUS : Xilinx 9.2 installed PC. BLOCK DIAGRAM:
TRUTH TABLE:
D0 1 0 0 0 0 0 0 0
D1 0 1 0 0 0 0 0 0
D2 0 0 1 0 0 0 0 0
D3 0 0 0 1 0 0 0 0
D4 0 0 0 0 1 0 0 0
D5 0 0 0 0 0 1 0 0
D6 0 0 0 0 0 0 1 0
D7 0 0 0 0 0 0 0 1
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Z 0 1 0 1 0 1 0 1
Where D0 to D7 are inputs and X,Y,Z are outputs.
VERILLOG CODE: 8 TO 3 ENCODER USING DATAFLOW MODELING STYLE `resetall `timescale 1ns/10ps Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
module encoder83data (din,a,b,c); input [0:7]din; output a,b,c; assign a=din[4]|din[5]|din[6]|din[7]; assign b=din[2]|din[3]|din[6]|din[7]; assign c=din[1]|din[3]|din[5]|din[7]; endmodule 8 TO 3 ENCODER USING STRUCTURAL MODELING STYLE `resetall `timescale 1ns/10ps module encoder83st(din,a,b,c) ; input [0:7]din; output a,b,c; or g1(a,din[4],din[5],din[6],din[7]); or g2(b,din[2],din[3],din[6],din[7]); or g3(c,din[1],din[3],din[5],din[7]); endmodule 8 TO 3ENCODER USING BEHAVIORAL MODELING STYLE `resetall `timescale 1ns/10ps module encodr83bh (D,X,Y,Z); input [0:7]D; output X,Y,Z; reg X,Y,Z; always@(D) begin case(D) 8'b10000000:begin X=1'b0;Y=1'b0,Z=1'b0;end 8'b01000000:begin X=1'b0;Y=1'b0;Z=1'b1;end 8'b00100000:begin X=1'b0;Y=1'b1;Z=1'b0;end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
8'b00010000:begin X=1'b0;Y=1'b1;Z=1'b1;end 8'b10001000:begin X=1'b1;Y=1'b0,Z=1'b0;end 8'b10000100:begin X=1'b1;Y=1'b0,Z=1'b1;end 8'b10000010:begin X=1'b1;Y=1'b1,Z=1'b0;end 8'b10000001:begin X=1'b1;Y=1'b1,Z=1'b1;end default endcase end endmodule 8 TO 3 LINE ENCODER TEST BENCH: `resetall `timescale 1ns/10ps module encoder83st_tb; reg [0:7] din; wire wire wire a; b; c; :begin X=1'bz;Y=1'bz;Z= 1'bz;end
encoder83st U_0( .din (din), .a (a), .b (b), .c (c) ); //apply stimulus initial begin #5 din=8'b10000000; #5 din=8'b01000000; #5 din=8'b00100000; #5 din=8'b00010000; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
#5 din=8'b00001000; #5 din=8'b00000100; #5 din=8'b00000010; #5 din=8'b00000001; end initial begin #100 $finish; end endmodule // encoder83st_tb Output waveforms:
EXPERIMENT: 6 MULTIPLEXERS
6.1---2:1 MULTIPLEXER Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
AIM: To design a 2:1 multiplexer using behavioral, dataflow and structural models and verify its functionality using the test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
TRUTH TABLE: S Y 0 I0 1 I1 VERILOG CODE: 2:1 MUX USING DATA FLOW MODELING STYLE: `resetall `timescale 1ns/10ps module mux21data (a,b,sel,out); input a,b,sel; output out; assign out=(sel)?b:a; endmodule
2:1 MUX USING BEHAVIORAL MODELING STYLE: module mux_beh(i,s, y); input [1:0] i; input s; output y; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
reg y; always@(s) begin if(s==1'b0) begin y=i[0]; end; else begin y= i[1]; end end end endmodule 2:1 MUX USING STRUCTURAL MODELING STYLE:
`resetall
`timescale 1ns/10ps module mux21st(a,b,sel,out) ; input a,b,sel; output out; wire p; not g0(p,sel); and g1(out,p,a); and g2(out,sel,b); endmodule
2:1 MUX TEST BENCH: `resetall `timescale 1ns/10ps module mux21data_tb; reg a; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
reg b; reg sel; wire out; mux21data U_0( .a (a), .b (b), .sel (sel), .out (out) ); initial begin a=1'b0; b=1'b1; end initial sel=1'b0; always #5 sel=~sel; endmodule // mux21data_tb
6.2. 4:1 MULTIPLEXER AIM: To design a 4:1 multiplexer using behavioral, dataflow and structural models and verify its functionality using the test bench. APPARATUS : Xilinx 9.2 installed PC Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
BLOCK DIAGRAM:
TRUTH TABLE: S1 0 0 1 1 VERILOG CODE: 4:1 MUX USING DATA FLOW MODELING STYLE: `resetall `timescale 1ns/10ps module mux41data (datain,addr,out); input [0:3] datain; input[0:1]addr; output out; assign out=datain[addr]; endmodule S0 0 1 0 1 Y I0 I1 I2 I3
4:1 MUX USING STRUCTURAL MODELING STYLE:
`resetall
`timescale 1ns/10ps module mux41st(in,s,out) ; input [0:3]in; input [0:1]s; output out; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
wire [0:3]y; and g1(y[0],in[0],(~s[0]),(~s[1])); and g2(y[1],in[1],(~s[1]),s[0]); and g3(y[2],in[2],s[1],(~s[0])); and g4 (y[3],in[3],s[1],s[0]); or g5(out,y[0],y[1],y[2],y[3]); endmodule 4:1 MUX USING BEHAVIORAL MODELING STYLE: module mux_behv(i,s, y); input [3:0] i; input [1:0]s; output y; reg y; wire [3:0]i; wire [1:0]s; always@(s) begin case(s) 2'b00:y=i[0]; 2'b01:y=i[1]; 2'b10:y=i[2]; 2'b11:y=i[3]; default: y=1'bz; endcase end endmodule 4:1 MUX TEST BENCH: `resetall `timescale 1ns/10ps module mux41data_tb; reg [0:3] datain; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
reg [0:1] addr; wire out; mux41data U_0( .datain (datain), .addr (addr), .out ); initial begin datain=4'b0101; #5 addr=2'b00; #5 addr=2'b01; #5 addr=2'b10; #5 addr=2'b11; end initial begin #100 $finish; end endmodule // mux41data_tb (out)
6.3 8:1 MULTIPLEXER AIM: To design a 8:1 multiplexer using behavioral ,dataflow and structural models and verify its functionality using the test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
TRUTH TABLE: S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 Y I0 I1 I2 I3 I4 I5 I6 I7
Where S0,S1,S2 are inputs and Y is output VERILOG CODE: 8:1 MUX USING DATA FLOW MODEL `resetall `timescale 1ns/10ps module mux81data1(sel,i,out) ; input [0:2]sel; input [0:7]i; output out; wire [0:7]y; assign y[0]=(~sel[0])&(~sel[1])&(~sel[2]&i[0]); assign y[1]=(~sel[0])&(~sel[1])&(sel[2]&i[1]); assign y[2]=(~sel[0])&(sel[1])&(~sel[2]&i[2]); Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
assign y[3]=(~sel[0])&(sel[1])&(sel[2]&i[3]); assign y[4]=(sel[0])&(~sel[1])&(~sel[2]&i[4]); assign y[5]=(sel[0])&(~sel[1])&(sel[2]&i[5]); assign y[6]=(sel[0])&(sel[1])&(~sel[2]&i[6]); assign y[7]=(sel[0])&(sel[1])&(sel[2]&i[7]); assign out=y[0]|y[1]|y[2]|y[3]|y[4]|y[5]|y[6]|y[7]; endmodule
8:1 MUX USING STRUCTURAL MODELING STYLE: `resetall `timescale 1ns/10ps module mux81st (s,i,o); input [0:2]s; input [0:7]i; output o; wire [0:7]y; and g1(y[0],(~s[0]),(~s[1]),(~s[2]),i[0]); and g2(y[1],(~s[0]),(~s[1]),(s[2]),i[1]); and g3(y[2],(~s[0]),(s[1]),(~s[2]),i[2]); and g4(y[3],(~s[0]),(s[1]),(s[2]),i[3]); and g5(y[4],(s[0]),(~s[1]),(~s[2]),i[4]); and g6(y[5],(s[0]),(~s[1]),(s[2]),i[5]); and g7(y[6],(s[0]),(s[1]),(~s[2]),i[6]); and g8(y[7],(s[0]),(s[1]),(s[2]),i[7]); or g9(o,y[0],y[1],y[2],y[3],y[4],y[5],y[6],y[7]); endmodule 8:1 MUX USING BEHAVIORAL MODELING STYLE: `resetall `timescale 1ns/10ps module mux81bh(i,sel,o) ; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
input [0:7]i; input [0:2]sel; output o; wire [0:7]i; wire [0:2]sel; wire [0:7]y; reg o; always@(sel) begin case(sel) 3'b000: o=i[0]; 3'b001: o=i[1]; 3'b010: o=i[2]; 3'b011: o=i[3]; 3'b100: o=i[4]; 3'b101: o=i[5]; 3'b110: o=i[6]; 3'b111: o=i[7]; endcase end endmodule
8:1 MUX TEST BENCH: `resetall `timescale 1ns/10ps module mux81bh_tb; reg [0:7] i; reg [0:2] sel; wire o; Dept. of ECE-ECAD & VLSI Lab
mux81bh U_0( .i (i), .sel (sel), .o (o) ); initial begin i=8'b 10101010; #5 sel=3'b000; #5 sel=3'b001; #5 sel=3'b010; #5 sel=3'b011; #5 sel=3'b100; #5 sel=3'b101; #5 sel=3'b110; #5 sel=3'b111; end initial begin #200 $finish; end endmodule // mux81bh_tb
Output Waveform:
EXPERIMENT: 7 DEMULTIPLEXER
7.1. 1:4 DEMULTIPLEXER AIM: To design a 1X4 DEMULTIPLEXER and verify its functionality and check its simulation report. Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
Z0 DEMULTIPLEXER Z1 Z2 Z3
S0 TRUTH TABLE: S1
S1
S0 0 1 0 1
Z0
Z1 0 A 0 0
Z2 0 0 A 0
Z3 0 0 0 A
0 0 1 1
A 0 0 0
VERILOG CODE FOR 1:4 DEMULTIPLEXER: `resetall `timescale 1ns/10ps module demux14bh(x,z0,z1,z2,z3,s) ; input [0:1]s; input [0:3]x; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
output [0:3]z0; output [0:3]z1; output [0:3]z2; output [0:3]z3; wire [0:1]s; wire [0:3]x; reg [0:3]z0; reg [0:3]z1; reg [0:3]z2; reg [0:3]z3; always @(s or x) begin case(s) 2'b00: begin z0=x;z1=4'b0;z2=4'b0;z3=4'b0;end 2'b01: begin z1=x;z0=4'b0;z2=4'b0;z3=4'b0;end 2'b10: begin z2=x;z0=4'b0;z1=4'b0;z3=4'b0;end 2'b11: begin z3=x;z1=4'b0;z2=4'b0;z0=4'b0 ;end endcase end end module TEST BENCH FOR 1:4 DEMULTIPLEXER: `resetall `timescale 1ns/10ps module demux14bh_tb; reg [0:3] x; wire [0:3] z0; wire [0:3] z1; wire [0:3] z2; wire [0:3] z3; reg [0:1] s; demux14bh U_0( Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
.x (x), .z0 (z0), .z1 (z1), .z2 (z2), .z3 (z3), .s (s) ); initial begin x=4'b1010; #10 s=2'b00; #10 s=2'b01; #10 s=2'b10; #10 s=2'b11; end initial begin #50 $finish; end endmodule // demux14bh_tb
7.2--- 1:8 DEMULTIPLEXER AIM: To design a 1:8 DEMULTIPLEXER and verify its functionality and check its simulation report. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM: Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
Z0 Z1 Z2 Z3 DEMULTIPLEXER Z4 Z5 Z6 Z7
S0 TRUTH TABLE: S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 Z0 A 0 0 0 0 0 0 0
S1
S2
Z1 0 A 0 0 0 0 0 0
Z2 0 0 A 0 0 0 0 0
Z3 0 0 0 A 0 0 0 0
Z4 0 0 0 0 A 0 0 0
Z5 0 0 0 0 0 A 0 0
Z6 0 0 0 0 0 0 A 0
Z7 0 0 0 0 0 0 0 A
VERILOG CODE FOR 1:8 DEMUX: `resetall `timescale 1ns/10ps module demux18bh(x,y,s); input x; output [0:7]y; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
input [0:2]s; wire x; wire [0:2]s; reg [0:7]y; always@(x or s) begin case(s) 3'b000: begin y[0]=x;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0;y[6]=1'b0;y[7]=1'b0; end 3'b001: begin y[0]=1'b0;y[1]=x;y[2]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0;y[6]=1'b0;y[7]=1'b0; end 3'b010: begin y[0]=1'b0;y[1]=1'b0;y[2]=x;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0;y[6]=1'b0;y[7]=1'b0; end 3'b011: begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=x;y[4]=1'b0;y[5]=1'b0;y[6]=1'b0;y[7]=1'b0; end 3'b100: begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0;y[4]=x;y[5]=1'b0;y[6]=1'b0;y[7]=1'b0; end 3'b101: begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=x;y[6]=1'b0;y[7]=1'b0; end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
3'b110: begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0;y[6]=x;y[7]=1'b0; end 3'b111: begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0;y[4]=1'b0;y[5]=1'b0;y[6]=1'b0;y[7]=x; end endcase end endmodule TEST BENCH FOR 1:8 DEMULTIPLEXER: `resetall `timescale 1ns/10ps module demux18bh_tb; reg x; wire [0:7] y; reg [0:2] s; demux18bh U_0( .x (x), .y (y), .s (s) ); initial begin x=1'b1; #10 s=3'b000; #10 s= 3'b001; #10 s=3'b010; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
#10 s=3'b011; #10 s=3'b100; #10 s=3'b101; #10 s=3'b110; #10 s=3'b111; end initial begin #100 $finish; end endmodule // demux18bh_tb
EXPERIMENT: 8 COMPARATORS 8.1.1- BIT COMPARATOR

AIM: To design a one bit comparator using behavioral model and verify the functionality using test bench. Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM: a b aeb alb agb
1-bit 1 comparator
TRUTH TABLE: a 0 0 1 1 b Aeb alb agb 0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0
Where aeb denotes a equals b and alb denotes a less than b and agb denotes a greater than b. VERILOG CODE FOR 1-BIT COMPARATOR: module comparator1(a,b,aeb,agb,alb) ; input a; input b; output aeb,alb,agb; wire a,b; reg aeb,alb,agb; always@(a or b) begin if (a<b) begin alb=1'b1; {aeb,agb}=1'b0; end else if(a==b) begin {alb,agb}=1'b0; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
aeb=1'b1; end else begin {alb,aeb}=1'b0; agb=1'b1; end end endmodule
TEST BENCH FOR 1-BIT COMPARATOR: `resetall `timescale 1ns/10ps module bit1comparator_tb; reg a; reg b; wire alb; wire agb; wire aeb; bit1comparator U_0( .a (a), .b (b), .alb (alb), .agb (agb), .aeb (aeb) ); initial begin #10 a=1'b0;b=1'b0; #10 a=1'b0;b=1'b1; #10 a=1'b1;b=1'b0; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
#10 a=1'b1;b=1'b1; end initial begin #50 $finish; end endmodule // bit1comparator_tb
8.2 4- BIT COMPARATOR
AIM: To design a four bit comparator using behavioral model and verify using the functionality using test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM: Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
TRUTH TABLE:
a 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101
b 111 1 111 0 110 1 110 0 101 1 101 0 100 1 011 1 100 0 011 0 010 1 010
alb aeb agb 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
1 110 0 110 1 111 0 111 1
0 001 1 001 0 000 1 000 0
0 0 0 0
0 0 0 0
1 1 1 1
Where aeb denotes a equals b and alb denotes a less than b and agb denotes a greater than b VERILOG CODE: module comparator4(a,b,aeb,agb,alb) ; input [3:0] a; input [3:0] b; output aeb; output alb; output agb; wire [3:0]a; wire [3:0]b; reg aeb,alb,agb; always@(a or b) begin if (a<b) begin alb=1'b1; {aeb,agb}=1'b0; end else if(a==b) begin Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
{alb,agb}=1'b0; aeb=1'b1; end else begin {alb,aeb}=1'b0; agb=1'b1; end end endmodule 4 BIT COMPARATOR TEST BENCH `resetall `timescale 1ns/10ps module comparator4_tb; reg [3:0] a; reg [3:0] b; wire wire wire aeb; agb; alb;
comparator4 U_0( .a (a), .b (b), .aeb (aeb), .agb (agb), .alb (alb) ); initial begin a = 1111; #10 a = 0000; b = 0001; b = 0000; Dept. of ECE-ECAD & VLSI Lab
#10 #10 #10 #10 end initial begin
a = 1100; a = 0000; a = 0001; a = 0100;
b = 0001; b = 0011; b = 0001; b = 0001;
#50 $finish; end endmodule Output Waveform:
EXPERIMENT: 9 D-FLIP FLOP

9.1 D-FLIP FLOP WITH SYNCHRONOUS RESET AIM: To design a D-flip flop with synchronous reset in behavioral model and testing the functionality using test bench APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
TRUTH TABLE:
Clk 1 1 1 1
VERILOG CODE: `resetall
Q 0 0 1 1
D Q(n+1) 0 0 1 1 0 0 1 1
`timescale 1ns/10ps module dff_syn_rst (data,clk,reset,q); input data,clk,reset ; output q; reg q; wire data,clk,reset; always @ ( posedge clk ) if (reset) begin q <= 1'b0; end else begin q <= data; end endmodule TEST BENCH: `resetall `timescale 1ns/10ps module dff_syn_rst_tb; reg data; reg clk; reg reset; wire q; dff_syn_rst U_0( .data (data), .clk (clk), .reset (reset), .q ); initial Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab (q)
clk = 1'b0; always #5 clk = ~clk; initial begin #5 data=1; reset=1; #5 data=0; reset=1; #5 data=1; reset=0; #5 data=0; reset=0; end initial begin #50 $finish; end endmodule // dff_syn_rst_tb Output Waveform :
9.2 D-FLIP FLOP WITH ASYNCHRONOUS RESET
AIM: To design a D-flip flop with Asynchronous reset in behavioral model and testing the functionality using test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
TRUTH TABLE:
Clk 1 1 1 1
VERILOG CODE:
Q 0 0 1 1
D Q(n+1) 0 0 1 1 0 0 1 1
D-FLIP FLOP WITH ASYNCHRONOUS RESET

`resetall `timescale 1ns/10ps module dff_asyn_rst(data,clk,reset,q) ; Sri Indu College of Engineering & Technology
USING
BEHAVIORAL MODEL
input data,clk,reset ; output q; reg q; wire data,reset,clk; always @ ( posedge clk or posedge reset) begin if (reset) begin q <= 1'b0; end else begin q <= data; end end endmodule TEST BENCH: `resetall `timescale 1ns/10ps module dff_asyn_rst_tb; reg data; reg clk; reg reset; wire q; dff_asyn_rst U_0( .data (data), .clk (clk), .reset (reset), .q ); initial Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab (q)
clk = 1'b0; always #5 clk = ~clk; initial begin data=0;reset=0; #5 data=1;reset=0; #5 data=0;reset=1; #5 data=1;reset=1; end initial begin #50 $finish; end endmodule // dff_asyn_rst_tb Output Waveform:
EXPERIMENT: 10
IC 74x93 4 -BIT BINARY COUNTER AIM: To write the VHDL code for IC 74x93 4 -bit binary counter. APPARATUS : Xilinx 9.2 installed PC TRUTH TABLE: Q(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OUTPUT Q(2) Q(1) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Q(0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CIRCUIT DIAGRAM OF IC74X93:
VHDL CODE: --Program for 4-bit counter library IEEE; use IEEE.std_logic_1164.all; entity cnt is port ( clk0: in STD_LOGIC; mr0: in STD_LOGIC; mr1: in STD_LOGIC; clk1: inout STD_LOGIC; Q:inout STD_LOGIC_VECTOR(3 downto 0) ); end cnt; architecture cnt of cnt is Component tff -- T- flip flop instantiation port ( t : in STD_LOGIC; clk : in STD_LOGIC; clr_l : in STD_LOGIC; q,nq : out STD_LOGIC ); end component; signal clear : std_logic; begin Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
clear<= mr0 nand mr1; -- common reset inputs for mod2 and mod8 --counters CLK1<=q(0); --to work as asynchronous mod16 counter t1:tff port map('1',clk0,clear,Q(0),open);--t1,t2,t3,t4 create four T-flip flops t2:tff port map('1',clk1,clear,Q(1), open); t3:tff port map('1',Q(1),clear,Q(2), open); t4:tff port map('1',Q(2),clear,Q(3), open); end cnt;
Output Waveform:
EXPERIMENT: 11
T-Flip Flop
AIM: To write the VHDL code for T-Flip Flop. APPARATUS : Xilinx 9.2 installed PC VHDL CODE: library IEEE; use IEEE.std_logic_1164.all; entity tff is port ( t : in STD_LOGIC;--input to the T-flip flop clk : in STD_LOGIC;--Clock signal for T-flip flop clr_l : in STD_LOGIC;--active low clear input q,nq : out STD_LOGIC--actual and complemented outputs of T-flip flop ); end tff; architecture tff of tff is begin process(t,clk,clr_l) variable temp:STD_LOGIC:='0'; begin if (clr_l='0') then temp:='0'; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
elsif ((clr_l='1') and (clk'event and clk='0')) then--perfoms during falling edge if ( t='0') then temp:=temp; else temp:= not temp; end if; end if; q<= temp; nq<= not temp; end process; end tff;
Test bench entity tff_tb is end tff_tb; architecture behavior of tff_tb is component tff port(clk,t,clr,pre : in std_logic; tq,tbq : out std_logic); end component; signal clk,t,clr,pre : std_logic := '0'; signal tq,tbq : std_logic; constant clk_period : time := 1 us; begin uut: tff port map (clk => clk,t => t,clr => clr,pre => pre,tq => tq,tbq => tbq); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stim_proc: process begin wait for 10 us; clr<='1';pre<='1';wait for clk_period*10; clr<='1';pre<='0';wait for clk_period*10; clr<='0';pre<='1';wait for clk_period*10; clr<='0';pre<='0';wait for clk_period*10; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
t<='0';wait for clk_period*10; t<='1';wait for clk_period*7; t<='0';wait for clk_period; t<='1';wait for clk_period*8; end process; end; WAVEFORMS:
EXPERIMENT: 12
JK-Flip Flop
AIM: To write the VHDL code for JK-Flip Flop. APPARATUS : Xilinx 9.2 installed PC VHDL CODE: library IEEE; use IEEE.std_logic_1164.all; entity jk_ff is port ( jk
: in STD_LOGIC_VECTOR(1 downto 0); --jk(1)=J;jk(0)=K; clk,pr_l,clr_l : in STD_LOGIC; q,nq : inout STD_LOGIC ); end jk_ff; architecture jk of jk_ff is begin process(clk,pr_l,clr_l,jk) variable temp:std_logic:='0'; begin q<='0';nq<='1'; if (pr_l='1' and clr_l='0') then q<='0';nq<='1'; elsif (pr_l='0' and clr_l ='1') then Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
q<='1';nq<='0'; elsif (pr_l='1' and clr_l='1') then if (clk 'event and clk='0') then --performs during the falling edge of clock case jk is when "00"=>temp:=temp; when "01"=>temp:='0'; when "10"=>temp:='1'; when "11"=>temp:=not temp; when others=>null; end case; end if; q<=temp; nq<= not temp; end if; end process; end jk; JK- flip-flop entity jkff is port ( clk,clr,pre,j,k : in std_logic; q,qb : out std_logic); end jkff; architecture behavioral of jkff is signal q_temp:std_logic:='0'; begin process(clk,j,k,pre,clr) begin if(clr='1') then q_temp<='0'; elsif(pre='1') then q_temp<='1'; elsif(clk='1' and clk'event) then if(j='0' and k='1') then q_temp<='0'; elsif(j='1' and k='0') then q_temp<='1'; elsif(j='1' and k='1') then q_temp<=not q_temp; end if; end if; end process; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
q<=q_temp; qb<=not q_temp; end behavioral; Test bench entity jkff_tb is end jkff_tb; architecture behavior of jkff_tb is component jkff port(clk,clr,pre,j,k : in std_logic; q,qb : out std_logic ); end component; signal clk,clr,pre,j,k : std_logic := '0'; signal q,qb : std_logic; constant clk_period : time := 1 us; begin uut: jkff port map ( clk => clk,clr => clr,pre => pre,j => j,k => k,q => q,qb => qb); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stim_proc: process begin clr<='1';pre<='1';wait for clk_period*10; clr<='1';pre<='0';wait for clk_period*10; clr<='0';pre<='1';wait for clk_period*10; clr<='0';pre<='0';wait for clk_period*10; j<='0';k<='0';wait for clk_period*10; j<='0';k<='1';wait for clk_period*7; j<='1';k<='0';wait for clk_period*9; j<='1';k<='1';wait for clk_period*8; end process; end; WAVEFORMS:
EXPERIMENT: 13
SR-Flip Flop
AIM: To write the VHDL code for SR-Flip Flop. APPARATUS : Xilinx 9.2 installed PC VHDL CODE: entity srff is port ( s,r,clk : in std_logic; srq,srqb : out std_logic); end srff; architecture behavioral of srff is signal q_temp:std_logic:='0'; begin process(clk,s,r) begin if(clk='1' and clk'event) then if(s='0' and r='1') then q_temp<='0'; elsif(s='1' and r='0') then q_temp<='1'; elsif(s='1' and r='1') then q_temp<=X; end if; end if; end process; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
srq<=q_temp; srqb<= not q_temp; end behavioral; Test bench entity srff_tb is end srff_tb; architecture behavior of srff_tb is component srff port(s,r,clk : in std_logic; srq,srqb : out std_logic); end component; signal s,r,clk : std_logic := '0'; signal srq,srqb : std_logic; constant clk_period : time := 1us; begin uut: srff port map (s => s,r => r,clk => clk,srq => srq,srqb => srqb); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stim_proc: process begin wait for 10us; s<='0';r<='0';wait for clk_period*10; s<='0';r<='1';wait for clk_period*7; s<='1';r<='0';wait for clk_period*9; s<='1';r<='1';wait for clk_period*8; end process; end;
EXPERIMENT: 14 SHIFT REGISTERS

14.1 LEFT SHIFT REGISTER USING ASYNCHRONOUS RESET AIM: To design a 4-bit left shift register using asynchronous reset in behavioral model and testing the functionality using test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
Qa A
Da
Qb B
Db
Qc C
Dc
Qd D
Db
Ser
clk
TRUTH TABLE:
Clk Rese 0 t 1
Q 000
Ser 0
1 1 1 1
0 0 0 0
0 000 1 001 1 011 1 111 1
0 0 0 0
VERILOG CODE:
4-BIT LEFT SHIFT REGISTER WITH ASYNCHRONOUS RESET USING BEHAVIORAL MODEL
`resetall `timescale 1ns/10ps module lftshtas (q,ser,clk,rst); input rst,ser,clk; output q; wire rst,ser,clk; reg [3:0]q; always@(posedge clk or posedge rst) begin if(rst) q=4'b0000; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
else q={q[2:0],ser}; end endmodule 4-BIT LEFT SHIFT REGISTER TEST BENCH `resetall `timescale 1ns/10ps module lftshtas_tb; wire [3:0] q; reg reg reg ser; clk; rst;
lftshtas U_0( .q (q), .ser (ser), .clk (clk), .rst (rst) ); initial clk=1'b0; always #5 clk=~clk; initial begin ser=1'b0; #10 ser=1'b1; #10 ser=1'b0; #10 ser=1'b1; #10 ser=1'b0; #10 ser=1'b1; #10 ser=1'b0; end Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
initial begin rst=1'b0; #3 rst=1'b1; #6 rst=1'b0; end initial #100 $finish; endmodule
14.2 RIGHT SHIFT REGISTER USING ASYNCHRONOUS RESET AIM: To design a 4-bit right shift register using asynchronous reset in behavioral model and by testing the functionality using test bench. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM:
Qa A
Da
Qb B
Db
Qc C
Dc
Qd D
Db
clk
TRUTH TABLE:
Clk Rese 0 1 1 1 1 1 t 1 0 0 0 0 0
Q 000 0 100 0 110 0 111 0 111 1 111 1
S 0 0 0 0 0 1
VERILOG CODE: 4-BIT RIGHT SHIFT REGISTER WITH ASYNCHRONOUS RESET USING BEHAVIORAL MODEL `resetall `timescale 1ns/10ps module rhtshtas(q,si,clk,rst) ; input si,clk,rst; output q; wire si,clk,rst; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
reg[3:0] q; always@( posedge clk or posedge rst) begin if(rst) q=4'b0000; else q={si,q[3:1]}; end endmodule 4-BIT RIGHT SHIFT REGISTER TEST BENCH `resetall `timescale 1ns/10ps module rhtshtas_tb; wire [3:0] q; reg reg reg si; clk; rst;
rhtshtas U_0( .q (q), .si (si), .clk (clk), .rst (rst) ); initial clk=1'b0; always #5 clk=~clk; initial begin #10 si=1'b0; #10 si=1'b1; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
#10 si=1'b0; #10 si=1'b1; #10 si=1'b0; end initial begin rst=1'b0; #3 rst=1'b1; #6 rst=1'b0; end initial #100 $finish; endmodule // rhtshtas_tb
EXPERIMENT: 15
UNIVERSAL SHIFT REGISTER
AIM: To design UNIVERSAL SHIFT REGISTER and verify the functionalities along with their synthesis and simulation reports. APPARATUS : Xilinx 9.2 installed PC THEORY: The 74194 is a high speed 4 bit shift registers. This is called universal because is incorporates virtually all of the features a system designer may want in a shift register. The circuit provides parallel inputs, parallel outputs, right-shift and left-shift Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
serial inputs, operating-mode-control inputs, and a direct overriding clear line. In the parallel load mode, the unit functions as a set of four D flip-flops. The two mode control bits SI and SO provide four modes of operation: (SI, SO)=0 0: retain the present state (do nothing) 0 1: Shift Right (in the direction QA toward QD). 1 0: Shift Left (in the direction QD toward QA). 1 0: Parallel (Broadside)Load of A,B,C,D into QA,QB,QC,QD. BLOCK DIAGRAM: q clock reset ls rs sel pd Universal Shift register
VERILOG CODE USING BEHAVIORAL MODELING: `resetall `timescale 1ns/10ps module usr(clock,reset,ls,rs,sel,pd,q) ; input clock,reset,ls,rs,sel,pd; output q; wire clock,reset,ls,rs; wire[1:0]sel; wire[3:0]pd; reg[3:0]q; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
always@(posedge reset or posedge clock) begin if(reset) q<=4'b0000; else case(sel) 2'b00: ; //no operation 2'b01:q<={q[2:0],ls}; //shift left operation 2'b10:q<={rs,q[3:1]}; //right shift operation 2'b11:q<=pd; endcase end endmodule USR TEST BENCH: `resetall `timescale 1ns/10ps module usr_tb; reg reg reg reg clock; reset; ls; rs; // parallel load
reg [1:0] sel; reg [3:0] pd; wire [3:0] q; usr U_0( .clock (clock), .reset (reset), .ls .rs (ls), (rs),
.sel (sel), Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
.pd .q ); initial clock=1'b0;
(pd), (q)
always #5 clock=~clock; initial begin ls=1'b0; rs=1'b1; pd=4'b0000; sel=2'b11; #10 sel=2'b10; #40 sel=2'b01; #10 pd=4'b0000; #40 sel=2'b11; end initial begin reset=1'b0; #3 reset=1'b1; #6 reset=1'b0; end initial # 150 $finish; Endmodule OUTPUT WAVEFORM:
EXPERIMENT: 16 COUNTERS
16.1 UP COUNTER AIM: To design UP COUNTER and verify functionality along with its synthesis and simulation reports. APPARATUS : Xilinx 9.2 installed PC. BLOCK DIAGRAM: out Dept. of ECE-ECAD & VLSI Lab
clock reset enable Up counter
TRUTH TABLE: Clock Reset Enable Out 1 1 X 0000 2 0 1 0001 3 0 1 0010 4 0 1 0100 5 0 1 1000 6 0 1 1001 7 0 1 1010 8 0 1 1011 9 0 1 1100 10 0 1 1101
VERILOG CODE USING BEHAVIORAL MODELING: resetall `timescale 1ns/10ps module upcounterbh(clock,enable,reset,out) ; input clock,enable,reset; output [0:3]out; wire clock,reset,enable; reg [0:3]out; always@(posedge clock or reset) begin if (reset==1'b1) Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
begin out=4'b0000; end else if(enable==1'b1) begin out=out+4'b0001; end end endmodule
UPCOUNTER TEST BENCH: `resetall `timescale 1ns/10ps module upcounterbh_tb; reg reg reg clock; enable; reset;
wire [0:3] out; upcounterbh U_0( .clock (clock), .enable (enable), .reset (reset), .out ); // apply stimulus initial begin clock=1; reset=0; enable=0; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab (out)
#5 reset=1; #5 reset=0; enable=1; #100 enable=0; #10 $finish; end always begin #5 clock=~clock; end endmodule // upcounterbh_tb OUTPUTWAVEFORM:
Result : Thus the truth table of upcounter is verified, synthesis report is generated and simulation results are verified.
16.2 DOWN COUNTER AIM: To design DOWN COUNTER and verify functionality along with its synthesis and simulation reports. APPARATUS : Xilinx 9.2 installed PC BLOCK DIAGRAM: clock reset enable TRUTH TABLE: clock reset enable out 1 1 X 1111 2 0 1 1110 Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab Down counter
out
3 4 5 6 7 8 9 10 VERILOG CODE: `resetall `timescale 1ns/10ps
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1101 1100 1011 1010 1001 1000 0111 0110
module downcounterbh(clock,enable,reset,out) ; input clock,enable,reset; output [0:3]out; wire clock,reset,enable; reg [0:3]out; always@(posedge clock or reset) begin if (reset==1'b1) begin out=4'b1111; end else if(enable==1'b1) begin out=out-4'b0001; end end endmodule DOWN COUNTER TEST BENCH: `resetall `timescale 1ns/10ps module downcounterbh_tb; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
reg reg reg
clock; enable; reset;
wire [0:3] out; downcounterbh U_0( .clock (clock), .enable (enable), .reset (reset), .out ); initial begin clock=1; reset=0; enable=0; #5 reset=1; #5 reset=0; enable=1; #100 enable=0; #10 $finish; end always begin #5 clock=~clock; end endmodule // downcounterbh_tb Output Waveform : (out)
Result : Thus the truth table of Downcounter is verified, synthesis report is generated and simulation results are verified.
EXPERIMENT: 17 CARRY SAVE ADDER

AIM: To perform the Carry Save Adder operation using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module csa_3(y,a,b,c); output [4:0]y; input [3:0]a,b,c; wire [3:0]s,ca; wire w1,w2,w3; full_adder k1 (s[0],ca[0],a[0],b[0],c[0]); full_adder k2 (s[1],ca[1],a[1],b[1],c[1]); full_adder k3 (s[2],ca[2],a[2],b[2],c[2]); full_adder k4 (s[3],ca[3],a[3],b[3],c[3]); half_adder k8 (y[0],w1,s[0],ca[0]); Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
full_adder k5 (y[1],w2,s[1],ca[1],w1); full_adder k6 (y[2],w3,s[2],ca[2],w2); full_adder k7 (y[3],y[4],s[3],ca[3],w2); endmodule module full_adder(s,co,a,b,ci); input a,b,ci; output s,co; wire c1,c2,s1; half_adder x1(s1,c1,a,b); half_adder x2(s,c2,s1,ci); or(co,c1,c2); endmodule module half_adder(s,c,a,b); output s,c; input a,b; xor(s,a,b); and(c,a,b); endmodule
TEST BENCH: module tb_csa_3(); wire [4:0]y; reg [3:0]a,b,c; csa_3 t5 (y,a,b,c); initial begin a=4'b0010; b=4'b1010; c=4'b0110; end initial #100 $stop; initial $monitor($time,"a=%b,b=%b,c=%b,y=%b",a,b,c,y); endmodule BLOCK DIAGRAM:
RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT: Final Report: Device utilization summary: --------------------------Selected Device : 2s50pq208-5
Number of Slices: 0% Number of 4 input LUTs: 0% Number of bonded IOBs: 11% TIMING REPORT Clock Information: -----------------No clock signals found in this design 5 8 17 out of out of out of 768 1536 144
Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 13.700ns
RESULT: Elaborating the design. run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0a=0010,b=1010,c=0110,y=10000 Stopped at time : 100 fs : File "J:/Ravinder_MTech/VERILOG/csa.v" Stopped at line=31 file name=J:/Ravinder_MTech/VERILOG/csa.v
VERIFICATION: Hence Performance of the Carry Save Adder operation using tools of
simulation and synthesized and verified the Verilog HDL code.
EXPERIMENT: 18 Bit Binary Multiplier

AIM: To Perform the 4-Bit Binary Multiplier operation using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module mull_4bit(s,a,b); output [7:0] s; input [3:0] a,b; wire [23:0] w; and g1(s[0],a[0],b[0]); and g2(w[0],a[0],b[1]);and g3(w[1],a[0],b[2]);and g4(w[2],a[0],b[3]); and g5(w[4],a[1],b[0]); and g6(w[5],a[1],b[1]); and g7(w[6],a[1],b[2]);and g8(w[7],a[1],b[3]); Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
and g9(w[12],a[2],b[0]);and g10(w[13],a[2],b[1]); and g11(w[14],a[2],b[2]); and g12(w[15],a[2],b[3]); and g13(w[20],a[3],b[0]); and g14(w[21],a[3],b[1]); and g15(w[22],a[3],b[2]);and g16(w[23],a[3],b[3]); rca_4add x1 (w[11:8],s[1],{1'b0,w[2:0]},w[7:4],1'b0); rca_4add x2 (w[19:16],s[2],w[11:8],w[15:12],1'b0); rca_4add x3 (s[7:4],s[3],w[19:16],w[23:20],1'b0); endmodule TEST BENCH: module tb_mull_4bit(); reg [3:0] a,b; wire [7:0] s; initial begin a=4'b0010; b=4'b0001; end mull_4bit DUT (s,a,b); initial #100 $stop; initial $monitor($time,"s=%b,a=%b,b=%b,",s,a,b); endmodule BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT: Final Report: Device utilization summary: Selected Device : 2s50pq208-5 Number of Slices: 0% Number of 4 input LUTs: 0% Number of bonded IOBs: 9%
TIMING REPORT: Clock Information: No clock signals found in this design
5 9 14
out of out of out of
768 1536 144
Timing Summary: Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 15.553ns RESULT: run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0s=00010000,a=0010,b=0001, Stopped at time : 100.000 ns : File
VERIFICATION: Hence Performance of the 4-Bit Binary Multiplier operation using
tools of simulation and synthesised and verified the Verilog HDL code.
EXPERIMENT: 19
RING COUNTER
AIM: Using The Ring Counter operation using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module ring_counter(en,reset,clk,count); input en,reset,clk; output [3:0]count; reg [3:0]count; always @(posedge reset or posedge clk) if(reset) count=4'b0001; else if(en) count={count[2:0],count[3]}; endmodule TEST BENCH: module tb_ring_counter(); reg en,reset,clk; wire [3:0]count; ring_counter h4 (en,reset,clk,count); initial begin reset=1'b1; clk=1'b0; en=1'b0; #3 reset=1'b0; #50 reset=1'b0; end always #5 clk=~clk; always #5 en=~en; initial #200 $stop; initial $monitor($time,"en=%b,reset=%b,clk=%b,count=%b",en,reset,clk,count); endmodule
BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT:
Final Report: Device utilization summary: Selected Device : 2s50pq208-5 Number of Slices: 0% Number of Slice Flip Flops: 0% Number of bonded IOBs: 4% Number of GCLKs: 25% TIMING REPORT: Clock Information: Clock Signal | Clock buffer(FF name) Load | clk | BUFGP 4 Timing Summary: --------------Speed Grade: -5 Minimum period: 3.385ns (Maximum Frequency: 295.421MHz) Minimum input arrival time before clock: 3.410ns Maximum output required time after clock: 8.189ns Maximum combinational path delay: No path found
2 4 7 1
out of out of out of out of
768 1536 144 4
| |
RESULT: Elaborating the design. Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
Finished Elaboration.
Simulator is doing circuit initialization process. Finished circuit initialization process. 0en=0,reset=1,clk=0,count=0001 3en=0,reset=0,clk=0,count=0001 5en=1,reset=0,clk=1,count=0010 10en=0,reset=0,clk=0,count=0010 15en=1,reset=0,clk=1,count=0100 20en=0,reset=0,clk=0,count=0100 25en=1,reset=0,clk=1,count=1000 30en=0,reset=0,clk=0,count=1000 35en=1,reset=0,clk=1,count=0001 40en=0,reset=0,clk=0,count=0001 45en=1,reset=0,clk=1,count=0010 50en=0,reset=0,clk=0,count=0010 Stopped at time : 200.000 ns : File VERIFICATION: Hence using the Ring Counter operation using tools of simulation and synthesised and verified the Verilog HDL code.
EXPERIMENT: 20
PIPELINED ADDER
AIM: To Pipelined Adder operation using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module pipeline_adder(rega,regb,regc,d,clk,reset); output [1:0]rega,regb,regc; input [1:0]d; input clk,reset; reg [1:0]rega,regb,regc; always@(posedge clk or posedge reset) if(reset) begin rega=2'b00; regb<=2'b00; regc<=2'b00; end else begin rega=d; regb<=rega+1; regc<=regb+1; end endmodule TEST BENCH: module tb_pipeline_adder(); wire [1:0]rega,regb,regc; reg [1:0]d; reg clk,reset; pipeline_adder t6 (rega,regb,regc,d,clk,reset); initial begin d=2'b00; reset=1'b0; clk=1'b0; end always #20 d=d+1'b1; always #2 clk=~clk; always #200 reset=~reset; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
initial #200 $stop; initial $monitor($time,"rega=%b,regb=%b,regc=%b,d=%b,clk=%b,reset= %b",rega,regb,regc,d,clk,reset); endmodule BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT: Final Report: Device utilization summary: Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
Selected Device : 2s50pq208-5 Number of Slices: 0% Number of Slice Flip Flops: 0% Number of 4 input LUTs: 0% Number of bonded IOBs: 6% Number of GCLKs: 25% TIMING REPORT
5 8 2 10 1
out of out of out of out of out of
768 1536 1536 144 4
Clock Information: Clock Signal | Clock buffer(FF name) Load | clk | BUFGP 8 Timing Summary: --------------Speed Grade: -5 Minimum period: 5.188ns (Maximum Frequency: 192.753MHz) Minimum input arrival time before clock: 5.150ns Maximum output required time after clock: 7.999ns Maximum combinational path delay: No path found
| |
RESULT: Elaborating the design. Finished Elaboration. run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0rega=xx,regb=xx,regc=xx,d=00,clk=0,reset=0 2rega=00,regb=01,regc=xx,d=00,clk=1,reset=0 4rega=00,regb=01,regc=xx,d=00,clk=0,reset=0 12rega=00,regb=01,regc=10,d=00,clk=0,reset=0 14rega=00,regb=01,regc=10,d=00,clk=1,reset=0 18rega=00,regb=01,regc=10,d=00,clk=1,reset=0 20rega=00,regb=01,regc=10,d=01,clk=0,reset=0 24rega=01,regb=10,regc=10,d=01,clk=0,reset=0 26rega=01,regb=10,regc=11,d=01,clk=1,reset=0 32rega=01,regb=10,regc=11,d=01,clk=0,reset=0 38rega=01,regb=10,regc=11,d=01,clk=1,reset=0 42rega=10,regb=11,regc=11,d=10,clk=1,reset=0 44rega=10,regb=11,regc=11,d=10,clk=0,reset=0 50rega=10,regb=11,regc=00,d=10,clk=1,reset=0
Stopped at time : 50.000 ns : File VERIFICATION: Hence Pipelined Adder operation using tools of simulation and synthesised and verified the Verilog HDL code.
EXPERIMENT: 21
UNIVERSAL SHIFT REGISTER

AIM: Using Universal Shift Register to prove that it can shift both shifts right and left shifts using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module universal_shift(s0,s1,pin,left,rite,a,clk,clr); input s0,s1,left,rite,clk,clr; input [3:0]pin; output [3:0]a; reg [3:0]a; always @(posedge clk or posedge clr) if(clr) a=4'b0; else begin case ({s0,s1}) 2'b00:a=a; 2'b01:a={rite,a[3:1]}; 2'b10:a={a[2:0],left}; 2'b11:a=pin; endcase end endmodule TEST BENCH: module tb_universal_shift(); reg s0,s1,left,rite,clk,clr; reg [3:0]pin; wire [3:0]a; universal_shift h2 (s0,s1,pin,left,rite,a,clk,clr); initial begin clk=1'b1; clr=1'b0; s0=1'b1; s1=1'b1; #2 pin=4'b0001; #2 left=1'b1; rite=1'b1; #100 s0=1'b0; s1=1'b1; Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
#100 s0=1'b1; s1=1'b0; #100 s0=1'b0; s1=1'b0; end always #5 clk=~clk; always #50 clr=~clr; initial #150 $stop; initial $monitor($time,"s0=%b,s1=%b,pin=%b,left=%b,rite=%b,a=%b,clk=%b,clr= %b",s0,s1,pin,left,rite,a,clk,clr); endmodule BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT: Final Report: Device utilization summary: Selected Device : 2s50pq208-5 Number of Slices: 0% Number of Slice Flip Flops: 0% Sri Indu College of Engineering & Technology
4 4
out of out of
768 1536
Number of 4 input LUTs: 8 out of 1536 0% Number of bonded IOBs: 14 out of 144 9% Number of GCLKs: 1 out of 4 25% TIMING REPORT Clock Information: Clock Signal | Clock buffer(FF name) Load | clk | BUFGP 4 Timing Summary: --------------Speed Grade: -5 Minimum period: 4.673ns (Maximum Frequency: 213.995MHz) Minimum input arrival time before clock: 4.755ns Maximum output required time after clock: 8.449ns Maximum combinational path delay: No path found
| |
RESULT: Elaborating the design. Finished Elaboration. run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0s0=1,s1=1,pin=xxxx,left=x,rite=x,a=xxxx,clk=1,clr=0 2s0=1,s1=1,pin=0001,left=x,rite=x,a=xxxx,clk=1,clr=0 5s0=1,s1=1,pin=0001,left=1,rite=1,a=xxxx,clk=0,clr=0 15s0=1,s1=1,pin=0001,left=1,rite=1,a=0001,clk=0,clr=0 20s0=1,s1=1,pin=0001,left=1,rite=1,a=0001,clk=1,clr=0 25s0=1,s1=1,pin=0001,left=1,rite=1,a=0001,clk=0,clr=0 35s0=1,s1=1,pin=0001,left=1,rite=1,a=0001,clk=0,clr=0 40s0=1,s1=1,pin=0001,left=1,rite=1,a=0001,clk=1,clr=0 50s0=1,s1=1,pin=0001,left=1,rite=1,a=0000,clk=1,clr=1 55s0=1,s1=1,pin=0001,left=1,rite=1,a=0000,clk=0,clr=1 60s0=1,s1=1,pin=0001,left=1,rite=1,a=0000,clk=1,clr=1 70s0=1,s1=1,pin=0001,left=1,rite=1,a=0000,clk=1,clr=1 75s0=1,s1=1,pin=0001,left=1,rite=1,a=0000,clk=0,clr=1
Stopped at time : 75.000 ns : File VERIFICATION: Hence Using Universal Shift Register proved that it can shift both shifts right and left shifts using tools of simulation and synthesized and verified the Verilog HDL code.
EXPERIMENT: 22 SEQUENCE DETECTOR

AIM: Using Mealy machine to prove the output is a function of both present and input using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: //---------Mealy FSM-----------module mealy_st0(a,clk,reset,z); input a,clk,reset; output z; reg z; parameter st0=4'b00, st1=4'b01, st2=4'b10; reg[0:1]p_state, n_state; // sequential logic always@(posedge reset or posedge clk) if(reset) p_state<=st0; else p_state<=n_state; // combinational logic always@(p_state or a) case(p_state) st0: begin z=(a)?1:0; n_state=(a)?st2:st0; end st1: begin z=(a)?1:0; n_state=(a)?st0:st1; end st2: begin z=0; n_state=(a)?st1:st2; end default: begin z=0; n_state=st0; end endcase endmodule TEST BENCH:
module tb_mealy_st0(); reg a,clk,reset; wire z; mealy_st0 f4 (a,clk,reset,z); initial begin a=1'b0; clk=1'b0; reset=1'b0; #5 a=1'b1; #6 a=1'b0; #5 a=1'b1; #45 a=1'b0; end initial forever #3 clk=~clk; initial #100 $stop; initial $monitor($time,"a=%b,clk=%b,reset=%b,z=%b",a,clk,reset,z); endmodule
BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:
SYNTHESIZED OUTPUT: Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
Final Report: Device utilization summary: --------------------------Selected Device : 2s50pq208-5 Number of Slices: 0% Number of Slice Flip Flops: 0% Number of 4 input LUTs: 0% Number of bonded IOBs: 2% Number of GCLKs: 25% TIMING REPORT:
1 2 2 4 1
out of out of out of out of out of
768 1536 1536 144 4
Clock Information: Clock Signal Load | clk 2 Timing Summary: --------------Speed Grade: -5
| Clock buffer(FF name) | BUFGP
| |
Minimum period: 5.328ns (Maximum Frequency: 187.688MHz) Minimum input arrival time before clock: 3.810ns Maximum output required time after clock: 10.132ns Maximum combinational path delay: 9.764ns RESULT: Elaborating the design. Finished Elaboration. run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0a=0,clk=0,reset=0,z=0 3a=0,clk=1,reset=0,z=0 5a=1,clk=1,reset=0,z=1 6a=1,clk=0,reset=0,z=1 9a=1,clk=1,reset=0,z=0 11a=0,clk=1,reset=0,z=0 12a=0,clk=0,reset=0,z=0 15a=0,clk=1,reset=0,z=0 16a=1,clk=1,reset=0,z=0 18a=1,clk=0,reset=0,z=0 21a=1,clk=1,reset=0,z=1 24a=1,clk=0,reset=0,z=1 27a=1,clk=1,reset=0,z=1
30a=1,clk=0,reset=0,z=1 33a=1,clk=1,reset=0,z=0 36a=1,clk=0,reset=0,z=0 39a=1,clk=1,reset=0,z=1 42a=1,clk=0,reset=0,z=1 45a=1,clk=1,reset=0,z=1 48a=1,clk=0,reset=0,z=1 51a=1,clk=1,reset=0,z=0 Stopped at time : 100.000 ns : File "E:/mealy_st0.v" Line 56 Stopped at line=56 file name=E:/mealy_st0.v VERIFICATION: Using Mealy machine proved that output is a function of both presented and input using tools of simulation and synthesis and verified the Verilog HDL code.
EXPERIMENT: 23 LINEAR FEEDBACK SHIFT REGISTER

AIM: To perform the LFSR operation using tools of simulation and synthesis and to verify the Verilog HDL code. Tool For Simulation And Synthesis: Xilinx PROGRAME SOURCE CODE: module lfsr(y,clk,reset); parameter l=8; parameter is=8'b10010001; parameter [1:l]tc=8'b1111_0011; output [1:l]y; input clk,reset; reg [1:l]y; always@(posedge clk) if(reset==1'b0) y<=is; else begin y[1]<=y[8]; y[2]<=tc[7] ? y[1]^y[8]:y[1]; y[3]<=tc[6] ? y[2]^y[8]:y[2]; y[4]<=tc[5] ? y[3]^y[8]:y[3]; y[5]<=tc[4] ? y[4]^y[8]:y[4]; y[6]<=tc[3] ? y[5]^y[8]:y[5]; y[7]<=tc[2] ? y[6]^y[8]:y[6]; y[8]<=tc[1] ? y[7]^y[8]:y[7]; end endmodule //l=length //is=Initial state //tc=top coefficient
TEST BENCH: module tb_lfsr(); parameter l=8; parameter is=8'b10010001; parameter [1:l]tc=8'b1111_0011; wire [1:l]y; reg clk,reset;
lfsr m4 (y,clk,reset); initial begin reset=1'b0; clk=1'b0; end always #2 clk=~clk; always #5 reset=~reset; initial #200 $stop; initial $monitor($time,"y=%b,clk=%b,reset=%b",y,clk,reset); endmodule BLOCK DIAGRAM:
RTL SCHEMATIC:
WAVE FORMS:.
SYNTHESIZED OUTPUT: Sri Indu College of Engineering & Technology Dept. of ECE-ECAD & VLSI Lab
Final Report: Device utilization summary: --------------------------Selected Device : 2s50pq208-5 Number 0% Number 0% Number 0% Number 6% Number 25% of Slices: of Slice Flip Flops: of 4 input LUTs: of bonded IOBs: of GCLKs: 5 8 5 10 1 out of out of out of out of out of 768 1536 1536 144 4
TIMING REPORT: Clock Information: Clock Signal Load | clk 8 | Timing Summary: --------------Speed Grade: -5 Minimum Minimum Maximum Maximum
| Clock buffer(FF name) | BUFGP
| |
period: 4.648ns (Maximum Frequency: 215.146MHz) input arrival time before clock: 5.560ns output required time after clock: 8.799ns combinational path delay: No path found
RESULT: Elaborating the design. Finished Elaboration.

run all Simulator is doing circuit initialization process. Finished circuit initialization process. 0y=xxxxxxxx,clk=0,reset=0 2y=10010001,clk=1,reset=0 4y=10010001,clk=0,reset=0 5y=10010001,clk=0,reset=1 6y=10000111,clk=1,reset=1 8y=10000111,clk=0,reset=1 10y=10010001,clk=1,reset=0 12y=10010001,clk=0,reset=0 14y=10010001,clk=1,reset=0 15y=10010001,clk=1,reset=1 16y=10010001,clk=0,reset=1
18y=10000111,clk=1,reset=1 20y=10000111,clk=0,reset=0 22y=10010001,clk=1,reset=0 24y=10010001,clk=0,reset=0 25y=10010001,clk=0,reset=1 26y=10000111,clk=1,reset=1 28y=10000111,clk=0,reset=1 30y=10010001,clk=1,reset=0 32y=10010001,clk=0,reset=0 34y=10010001,clk=1,reset=0 35y=10010001,clk=1,reset=1 36y=10010001,clk=0,reset=1 38y=10000111,clk=1,reset=1 40y=10000111,clk=0,reset=0 42y=10010001,clk=1,reset=0 44y=10010001,clk=0,reset=0 45y=10010001,clk=0,reset=1 46y=10000111,clk=1,reset=1 48y=10000111,clk=0,reset=1 50y=10010001,clk=1,reset=0 Stopped at time : 50.000 ns : File VERIFICATION: Hence the LFSR operation using tools of simulation and synthesized and verified the Verilog HDL code.

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ECAD AND VLSI LAB MANUAL

IV B-TECH, ECE 1ST SEMESTER

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

ECAD AND VLSI LAB

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

EXPERIMENT: 1 LOGIC GATES

(not) (and) (or)

OUTPUT WAVEFORMS: AND GATE:

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Result : The truth tables of all logic gates are verified

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

TRUTH TABLE: a 0 0 1 1 b 0 1 0 1 carry 0 0 0 1 Sum 0 1 1 0

Sri Indu College of Engineering & Technology

and g2(a,b); endmodule

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

OUTPUT WAVEFORMS: FULL ADDER:

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

FULL ADDER S[3] Cout

FULL ADDER S[2]

FULL ADDER S[1]

FULL ADDER S[0]

S[3] TRUTH TABLE:

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

100 1 101 0 101 1 110 0 110 1 111 0 111 1

100 1 101 0 101 1 110 0 110 1 111 0 111 1

0010 0100 0110 1000 1010 1100 1110

001 1 010 1 011 1 100 1 101 1 110 1 111 1

Sri Indu College of Engineering & Technology

begin #160 $finish; end endmodule

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

TRUTH TABLE: a b Borr 0 1 0 0 Diff 0 1 1 0

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

a, b are inputs and borr, diff are the outputs.

Diff = a xor b Borr = ab

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

OUTPUT WAVEFORMS: HALF SUBTRACTOR

Sri Indu College of Engineering & Technology

Dept. of ECE-ECAD & VLSI Lab

a, b, c, denote inputs and diff, borr denote outputs.

Sri Indu College of Engineering & Technology