ABSTRACT

Power handling in modern coarse-grained reconfigurable arrays is a key problem in embedded processor circuits. This project presents a systematic approach to efficiently handle a very large number of power domains in modern coarse-grained reconfigurable arrays in order to tightly match the different computational demands of processed algorithms with corresponding power consumption. It is based on a new highly scalable and generic power control network and additionally uses the state-of-the-art common power format based front-to-backend design methodology for a fully automated implementation. The power management is transparent to the user and is seamlessly integrated into the overall reconfiguration process: reconfiguration-controlled power gating. The application of the proposed technique results in 60% active leakage and 90% standby leakage power reduction for several digital signal processing algorithms.

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ACKNOWLEDGEMENT

On the occasion of presenting this project phase 1 report, I wish to express my deep and prolongs of gratitude to a number of persons who have contributed to the completion of this first phase of my project. First of all I express my deep gratitude to Almighty, the supreme guide, for bestowing his blessings upon us in my entire endeavor. I express my deep gratitude to our Chairman Dr. P. Suyambu, who in all aspects encourages doing innovating work in current trends. I heart fully thank our Principal Prof. V. Gopi, his inspiring support for doing this project. I express my deep gratitude to our Head of the department Prof. S.Murugan for his valuable Moral support for doing this project work. I express my sincere gratitude to our Dean of Academics Prof. G. Antony for his valuable Moral support for doing this project work. I also express my heartfelt gratitude to Mrs. T. Jini M.E, my internal project guide for her valuable guidance and encouragement throughout my humble endeavor. Last but not the least I express my sincere thanks to all my friends who helped me for the successful completion of first phase of my project.

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TABLE OF CONTENTS

CHAPTER

TITLE ABSTRACT (ENGLISH) ABSTRACT (TAMIL) LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATIONS

PAGE
i ii iv v

vi 1 2 2 3 4 7 8 11

INTRODUCTION
1.1.1. EMBEDDED SYSTEM 1.1.2. CHARACTERISTICS OF EMBEDDED SYSTEM 1.1.3. ASIC AND FPGA SOLUTIONS 1.1.4. TOOL ARCHITECTURE OVERVIEW 1.1.5. 1.2. 1.2.1 DEBUGGING CGRA MESH-BASED ARCHITECTURES

2 3

REVIEW OF LITERATURE METHODOLOGY

3.1. REQUIREMENTS

16 22 22 23

REFERENCES

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LIST OF TABLES

TABLE

TITLE

PAGE

1.2

Timeline example of CGRA

LIST OF FIGURES FIGURE

1.1 1.2.1

TITLE
Embedded software tool architecture CGRA architecture & application mapping

PAGE
4 11

vi

LIST OF SYMBOLS AND ABBREVIATIONS

CGRA FPGA ASIC SoC SCI SSC ESSI USB GPIO ADC/DAC PE COARSE GRAINED RECONFIGURABLE ARCHITECTURES FIELD-PROGRAMMABLE GATE ARRAY APPLICATION-SPECIFIC INTEGRATED CIRCUIT SYSTEM ON A CHIP SERIAL COMMUNICATION INTERFACES SYNCHRONOUS SERIAL COMMUNICATION ENHANCED SYNCHRONOUS SERIAL INTERFACE UNIVERSAL SERIAL BUS GENERAL PURPOSE INPUT/OUTPUT ANALOG TO DIGITAL/DIGITAL TO ANALOG CONVERTER PROCESSOR ELEMENT

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