Synchronous Ethernet

Introduction
Ethernet is the ubiquitous communication platform in the home and enterprise networks. The simplicity, performance and cost effectiveness has made Ethernet technology a choice for transport networks as well. There are challenges in Ethernet technology to be adapted for carrier class high reliable managed networks. The inherently asynchronous Ethernet has another primary challenge of carrying time sensitive traffic like real time voice or video.

Asynchronous to Synchronous
Traditionally Ethernet nodes were running asynchronously to each other, with a defined +/-100ppm accuracy of the nominal frequency. Most of the traffic carried over Ethernet are asynchronous and are bursty in nature. For example, the email and internet IP Packet traffic, carried through Ethernet are bursty in nature with usually large chunks, but inconsistent in nature. Synchronization in its strict sense was not required because of the nature of the traffic going through. The transceiver buffers used to take care of the unexpected variations in the data flow. Moreover, on protocol layer, the triggers from hardware sent software control messages to Pause and Flow Control Ethernet frames. [Diagrams may need to re-draw]

As Ethernet started to carry real time voice and video, the traffic patterns changed. Such services demanded Constant Bit Rate or Variable bit Rate but contiguous nature of traffic which demanded all nodes in a network from source to destination to have same average frequency. The timing and synchronization techniques that were applied to the traditional circuit switched networks became relevant to the Ethernet networks as well. The networks equipment based on Ethernet networks that supports synchronous timing are described as Synchronous Ethernet (SyncE) networks.

Synchronized Clocks on Physical Layer

Ethernet Physic Layer Devices (PHY) convert the transmit logical signals to line-coded with embedded local clock and format them as balanced signals for transmission over copper or fibre cables for the transmit portion. On the receive side the clock data recovery mechanism of the PHYs recovers the signals, decode and convert them to logical levels. The extracted clock from the PHY is cleaned up to generate the system clocks and is propagated downstream on a network.

Standards Activities
ITU-T has formed standards for Ethernet networks that are equivalent to the synchronous transport networks. The Recommendation ITU-T G.8010/Y.1306 (2004), describes the Architecture of Ethernet layer networks. The Recommendation ITU-T G.8262/Y.1362, defines the Timing characteristic of a synchronous Ethernet Equipment Slave Clock(EEC).This recommendation defines the minimum requirements for timing devices used in synchronizing network equipment that supports synchronous Ethernet. The EEC characteristics define equipment limits and the implementations should comply with standalone and synchronous performance limits and be tolerant to input signal variations. The standards require the equipment to performs holdover functions and be resistant to impairments to the synchronization flow.

Rakon Oscillators for Synchronous Ethernet

Typically the EEC system is implemented with a PLL loop filtering the PHY extracted clock. The local oscillator used in the PLL system need to be compliant to the free running accuracy defined by G.8262. As the oscillator presents high pass filter effect in the loop, during wander generation, the time domain performance (MTIE and TDEV) of the oscillator needs to be within the limits defined by G.8262 at 0.1Hz, which is the loop bandwidth defined for Option 2 of the standards. When the synchronizer looses reference from the network, it enters a holdover state where the system continues to generate last known good frequency of the network. The performance of the system heavily depends on the oscillator at this stage. The frequency versus temperate performance and the ageing of the oscillator comes into picture on the holdover performance of the synchronizer. Rakon provides G.8262 compliant TCXOs for Synchronous Ethernet applications. Rakon has qualified oscillators for G.8262 after extensive time domain performance analysis of the clocks at various frequencies. Rakon has worked with numerous timing and synchronization silicon provides to qualify the solution for complete G.8262 compliance and some of the references are listed in alphabetical order below. Sl No 1 2 3 4 5 6 Chipset Vendors Analog Devices IDT Microsemi Semtech Silicon Labs Symmetricom Chipset Family AD954x IDT8V89316 ZL3013x, ZL3014x, ZL3016x ACS953x Si Soft Clock + Discrete TCXO Frequencies 12.8M 12.8M 20M, 24.576M 12.8M 12.8M

Requirement for low jitter clocks driving the PHYs is extremely important as the G.8262 requirements for output jitter is on system output and not on the PLL outputs. The PLL outputs may still go through frequency multipliers, PHYs, electrical to optical converters before reaching the physical line interface. Rakon G.8262 compliant oscillators provide industrys one of lowest phase noise and rms jitter in the 12K-20M range.

[ Additional description and diagrams: Base model description of Stratum 3 version of Pluto + (without mentioning Pluto+s name?) MTIE and TDEV plots of Pluto + with the G.8262 Masks Phase noise plot showing <300ps in the 12K-20M range on Pluto + Other XOs and VCXOs description in general]