CONTENTS

Title

Page No.

Table of Contents Preface List of Figures List of Tables List of Abbreviations List of Symbols List of Publications

i-iv v-vii viii-x xi xii-xvi xvii xviii

Chapter 1

Proposed Work 1.1 Overview 1.2 Literature Survey 1.3 Inferences drawn from the Literature Review 1.4 Problem Definition 1.5 Objectives 1.6 Design Flow 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.7 Design Specification MATLAB / Simulink Design VHDL / Xilinx System Generator Design Synthesis Reconfigurable Implementation

1-30 1-3 3-12 13-15 15-16 16-16 16-23 16-17 17-19 19-21 21-22 22-23 23-30

Reconfigurability

1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.8 Chapter 2

Field Programmable Gate Arrays FPGA Families The Xilinx Virtex-II Architecture Virtex-II Ordering FPGA Advantages FPGA Applications FPGAs vs ASICs

23-24 24-24 25-26 27-27 27-28 28-28 29-29 29-30 31-50 31-31

Summary

Wireless Communications: Architectures and Algorithms 2.1 2.2 Introduction Transmitter 2.2.1 Architectures

31-36 32-34
32-33 33-34

Direct up-conversion Transmitters

(a) (b) Classical I/Q transmitter Transmitters using - modulators

2.2.2

Polar modulation Transmitters

(a) (b) Polar transmitter Polar digital transmitter

34-36
34-35 35-36

2.3 2.4

Multiband and Multimode Approach Rectangular to Polar Conversion 2.4.1 Rectangular versus Polar Representations

36-37 37-39 38-39 39-42 39-40 40-40 41-41 41-42 42-42

2.5

Algorithm Classes 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 LUT-based Algorithms Polynomial approximation Algorithms Rational approximation Algorithms Quadratic Convergence Algorithms Linear Convergence Algorithms

2.6

CORDIC Algorithm 2.6.1 CORDIC Concept

42-49 43-43 44-45 45-45 45-49

46-47 47-48 48-49

2.6.2 Iterative Equations 2.6.3 Vectoring Mode

2.6.4 CORDIC Architectures

(i) (ii) (iii) Folded CORDIC Unfolded fully parallel CORDIC Unfolded parallel with pipelining CORDIC

2.7 Chapter 3

Summary

50-50 51-62 51-51 51-52 52-60 52-53 53-55 55-55 55-57 57-59 59-60 60-62 60-60 60-61 61-61 61-61 61-62

Proposed Model Development 3.1 3.2 3.3 Introduction Model Development Model Description 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 Constant Simulink Arrangement Scale Factor Quadrant Map Fine Angle Rotation Quadrant Correct

Special Purpose Blocks 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 System Generator Sine Wave Gateway In Gateway Out Scope

3.4 Chapter 4

Summary

62-62 63-78 63-65 65-73 73-77 77-78 79-82 79-79 80-82

Results and Discussions 4.1 4.2 4.3 4.4 MATLAB/Simulink Simulation ISE Simulation and Reconfigurable Implementation Comparison with other implementation strategies Summary

Chapter 5

Conclusion and Future Scope 5.1 5.2 Conclusion Future Scope

References

83-89

Preface
The impacts of advances in wireless technology deployment are the primary motivations for this research. The research and development of wireless communication systems has been rapidly growing for the last decades. When Guglielmo Marconi patented a system for transmitting Hertz oscillations in 1897, it was the first Wireless Communication System utilising RF spectrum. A little over one hundred and fifteen years later wireless communications are ubiquitous. Today one would be hard pressed to not to use wireless systems, whether listening to the radio, talking on a mobile phone, or browsing the Internet, or above all making use of a smart phone for just said purposes and for many more; all this through a wireless network. The necessity of high data rates wireless communication becomes important for the end-user, especially to support high mobility lifestyle always get connected, and demand for the multimedia communication, such as the video phone, live streaming, online gaming, and the Internet. Various wireless communication standards operate in a variety of different frequency bands which can be different from country to country. Furthermore, there are an increasing number of wireless communication standards that are employed by wireless communication devices. Current standards include Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Universal Mobile Telecommunications System (UMTS), CDMA2000, Long Term Evolution (LTE), and new standards are continually being developed. These standards provide for a variety of wireless signal specifications and formats, including different transmit level requirements, different modulation types, etc. For example, GSM employs Gaussian Minimum Shift Keying (GMSK), EDGE employs GMSK and 8-Phase Shift Keying (8-PSK), UMTS employs Code Division Multiple Access (CDMA), etc. As a result, current wireless communication systems require a multiband and multimode approach, so that several communication standards and applications can be incorporated in one device to satisfy the users, who expect mobility, ubiquitous connection and high data rates at the same time. It is seen that many wireless communication systems require the efficient conversion of rectangular to polar coordinates and in previous years, several algorithms and architectures

have been developed to speed up the process by reducing its iteration counts and through its pipelined implementation. Latency of computation, however, continues to be the major drawback of these algorithms as there are not efficient algorithms for the parallel implementation. Analysing the ability and potential of the multiplier-less algorithms, like CORDIC, it is thought to be suitable to work efficiently and effectively for the Rectangularto-Polar conversion. In this book, work done in the area of wireless transmitters has been reviewed and the focus is made on the necessity of rectangular to polar conversion. Various architectures and algorithms are reviewed to identify the problem by figuring out the existing challenges. It was observed that most of the work has been done on providing speed, precision and areaefficient solutions separately. The research in these areas has been continuing and there is still a need for developing faster, more precise, utilizing less-area and low cost solutions by working on these parameters simultaneously. Thus in order to bridge the gap between existing problems, the main aim of this Thesis work is to design a reconfigurable rectangular to polar converter to optimize Area and Speed by optimal resource consumption of the FPGA target device for various precision values using CORDIC Algorithm. This Thesis work presents an architecture for the efficient rectangular to polar conversion (RPC) for achieving true multiband and multimode wireless communications using fully parallel CORDIC, a Linear Convergence Algorithm. CORDIC falls into the class of shiftand-add algorithms it is a multiplierless method dominated by additions. FPGAs are very efficient at realising arbitrary precision adders, and thus the CORDIC algorithm is in many ways a natural fit for being implemented with FPGA architectures such as the Xilinx Virtex family of devices. The proposed design has been modelled using MATLAB/Simulink and System Generator software, synthesized with ISE 10.1 software and is implemented on Virtex-II XC2V30004FG676 Xilinx FPGA device. The proposed architecture provides 15-30 % savings in the FPGA slices when compared with the LUT-based method. The highest saving of 69.9 % is done with the 22-bit precision case. The 4-input LUTs also provide area savings from 18-40 % for the proposed fully parallel CORDIC architecture. Though the number of flip-flops is increased in the proposed design but the proposed design is not using any BRAM or multiplier, whereas the efficiency of the existing architecture has mostly been degraded due

to use of BRAMs and multipliers in the LUT-based approach. Furthermore, the proposed architecture increases the maximum clock frequency, which is 3.56 times for the 22-bit precision model and 3.01 times for the 12-bit precision model. The design is able to work at 177.620 MHz with 12-bit precision with low hardware utilization and is suitable for high speed wireless communications and provides an alternative for multiband and multimode operations that can support various modulation formats such as EDGE, GSM, CDMA, TDMA, and WCDMA and can overcome from the problems associated with I/Q based transmitter design too. This book will be useful for undergraduate, Masters and research students, who wish to study the relations among various architectures of wireless transmitters and different algorithms to implement these architectures.

List of Figures
Figure No. Fig. 1.1 Fig. 1.2 Fig. 1.3 Fig. 1.4 Fig. 1.5 Fig. 1.6 Fig. 1.7 Fig. 1.8 Fig. 2.1 Fig. 2.2 Fig. 2.3 Fig. 2.4 Fig. 2.5 Fig. 2.6 Fig. 2.7 Fig. 2.8 Fig. 2.9 Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Description Projection of mobile phone unit sales by standard Compound annual growth rate of mobile data traffic by application Design Flow System Generator block and its dialog window Detailed Design Flow A high-level view of the architecture of a Virtex-II FPGA FPGA configuration using a bitstream Virtex-II Ordering Example Classical I/Q Transmitter Transmitters using - modulators Polar transmitter Polar Digital Transmitter Example of Rectangular and Polar frequency domains Rotation in Circular Coordinates Folded CORDIC Architecture Unfolded fully parallel CORDIC Architecture Unfolded parallel with pipelining CORDIC Architecture Model Arrangement Proposed Model Constant Xilinx Block Simulink Arrangement Page No. 1 2 17 21 22 26 26 27 33 33 35 35 38 44 46 49 49 51 52 53 53

Fig. 3.5 Fig. 3.6 Fig. 3.7 Fig. 3.8 Fig. 3.9 Fig. 3.10 Fig. 3.11 Fig. 3.12 Fig. 3.13 Fig. 3.14 Fig. 3.15 Fig. 3.16 Fig. 3.17 Fig. 3.18 Fig. 3.19 Fig. 3.20 Fig. 3.21 Fig. 3.22 Fig. 3.23 Fig. 4.1 Fig. 4.2 Fig. 4.3 Fig. 4.4 Fig. 4.5 Fig. 4.6 Fig. 4.7

Trigonometric Function Simulink Block atan2 Trigonometric Function Simulink Block Real-Imag to Complex Simulink Block Abs Simulink Block Quadrant Map subsystem Slice Xilinx Block Negate Xilinx Block Mux Xilinx Block Fine Angle Rotation subsystem A Processing Element Add/Sub Xilinx Block Shift Xilinx Block Inverter Xilinx Block Quadrant Correct subsystem System Generator Xilinx Block Sine Wave Simulink Block Gateway In Xilinx Block Gateway Out Xilinx Block Scope Simulink Block Scope view of rectangular input x Scope view of rectangular input y Scope view of polar output magnitude X Scope view of polar output phase Z Magnitude Error Variance Phase Error Variance Simulation of the proposed architecture for 12-bit precision

54 54 54 55 56 56 56 57 57 58 58 59 59 60 60 61 61 61 61 63 63 64 64 65 65 66

(a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.8 Simulation of the proposed architecture for 14-bit precision (a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.9 Simulation of the proposed architecture for 16-bit precision (a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.10 Simulation of the proposed architecture for 18-bit precision (a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.11 Simulation of the proposed architecture for 20-bit precision (a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.12 Simulation of the proposed architecture for 22-bit precision (a) Simulation Waveforms (b) RTL Schematic Diagram Fig. 4.13 Fig. 4.14 Fig. 4.15 Fig. 4.16 Fig. 4.17 Fig. 4.18 Comparison Chart for the number of Multipliers Comparison Chart for the number of Slices Comparison Chart for the number of LUTs Comparison Chart for the number of Flip-flops Comparison Chart for the number of BRAMs Comparison Chart for the maximum working Frequency

66 66 67 67 67 68 68 68 69 69 69 70 70 70 71 71 71 74 74 75 75 76 76

List of Tables
Table No. Table 1.1 Table 1.2 Table 1.3 Table 2.1 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7 Table 4.8 Table 4.9 Table 4.10 Description Xilinx Devices Comparison Virtex-II Field-Programmable Gate Array Family Members Page No. 24 25

FPGA end markets and applications 28 Multiband & Multimode RF transceivers for various wireless applications 37 Error Variance Data Statistics Area Utilization for 12-bit precision Area Utilization for 14-bit precision Area Utilization for 16-bit precision Area Utilization for 18-bit precision Area Utilization for 20-bit precision Area Utilization for 22-bit precision Minimum Period and Maximum Frequency for different word-lengths Performance of the Proposed Arch Based on Fully Parallel CORDIC Performance of the Architecture Based on LUT-based Approach 64 66 67 68 69 70 71 72 72 73

List of Abbreviations
- ACLR ADPLL AM AR ASIC ASK BBR BOM BPF BRAM CAD CAGR CDMA CLB CMOS CORDIC D/A DAC DBPSK Delta-Sigma Adjacent Channel Leakage Ratio All Digital Phase-Locked Loop Amplitude Modulation Angle Recoding Application Specific Integrated Circuit Amplitude Shift Keying Binary to Bipolar Recoding Bill Of Materials Band Pass Filter Block Random Access Memory Computer Aided Design Compound Annual Growth Rate Code Division Multiple Access Configurable Logic Block Complementary Metal-Oxide Semiconductor COordinate Rotation DIgital Computer Digital-to-Analog Digital-to-Analog Converter Differential Binary Phase Shift Keying

DC DCO DCS DDR DPA DPD DQPSK DSL DSP DVB-T/H DVR EDGE EDIF EER EVM FM

Direct-up Conversion Digitally Controlled Oscillator Digital Cellular System Double Data Rate Digital Power Amplifier Digital Pre-Distortion Differential Quaternary Phase Shift Keying Digital Subscriber Line Digital Signal Processing Digital Video Broadcasting-Terrestrial/Handheld Digital Video Recorder Enhanced Data-rates for GSM Evolution Electronic Data Interchange Format Envelope Elimination and Restoration Error Vector Magnitude Frequency Modulation

FORTRAN FORmula TRANslator (Programming Language) FPGA FSK GFSK GMSK 3GPP GPRS GSM GUI HDL I/Q Field Programmable Gate Array Frequency Shift Keying Gaussian Frequency Shift Keying Gaussian Minimum Shift Keying 3rd Generation Partnership Project General Packet Radio Service Global System for Mobile Communications Graphical User Interface Hardware Description Language In-phase/Quadrature

IEEE IF IOB IP ISE JPEG LAN LCD LINC LO LPF LTE LUT LVDS MANs MAR MAT-file MATLAB MPEG MSR MUX NCD NCF NGC NGD NRE OFDM

Institute of Electrical and Electronics Engineers Intermediate frequency Input Output Blocks Intellectual Property Integrated Software Environment Joint Photographic Experts Group Local Area Network Liquid Crystal Display LInear amplification using Nonlinear Components Local Oscillator Low Pass Filter Long Term Evolution Look Up Table Low Voltage Differential Signalling Metropolitan Area Networks Micro-rotation Angle Recoding MATLAB-file MATrix LABoratory Moving Picture Experts Group Mixed Scaling Rotation Multiplexer Native Circuit Design Netlist Constraints File Native Generic Circuit Native Generic Database Non-Recurring Engineering Orthogonal Frequency Division Multiplexing

P2P PA PANs PAPR PCI PCS PE PM PSK PWM QAM RF RM ROM RPC RTL Rx SAW SDM SDR SOC SPA SQNR SRAM SRT TDMA Tx

Peer-to-Peer Power Amplifier Personal Area Networks Peak-to-Average Power Ratio Peripheral Component Interconnect Personal Communications Service Processing Element Phase Modulation Phase Shift Keying Phase Width Modulation Quadrature Amplitude Modulation Radio Frequency Rotation Mode Read Only Memory Rectangular to Polar Conversion Register Transfer Level Receiver Surface Acoustic Wave Sigma Delta Modulator Software Defined Radio System On Chip Switching Power Amplifier Signal-to-Quantization Noise Ratio Static Random Access Memory Sweeney, Robertson, and Tocher (a division algorithm, named for its creators) Time Division Multiple Access Transmitter

Tx-SAW UMTS VHDL VHSIC VLSI VM VSWR WCDMA WiFi WiMAX WLAN XPA XSG XST

Transmitter Surface Acoustic Wave Universal Mobile Telecommunications System VHSIC Hardware Description Language Very High Speed Integrated Circuit Very Large Scale Integration Vectoring Mode Voltage Standing Wave Ratio Wideband Code Division Multiple Access Wireless Fidelity Worldwide interoperability for Microwave Access Wireless Local Area Network Xilinx Power Analyzer Xilinx System Generator Xilinx Synthesis Tool

List of Symbols
I(t) Q(t) v(t) c A(t) (t) f(x) Pm(x) Qn(x) Rmn(x) xi, yi, zi xi+1, yi+1, zi+1 u i p Sp,i p,i K In-phase baseband signal Quadrature baseband signal RF signal RF carrier frequency Amplitude of the carrier Phase of the carrier arbitrary function Polynomial of degree m Polynomial of degree n Ratio of two polynomials Pm(x) and Qn(x) Input variables before ith iteration Output Variables after ith iteration vector on X-Y plane in CORDIC algorithm unknown angle calculated by micro-rotations direction of rotation radix of the number system type of coordinate system non-decreasing integer shift sequence elementary rotation angle Scale factor

xn, yn, zn

values of the coordinates after n iterations

List of Publications
[1] Anurag Vijay Agrawal, Rajesh Mehra, Reconfigurable Design of Rectangular to Polar Converter using Linear Convergence, International Journal of Computer Applications, Vol. 50, No.5, pp. 23-27, July 2012. [2] Anurag Vijay Agrawal, Rajesh Mehra, Efficient Rectangular to Polar Conversion for Multiband and Multimode Wireless Communications, International Journal of Computer Applications, Vol. 64, No.20, pp. 31-37, February 2013.