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74259 EasyHDL Model

This sample design shows how a digital part (a 74259) can be modelled

by a script written in EasyHDL. This is an alternative to modelling the

U1(D)

D Q0 U1 13 4
D Q0
U1
13
4

U1(Q0)

U1(Q1)

U1(A0)

device as an equivalent circuit and allows for great flexibility in creating

1 A0 // most of the script is hidden. To see the full script point at
1
A0
// most of the script is hidden. To see the full script point at it with the
// mouse (you may need to zoom in first) and press CTRL+E to Edit it.
*ENDSCRIPT
the functional behaviour of the device but also its timing based on
values selected from the 'value' of the device the script is attached
Q5
74259 EasyHDL Model
Labcenter Electronics,
53-55 Main Street,
Grassington,
North Yorkshire,
BD23 5AA
Fax: +44 (0)1756 752857
Tel: +44 (0)1756 753440
Email:
info@labcenter.co.uk
WWW:
http://www.labcenter.co.uk/
2
Q1
// This is the model for the 74XX259. To avoid cluttering the diagram
Q2
A1
3
Q3
A2
Q4
14
LE
c
i
n
o
r
t
c
e
s
U1(A2)
10 U1(Q6)
WIDTH=32u
START=32u
U1(LE)
WIDTH=32u
START=16u
U1(A1)
5 U1(Q2)
6 U1(Q3)
7 U1(Q4)
9 U1(Q5)
U1(MR)
11 U1(Q7)
PRIMITIVE=DIGITAL,SCRIPT
Q6
15
MR
Q7
12
74259
SCRIPT=74XX259
INIT=1
*SCRIPT PROGRAM 74XX259

your models.

The script is held on the schematic and can be seen below the 74259

and above the graph. Most of the script is hidden to avoid clutter - to see it

fully point at it with the mouse (you may need to zoom in to point at it

accurately) and press CTRL+E to Edit it. Notice that the script not only

models

a set of

to (in this example, a standard TTL family 74259).

For another example of EasyHDL modelling, see the 7493.DSN sample.

E

l

E l
E l

U2

PIC16F877

14

13

1

OSC2/CLKOUT

OSC1/CLKIN

RB0/INT

RB1

MCLR/Vpp/THV

RB2

2

RB3/PGM

4

3

7

5

6

RA3/AN3/VREF+

RA2/AN2/VREF-

RA5/AN4/SS

RA4/T0CKI

RA0/AN0

RA1/AN1

RC0/T1OSO/T1CKI

RB6/PGC

RB7/PGD

RB4

RB5

10

8

9

RE1/AN6/WR

RE0/AN5/RD

RC1/T1OSI/CCP2

RC3/SCK/SCL

RC2/CCP1

RE2/AN7/CS

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7
U2 PIC16F877 14 13 1 OSC2/CLKOUT OSC1/CLKIN RB0/INT RB1 MCLR/Vpp/THV RB2 2 RB3/PGM 4 3 7

I2C Memory Test

switch is closed only a read test is done. This can be used to verify memory persistence.

A switch on RA5 controls whether or not the write portion of the test is performed. When the

and the Status (RA0) line is toggled.

again verifying each byte as it is read. If an error occurs then the error code is written to Port D

The source code writes a series of values to address 0x0100-0x010F and then reads them back

This sample shows the functioning of the a 24C04A I2C serial memory.

STATUS WRITE PULLUP R2 ? MEMORY?
STATUS
WRITE
PULLUP
R2
?
MEMORY?
R3 30 35 36 37 U1 24C04A 3 6 SDA SCK R1 PULLUP 29 PULLUP ErrCode
R3
30
35
36
37
U1
24C04A
3
6
SDA
SCK
R1
PULLUP
29
PULLUP
ErrCode
SCK
SDA
5
WP
7
A1
2
A2
34
33
21
D6
D5
D4
D3
D2
D1
D0
D[0..7]
15
23
24
26
D7
22
25
27
39
40
20
19
38
18
17
16
28
0 SET 0 Q-OUTPUT NAND U2 RESET NAND U1 feedback connections from each NAND gate to
0
SET
0
Q-OUTPUT
NAND
U2
RESET
NAND
U1
feedback connections from each NAND gate to the other.
clear the Q output to logic 0. The circuits ability to remember its state derives from the
input returns to logic 1, the Q output 'remembers' its state. Similarly, the RESET input will
If the SET input is changed to logic 0, the Q output becomes set to logic 1. When the SET
The RS (reset-set) flip-flop is the simplest logic circuit that can exhibit memory behaviour.
Q-OUTPUT
BREAK ELSE QD = FALSE AFTER TDRD QC = FALSE AFTER TDRC QB = FALSE AFTER
BREAK
ELSE
QD = FALSE AFTER TDRD
QC = FALSE AFTER TDRC
QB = FALSE AFTER TDRB
countb = 0
QA = FALSE AFTER TDRA
counta = 0
ELSIF RA & RB
QD = countb & 4
QC = countb & 2
QB = countb & 1
QA = counta & 1
IF EVTID=EI_BOOT
QA = counta & 1 AFTER TDLHQA,TDHLQA
IF CKA=NEGEDGE
TDLHQC=21n : TDHLQC=23n : TDLHQD=34n : TDHLQD=34n
D TDLHQA=10n : TDHLQA=12n : TDLHQB=10n : TDHLQB=14n
: TDRB=26n
: TDRC=26n
: TDRD=26n
C TDRA=26n
CASE 7493 :
MAP ON VALUE
INT counta = INIT & 1, countb = INIT >> 1
PIN QA,QB,QC,QD
PIN CKA, CKB, RA, RB
TPROP TDHLQA, TDHLQB, TDHLQC, TDHLQD
TPROP TDLHQA, TDLHQB, TDLHQC, TDLHQD
For another example of EasyHDL modelling see the 74259.DSN sample file.
PRIMITIVE=DIGITAL
SCRIPT=7493
ENDIF
*ENDSCRIPT
ENDIF
ENDIF
QD = countb & 4 AFTER TDLHQD,TDHLQD
QC = countb & 2 AFTER TDLHQC,TDHLQC
QB = countb & 1 AFTER TDLHQB,TDHLQB
countb = countb+1
IF CKB=NEGEDGE
7493 EasyHDLModel
B
A
is a complete model of both the functional as well as timing behaviour of the 7493.
This sample shows a 7493 counter modelled using an EasyHDL script. The script
RESET
CLOCK
3
9
QC
8
QD
11
R0(1)
2
R0(2)
CKA
U1
7493
QB
1
CKB
12
QA
14
IPROP INIT=0
ALIAS RA=R0(1), RB=R0(2)
*SCRIPT PROGRAM 7493
53-55 Main Street,
7493 EasyHDLModel
WWW:
http://www.labcenter.co.uk/
info@labcenter.co.uk
Email:
Tel: +44 (0)1756 753440
Fax: +44 (0)1756 752857
BD23 5AA
North Yorkshire,
Grassington,
Labcenter Electronics,
i
s
c
n
o
r
t
c
e
El
TPROP TDRA, TDRB, TDRC, TDRD
ENDMAP
counta = counta+1