EE100B Lab Report #1: Current Mirrors and Cascodes

Zaza Nguyen 860967146 Partner: Andrew Yu Section 23 2-1-2013

Abstract: The objectives in this lab are to get familiar with the design of Current Mirrors and Sinks (and similarly Sources. It is to also understand the purpose, performance and design of cascade stages. In this lab we have successfully accomplished these goals, by proving that our experimental data does match up with theoretical data. In each part, a graph with a set of data is provided to show the understanding of current vs. drain-source voltage characteristics and how to calculate the resistance impedance with the input vs. output provided. Lab Procedures: Part 1: 1) Determine the appropriate to use in the circuit detailed in figure 1 by using the theoretical equations listed below. We know that ), so plugging them in: This is useful to comparing out experimental values to this value and analyze whether we are correctly doing this lab. We should get roughly the same value if my calculations are correct. 2) After assembling the circuit of Figure 1.1, we experimentally determine what will yield a by varying . We set the current to roughly .203 mA, which will determine the are looking for.

Figure 1.1: Current mirror (sink) 3) In this step, we do the opposite of the previous step by finding the different values of when the current reaches to .2mA. Keeping constant and varying from 0.0V to +2.0V (with emphasis on 0.0V 1.0V), we were able to tabulate . (Figure 1.2 in Analysis)

4) We plot M2s Drain current vs. Drain-Source voltage (Figure 1.3 in Data Analysis) 5) Perform a linear fit to the line in the saturation region and determine the output impedance from the slope of this line using the equation: . ( data are in Figure 1.3 in Analysis) 6) We plot the current gain by using our data from step 2 and a new table of data of . We compare the results and see if it differs from unity.

(Figure 1.4 in the analysis section) Part 2:

1) We assemble the circuit in Figure 2.1.

Figure 2.1: Current Mirror w/ Cascode stage using 2 (two) ICs CD4007

, because we want to have the lowest voltage for body effects in nMOSFETS. We do this while observing our Pin 14 and 7, and remembering to reconnect Pin 14 to the highest voltage in the circuit.
We still set 2) Vary until the appropriate M3 biasing is established so that . In our case, we had set which is the highest from part 1 of

this lab.

3) We vary

0.0V to +5.0V (with emphasis on 0.0V 1.0V) and tabulate data of . (Figure 2.2 in Data Analysis)

4) Plot , linear fit to the line in the saturation region and determine the output impedance by using this equation: . (Figure 2.3 in

Data Analysis)
5) Compare this output impedance with the one calculated in Part 1.

6) Compare this output impedance with the theoretical value calculated using the equation:

Analysis: Part 1:
1) ( )

Based on my calculations, my theoretical

2) Our determined 3)
VDD2 [V] 0.027 0.05 0.1 0.19 0.5 0.7 1 1.3 1.7 2 VDS2 [V] 0.027 0.05 0.1 0.19 0.5 0.7 1 1.3 1.7 2 IDS2 [uA] 24 41 86 132 189 193 195 196 197 198

ro = VDS2 / IDS2 0.001125 0.00122 0.00116 0.00144 0.00265 0.00363 0.00513 0.00663 0.00863 0.010101

Figure 1.2: Table of

being constant while

is changing from varying of

was kept constant and we varied from 0.0V to +2.0V (with emphasis on 0.0V 1.0V) to get a set of points that would reach . Using the equation , was found for each points which is used in step 5 of part 1 lab. 4)
250 200 Current [uA] 150 100 50 0 0 0.5 1 1.5 Voltage [V] 2 2.5

Part 1: ID2(VDS)

Figure 1.3: M2s Drain current vs. Drain-Source voltage From the linear fit, we can see that the slope is 0.01009, therefore the output impedance is . 6)
VDS2 0.027 0.05 0.1 0.19 0.5 0.7 1 1.3 1.7 2 Iout/Iin 0.99 0.99 0.99 0.99 0.99 0.99 0.99 0.99 0.99 0.99
Part 1 - #6 2.5 IOUT / IIN (VDS )
2

/ I (mA) I

1.5

OUT

IN

0.5

Figure 1.4: Data Table and Graph of Current gain

0.5

1.5

2.5 VDS (V)

2

3.5

4.5

In Figure 1.4 we can see that for the region of saturation, our results are very close to unity. However, it quickly diverges as we move in to the triode region, as well as when . Part 2: 2) Iout = Iref Iout = 198uA 1) VOUT [V]
0.02 0.05 0.11 0.21 0.3 0.5 0.75 1 2 3 12

3)
IOUT [uA] 13 34 71 120 152 184 194 196 197 197 198 ro casc = Vout / Iout 0.00154 0.00147 0.00155 0.00175 0.00197 0.00272 0.00387 0.0051 0.01015 0.01523 0.060606

Figure 2.2:

was kept constant and we varied

from 0.0V to +2.0V (with

In figure 2.2, we vary 0.0V to +5.0V (with emphasis on 0.0V 1.0V). This shows that in the emphasis between 0.0V and 1.0V, Iout is increasing until it reaches 2V, which is when it starts going into saturation mode. Even up to 12V for Vout, Iout is still roughly the same and does not change much. 4)

Part 2: Iout(Vout)
250 200 Iout [uA] 150 100 50 0 0 5 Vout [V] 10 15

Figure 2.3: Plot of From the linear fit, we can see that the slope is 0.000541, therefore the output impedance is . This is a great improvement of around an 18 times increase in output impedance. 5) The theoretical output impedance is given by: ( ) . This value is very close to our experimentally determined impedance and the discrepancy can easily be attributed to the relatively small number of data points collected that limit the accuracy of our linear fit for the saturation region of the graph. Problems: In this lab, there were very few errors that were made, and the errors were easily fixable. The first one is mistakenly plotting the variables in the wrong axis, which was definitely a crucial mistake. If graphs were plotted wrong, we would be analyzing it incorrectly which means there was no way of getting the correct value of the slope for saturation mode. Secondly, we were to reconnect Pin 14 to the highest voltage in the circuit which we did not check until after a few data points. That is also very important to the lab because once the voltage of pin 14 is no longer the highest voltage in the circuit, the data became will wildly inconsistent. However, this was not a problem in the analysis section, because we were able to simply use our data that was in the saturation mode and analyze.

Conclusions: In this lab, I felt like we had a successful lab which we completed our purposes. We were able to familiar ourselves with the design of Current Mirrors and Sinks and other similarly sources. We were also able to understand the purpose, performance and design of cascade stages. Using our data, we can see that we were on the right tracks, by proving that our experimental data does matches up when compared to the theoretical data we calculated for. Overall, the lab went well; we learned about build current mirror, sink, and source circuits as well as how they behave.