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ELECTRONICS & COMMUNICATION ENGINEERING

ELECTRONIC CIRCUITS LAB


1


1. COMMON EMITTER AMPLIFIER

Aim:

1. Design a COMMON - EMITTER amplifier for given specifications.
2. Simulate the designed amplifier.
3. Develop the hard ware for designed amplifier.
4. Compare simulation results with practical results.

Apparatus:

S.No Name of The Component/
Equipment
Specifications Qty

1

Transistor (BC107)
Icmax=100mA
P
D
=300mw
Vceo=45V
Vbeo=50V

1
2 Capacitors(designed values) Electrolytic type,
Voltage rating=
1.6v
3

3 Resistors (designed values) Power rating=0.5W
Carbon type
4

4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1

Theory: Common Emitter amplifier has the emitter terminal as the common
terminal between input and output terminals. The emitter base junction is forward
biased and collector base junction is reverse biased, so that transistor remains in
active region throughout the operation. When a sinusoidal AC signal is applied at
input terminals of circuit during positive half cycle the forward bias of base emitter
junction V
BE
is increased resulting in an increase in I
B
,The collector current I
c
is
increased by times the increase in I
B,
V
CE
is correspondingly decreased. i.e output
voltage gets decreased. Thus in a CE amplifier a positive going signal is converted
into a negative going output signal i.e..180
o
phase shift is introduced between output
and input signal and it is an amplified version of input signal.
Characteristics of CE amplifier

1. Large current gain (A
I
)
2. Large voltage gain (A
V
)
3. Large power gain(A
P
=A
I
.A
V
)
4. Phase shift of 180
o

5. Moderate input & output impedances.





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Circuit Diagram:

Design Equations:
Given Data:
V
CC
=12V, V
CE
= 6V, I
E
=2mA, =500, S 5.

1) For fixing the optimum operating point Q, mark the middle of the d.c load line
and the corresponding V
CE (Q)
and I
CQ
values are determined.
V
CE (Q)
= V
CC
/2 = 12/2 = 6V
2) Applying Kirchoffs voltage law to the collector circuit in the diagram
V
CC
I
CQ
(R
C
+R
E
) +V
CE(Q)
12 I
CQ
(R
C
+R
E
) +V
CE(Q)

R
C
+R
E
= 12-6/2mA =3K
3) By choosing drop across R
E
as 0.1 V
CC

V
E
= V
CC
/10 = 12/10 = 1.2V
4) In transistor since base current is very small, so I
E
is approximately equal to
I
C
( I
E

= I
C
) , I
E
R
E
= 1.2V ; I
C
R
E
= 1.2V ;
R
E
=1.2/(2 X10
-3
) = 600
5) R
C
= 3K - 0.6K = 2.4K
6) The voltage across R
2
is
V
R2
= V
BE
+I
E
R
E
V
CC
. R
2
/(R
1
+R
2
) = 0.6+1.2
R
1
/(R
1
+R
2
)=1.8/12=0.15 ----------------------------- (a)





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7) S = (1+ ) / (1+ R
E
/(R
E
+R
B
))
5= 101/ (1+(100 X 600/(600+R
B
)))
R
B
=2.5K
R
1
R
2
/ (R
1
+R
2
) = 2.5 K ------------------- (b)
From (a) & (b)
R
1
= 16.8 K R
2
= 2.96 K
Capacitor Calculations:
To provide low reactances almost short circuit at the operating frequency
f=1KHZ.
X
Ci
= 0.1R
B
, Xc
o
=0.1 R
C
, Xc
E
=0.1 R
E


8) X
Ci
= R
B
/ 10 = 2.5K/10=0.25
C
i
= 1/ (2fXc
i
) = 0.63F
9) Xc
o
= R
C
/10 = 0.24 X 10
3

C
o
=1/ (2fXco) = 0. 66 F
10) Xc
E
= R
E
/ 10 = 60
C
E
=1/ (2fXc
E
) = 2.6 F
Standard values of Resistors and capacitors R
1
=22K, R
2
=5.6K, R
C
=1K,
R
E
=220, C
i
= C
o
= 10 F, C
E
=100 F.

Procedure:

1. Connect the circuit as per the circuit diagram.
2. Apply the supply voltage , V
CC
=12V
3. Make sure that the transistor is operating point in active region by keeping
V
CE
half of V
CC.

4. Now feed an ac signal of 20mV at the input of the amplifier with different
frequencies ranging from 100HZ to 300 MHZ and measure the amplifier
output voltage.
5. Now calculate the gain in decibels at various input signal frequencies.
6. Draw a graph with frequencies on X-axis and gain in dbs on Y-axis. From
the graph calculate Bandwidth.










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Tabular form:

Simulation:
Input AC voltage, V
I
= 20 mV (peak-peak)

S.No
Frequency
(HZ)
Output Voltage(V
o
)
(Volts-p-p)
Gain in decibels
A
V=
20 log (V
o
/ V
i
)
1 50 0.17 18.58
2 100 0.2 20
3 500 0.75 31.48
4
1K 1.6 38.0
5 5K 4.6 47.23
6 10K 5.4 48.623
7 70K 6.2 49.54
8 100K 6.2 49.54
9 500K 6.2 49.54
10
1M 6.2 49.54
11
10M 5.6 48.94
12
70M 3.2 44.08
13
200M 1.2 35.56
14
300M 0.8 32.04








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Practical:

Input AC voltage, V
I
= 20 mV (peak-peak)

S.No Frequency (HZ)
Output Voltage (V
o
)
(Volts-p-p)
Gain in decibels
A
V
=20 log (V
o
/ V
I
)
1 20 0.1 13.97
2 50 0.15 17.50
3 70 0.2 20.00
4 300 0.3 23.52
5 500 0.75 31.48
6 1K 1.2 35.56
7 10K 6.1 49.68
8 50K 6.1 49.68
9 70K 6.1 49.68
10 100K 6.1 49.68
11 200K 6.1 49.68
12 500K 6.1 49.68
13 1M 6.1 49.68
14 10M 5.6 48.94
15 200M 1.2 35.56
16 300M 1.0 33.97








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Model graph:

Observations:
Simulated Practical

Maximum gain (A
v
) 49.54 dB 49.68dB
Lower cutoff frequency (F
L
) 5 KHz 5.5 KHz
Upper cutoff frequency (F
H
) 40MHz 45MHz
Band width (B.W) = (F
H
F
L
) 39.9MHz 38.9MHz
Gain bandwidth product = A
v
(B.W) 1.98GHz 2.23GHz

Precautions:

1. Connections must be given very carefully.
2. Readings should be noted without any parallax error.
3. The applied voltage, current should not exceed the maximum rating of the
given transistor.

Inferences: A maximum gain of 49.54 dB and a B.W of 39.9MHZ is obtained
from simulation, and a maximum gain of 49.68 dB and a B.W of 38.9 MHZ is
obtained from Practical circuit.
Result: A Common emitter amplifier with given specifications is designed and
simulated. Simulation and practical results are compared and verified.












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Questions & Answers

1. What are the characteristics of C.E amplifier?
a. 1.Moderate input and output impedances.
2. High voltage gain.
3. High current gain.
4. High power gain.
2. What is the main application of CE amplifier?
a. It is mostly used as a Audio Signal Voltage Amplifier.

3. What is meant by Bandwidth of an amplifier?
a. The range of frequency over which gain is equal to or greater than 70.7% of
maximum gain.
4. Find the phase relation b/w input and output?
a. The phase relation b/w the input and output voltage can be determined when V
i

increases in positive direction. It increases the base emitter voltage V
BE
. An
increase in V
BE
raises the level of I
C
. There by increasing the drop across R
C
.
V
CC
= V
O
+I
C
R
C
=> V
O
=V
CC
-I
C
R
C
Thus as V
i
increase in positive direction, V
C
goes in negative direction and vice
versa. This shows that amplifier o/p voltage is 180
o
out of phase with input
voltage.

5. Measure R
i
, R
O
and A
i
of a circuit?
a. Zi = R
B
// Z
B
where Z
B
=R
E

R
B
= R
1
//R
2

Z
O
= (1/h
oe
)//R
C
= R
C

Voltage gain = -(R
C
//R
L
)/R
E

The value of collector resistance R
C
mainly effects voltage gain. Gain also varied by
varying R
E
. If R
E
varies Q point is varies.
6. Define operating point?
a. For proper operating of a Transistor, whether the signal is present or not,a fixed
level of currents and voltages are required. These values of current and voltages
define the point, at which transistor operates. This point is called operating point.









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7. Proof for the circuit/BJT is in active region operation?
a.




8. Which component in the circuit effects the gain and bandwidth of an amplifer?

a. Voltage gain = - (R
C
//R
L
)/R
E

The value of collector resistance R
C
mainly effects voltage gain. Gain also
varied by varying R
E
. If R
E
varies Q point is varies.






















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2. COMMON SOURCE AMPLIFIER

Aim:
1. Design a COMMON - SOURCE amplifier for given specifications.
2. Simulate the designed amplifier.
3. Develop the hard ware for designed amplifier.
4. Compare simulation results with practical results.

Apparatus:

S.No Name Of The
Component/Equipment
Specifications Qty
1 Field Effect Transistor
(BFW10)
I
GS
=10mA
P
D
=300mW
V
GS
= -30V
V
DG
=-30V

1
2 Capacitors(designed values) Electrolytic type Voltage
rating= 1.6v
3

3 Resistors (designed values) Power rating=0.5W
Carbon type
4
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1


Theory: In common source amplifier circuit source terminal is made common to
the other two terminals. In common source amplifier circuit input is applied between
gate and source and output is taken from drain and source. The coupling capacitors
C
1
and C
2
are used to isolate the D.C biasing from the applied ac signal, and acts as
short circuit for the ac analysis. The high frequency characteristics of the FET
amplifier are determined by the interelectrode and wiring capacitance.
The CS amplifier which provides good voltage amplification is most
frequently used. In cascade amplifier input impedance of the second stage acts as
shunt across output of first stage and R
d
is shunted by C
i
. Since the reactance
decreases with increasing frequencies, the output impedance will be low at high
frequencies, this will result in decreasing the gain at high frequencies.










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Circuit Diagram:-



















Design Equations:

Given data:
= 50,r
d
= 46K , g
m
= 2 m mho, I
D
= 4 mA, V
Ds
= 8V , V
Gs
= -2V , V
DD
= 30V ,
V
gn
= 12V

1) To calculate R
D
&R
S


Applying Kirchoffs voltage law to the drain circuit in the diagram
V
DD
= I
D
R
D
+V
DS
+V
S
V
DD
= I
D
(R
D
+R
S
)+(V
DD
/2) (since V
Ds
= I
D
R
s
so =V
DD
/2)
R
D
+R
S
= 15/(4 * 10
-3
) = 3.75k
Assume R
s
= 1K
R
D
=3.75k - R
S
=2.75K
2) As voltage divider bias in the circuit
R
GS
= R
1
// R
2
= 100M
Capacitor calculations:

To provide low reactances almost short circuit at the operating frequency
f=1KHZ. X
Cs
= 0.1R
s
, Xc
i
=0.1 R
gs
, Xc
o
=0.1 R
D






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3) Xc
s
= (Rs/10) =100
C
S
= 1/(2fXc
S
) = 1.59F
4) Xc
i
= Rgs/10 = 319
C
i
= 1/(2fXc
1
) = 1.59 nF
5) Xc
o
= R
D
/10 = 275
C
o
= 1/(2fXc
2
) = 0.578F
Standard values
R
D
=6.2K , R
s
= 1.5K ,R
G
=4.7K , C
i
=0.1F, C
o
= 0.1F, C
s
= 40F.

Procedure:-

1. Connect the circuit as per the circuit diagram.
2. Apply supply voltage, V
DD
of 12V.
3. Now feed an AC signal 20mV at the input of the amplifier with different
frequencies ranging from 100HZ to 100 MHZ and measure the amplifier
output voltage.
4. Now calculate the gain in decibels at various input signal frequencies.
5. Draw a graph with frequency on X- axis and gain in dB on Y- axis. From
graph calculate bandwidth.
Tabular Form:

Simulation :
ac Input voltage V
I
=20mV (peak-peak)


S.No

Frequency (Hz)

Output Voltage(V
o
)
(Volts-p-p)
Gain in decibels
A
V
=20 log (V
o
/ V
i
)
1 100 0.12 15.0563
2
200 0.18 19.0848
3
500 0.32 24.082
4
700 0.36 25.1054
5 1K 0.4 26.0205
6 3K 0.43 26.6487
7
5K 0.43 26.6487
8
10K 0.43 26.6487
9
50K 0.43 26.6487
10
1M 0.43 26.6487
11
10M 0.43 26.6487
12
50M 0.39 25.8007
13
70M 0.35 24.8607
14
100M 0.29 23.2273





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Practical:
ac Input voltage V
I
=20mV (peak-peak)


S.No Frequency (Hz)
Output Voltage(V
o
)
(Volts-p-p)
Gain in decibels
A
V
=20 log (V
o
/ V
i
)
1 200 0.18 19.08
2
500 0.32 24.08
3
700 0.36 25.10
4
1K 0.4 26.02
5 5K 0.41 26.23
6 10K 0.41 26.23
7
30K 0.41 26.23
8
50K 0.41 26.23
9
1M 0.41 26.23
10
3M 0.41 26.23
11
7M 0.41 26.23
12
10M 0.39 25.80
13
20M 0.36 25.10
14
60M 0.28 22.92






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Model Graph:














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Observations:

Simulated Practical

Maximum gain (A
v
) 26.64 dB 26.23 dB
Lower cutoff frequency (f
L
) 500Hz 700Hz
Upper cutoff frequency (F
H
) 90MHz 100MHz
Band width (B.W) = (F
H
F
L
) 89.9MHz 99.9MHz
Gain bandwidth product = A
v
(B.W) 2.39GHz 2.622GHz

Precautions:

1. Connections must be made very carefully.
2. Readings should be noted without any parallax error.
3. The applied voltage and current should not exceed the maximum ratings of
the given transistor.

Inferences: A maximum gain of 26.64 db and a B.W of 89.9MHz is obtained from
simulation and a maximum gain of 26.23 db and a B.W of 99.9 MHz is obtained from
Hardware.

Result: A common source amplifier with given specifications is designed and
simulated. Simulation and practical results are compared.

Question & Answers

1. What is meant by Transconductance with respect to JFET?
a. The control that gate-source voltage has over the drain current is measured by
Transconductance of a JFET. It is defined as the ratio of change in drain current to
Change in gate-source voltage.

2. What are the characteristics of CS amplifier?
a. 1. High input impedance.
2. High voltage gain.
3. Phase shift of 180 degrees between input and output.
3. What is Amplification Factor ()?
a. It is defined as the ratio of small change in drain voltage to the small change in
gate voltage, keeping the drain current constant
=V
ds
/ V
gs






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4. Define operating point?
a. For proper operating of a Transistor, whether the signal is present or not , a fixed
level of currents and voltages are required. These values of current and voltages
define the point, at which transistor operates. This point is called operating point.
5. Which component in the circuit effects the gain and bandwidth of an amplifer?
a. Voltage gain A
V
=(- R
D
)/( R
D
+r
d
).
The value of drain resistance R
D
mainly effects voltage gain. Gain also
varied by varying R
S
. If R
S
varies Q point is varies.
























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3. TWO STAGE RC COUPLED AMPLIFIER

Aim:
1. Design two stage RC coupled amplifier for given specifications.
2. Simulate the designed amplifier.
3. Develop the hard ware for designed amplifier.
4. Compare simulation results with practical results.
Apparatus:

S.No Name of The
Component/equipment
Specifications Qty
1 Transistor (BC-107) Icmax=100mA
P
D
=300mW
Vceo=45V
Vbeo=50V

02
2 Capacitors(designed values) Electrolytic type
Voltage rating= 1.6v
05

3 Resistors (designed values) Power rating=0.5W
Carbon type
09
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1

Theory: When two amplifiers are connected, in such a way that the output signal
of first serves as the input signal of second, the amplifiers are said to be connected in
cascade. Cascading is done to increase the gain of the amplifier.
Each stage of the cascade amplifier should be biased at its designed
level. It is possible to design a Multistage cascade in which each stage is separately
biased and coupled to the adjacent stage using blocking or coupling capacitors. In
this circuit each of the two capacitors c
1
& c
2
isolate the separate bias network by
acting as open circuits to dc and allow only signals of sufficient high frequency to
pass through cascade.











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Circuit Diagram:


Design equations:
Given Data:
h
fe1
= h
fe2
= 200, R
L
=10,I
E1
= I
E2
=1mA, s
1
= s
2
=8, f=100HZ, V
CC
=12v

1) For fixing the optimum operating point Q, mark the middle of the d.c load line
and the corresponding V
CE (Q)
and I
CQ
values are determined.
V
CE (Q)
= V
CC
/2 = 12/2 = 6V
2) By choosing drop across R
E
as 0.1 V
CC

V
E
= V
CC
/10 = 12/10 = 1.2V
3) In transistor since base current is very small, so I
E
is approximately equal to
I
C
( I
E

= I
C
) , I
E
R
E
= 1.2V ; I
C
R
E
= 1.2V
R
E
= V
E
/ I
E
=1.2/1mA =1.2K
4) Applying Kirchoffs voltage law to the collector circuit in the diagram
R
C
= (V
CC
V
CE
V
E
) / I
C
= (12 -6-1.2)/1mA = 4.8K
5) The voltage across R
2
is
V
BB
= V
CC
* R
2
/ (R
1
+ R
2
) --------------- (1)
V
BB
= V
BE
+ I
E
R
E

= 0.6 + (10
-3
) (10
3
*1.2)
= 1.8V -------------------- (2)








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Substitute (2) in (1)
1.8 = 12 R
2
/ (R
1
+R
2
)
R
2
= 0.1761 R
1
------------------ (a)
6) S=1+ R
1
R
2
/ (R
1
+R
2
) R
E

8 = 1+ R
1
R
2
/(R
1
+R
2
) 1.2*10
3
-----------------(b)
By solving (a) and (b) we get
R
1
= 56K R
2
= 9.8K
Capacitor calculations:
To provide low reactances almost short circuit at the operating frequency
f=100HZ. X c
E
= 0.1R
E
, Xc
i
=0.1 Z
i
, Xc
o
=0.001 Z
0

7) X c
E
<< R
E,
X c
E
=R
E
/10 =1.2K/10=120
=> C
E
= 0.132F
8) X
Ci
=Zi/10 Where Zi=hie//R
E
= 8.18K
=> C
i
=1.96F
9) X
Co
= Z
O
/1000
Z
O
=R
L
//R
C
= 827
=> C
O
= 19.2F
Standard values
R
11
= R
12
= R
1
=56 K, R
21
= R
22
=R
2
= 9.8 K, R
E1
=R
E2
=R
E
=1.2 K,
R
C1
=R
C2
=R
C
=4.8 K, R
L
=10,C
i
=0.1F,C
C
= 0.01F,C
E
= 1F C
0
= 10F.
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Apply supply voltage, Vcc= 12V.
3. Make sure that the transistor is operating in active region by keeping Vce half
of Vcc.
4. Now feed an ac signal of 20mV at the input of the amplifier with different
frequencies ranging from 100Hz to 1MHz and measure the amplifier output
voltage, V
o
.
5. Now calculate the gain in db at various input signal frequencies.
6. Draw a graph with frequencies on X- axis and gain in db on Y- axis. From
graph calculate bandwidth.







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Tabular Form:
Simulation:
Input AC voltage, V
i
= 20mV (peak-peak)

S.No Frequency (Hz)
Output voltage Vo
(mv) (peak-peak)
Gain in decibels
A
V
=20 log (V
o
/ V
i
)
1
100 26 2.28
2
300 80 12.04
3
500 150 17.5
4
1K 340 24.6
5
3K 1500 37.5
6 5K 8600 52.66
7
10K 8600 52.66
8
50K 8600 52.66
9 60K 8600 52.66
10 80K 8600 52.66
11
90K 8600 52.66
12
100K 8600 52.66
13
500K 4000 46.02
14
1M 1000 33.98







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Practical:
Input AC voltage, V
i
= 20mV (peak-peak)

S.No Frequency (Hz)
Output voltage Vo
(mv) (peak-peak)
Gain in decibels
A
V
=20 log (V
o
/ V
i
)
1
50 22 0.82
2
100 25.5 02.11
3
200 58 09.24
4
500 152 17.61
5
1K 330 24.34
6 5K 8500 52.56
7
10K 8500 52.56
8
20K 8500 52.56
9 50K 8500 52.56
10 100K 8500 52.56
11
200K 8500 52.56
12
300K 8500 52.56
13
500K 8500 52.56
14
700K 4000 46.02
15
1M 900 33.06







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Observations:
Simulation Practical
Maximum gain (A
v
) 52.66dB 52.56dB
Lower cutoff frequency (f
L
) 4.6KHz 4.5KHz
Upper cutoff frequency (F
H
) 470kHz 580KHz
Band width (B.W) = (F
H
F
L
) 465KHz 575.5KHz
Gain bandwidth product = A
v
(B.W) 24.48MHz 30.24M Hz
Model graph:

Precautions:

1. Connections must be done very carefully.
2. Readings should be noted without any parallax error.
3. The applied voltage and current should not exceed the maximum
ratings of the given transistor.



Inferences: A maximum gain of 52.66dB and a B.W of 465 KHz is obtained from
simulation and a maximum gain of 40.00 dB and a B.W of 580 KHz is obtained from
practical circuit.

Result:
A Two stage RC coupled amplifier with given specifications is designed and is
simulated. Simulated and practical results are compared.









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Questions & Answers

1. Why RC coupled amplifiers widely used as voltage amplifiers?
a. Because of their excellent audio fidelity over a wide range of frequencies.
2. Why the voltage gain of RC coupled amplifier falls in low frequency range?
a. Due to the coupling capacitor.
3. Why the voltage gain of RC coupled amplifier falls at high frequency range?
a. Due to the shunting effect of inter-winding capacitances, inter-electrode
capacitances.




























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4. WIENBRIDGE OSCILLATOR

Aim:
1. Design a WIEN BRIDGE OSCILLATOR for given specifications.
2. Simulate the designed oscillator.

3. Develop the hard ware for designed oscillator.

4. Compare simulation results with practical results.

Apparatus:

S.No Name of The Component/Equipment Specifications Qty
1 Transistor (BC-107) I
CMAX
=100mA
P
D
=300mW
V
CEO
=45V
V
BEO
=50V

2
2 Capacitors(designed values) Voltage rating=
1.6v Electrolytic
type
5

3 Resistors (designed values) Power
rating=0.5W
Carbon type
10
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1

Theory: The circuit diagram of Wien bridge oscillator is given in figure .The
circuit consists of a two stage RC coupled amplifier which provides a phase shift of
360 or 0. A balanced bridged is used as the feed back network which has no need to
provide any additional phase shift. The feed back network consists of lead-lag
network(R1-C1 and R2-C2) and a voltage divider (R3-R4). The leadlag network
provides positive feed back to the input of first stage and the voltage divider provides
a negative feed back to the emitter of Q1.
If the bridge is balanced,
R
3
/R
4
=(R
1
-jXc
1
)/(R
2
)(-jX
2
)/(R
2
-jXc
2
)).
Where Xc1 and Xc2 are the reactances of the capacitors.
By simplifying and equating the real and imaginary parts on both sides,we get the
frequency of oscillation as,
f
o
= 1/ ( 2R
1
R
2
C
1
C
2
)
=1/(2RC), if R
1
=R
2
=R
3
and C
1
=C
2
=C.






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24

The ratio of R3 to R4 being greater than 2 will provide a sufficient gain for the circuit
to oscillate at the desired frequency. This oscillator is used in commercial audio
signal generator.

Circuit Diagram:



Design Equations:

Given data:
V
CC
=15v, V
CE
=8v, I
C
=2mA, =100, V
BE
=0.6v,


1) Applying Kirchoffs voltage law to the collector circuit in the diagram
V
CC
= V
CE
+ I
C
R
C

Rc = (Vcc -Vce)/Ic = 3.5 K
I
B
= I
C
/ = 20A
2) Applying Kirchoffs voltage law to the base circuit in the diagram
Vcc = I
B
R
B
+ V
BE
=> R
b
= 720K
Current through R
5
,R
6

I
1
= 10I
B

= 10(0.02mA)=0.2mA
But I
1
= Vcc/(R
5
+ R
6
)
R
5
+ R
6
= 15/0.2m = 75K
But V
6
= V
BE
+ V
E





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25
V
E
= Vcc

/ 10 = 1.5V
V
6
=0.6+1.5=2.1
I
1
(R
6
)=2.1
R
6
=10.5K
R
5
+ R
6
=75K
R
5
=75K-10.5K=64.5K
Ve = I
E
R
E
=> R
E
=750;
X
CO
=R
C
/10=(3.5k)/10=350.
f=1KHZ
C
O
=1/(2fR
C
/10)=1/(2*1K*350)=0.45F
C
F
=0.01 F.
PRACTICAL VALUES:
Time period=1.2 X 500=6 X10
-4
msec
f=1/T=1.66KHZ
%error = (|Theoritical-Practical|/ Theoritical) x100
=(|1.69K-1.66K|/1.66K) X 100
=1.77%

Procedure:

1. Connections are made as per the circuit diagram.
2. Switch on power supply.
3. Connect the CRO at output of the circuit.
4. Adjust potentiometer for distortion free wave form.
5. Measure the output frequency and amplitude on CRO and compare the
theoretical and practical frequencies.
6. Repeat the procedure for different values of capacitor.

Tabular form:

Simulation:

S.No Amplitude(V) (Peak-Peak) Frequency(KHZ) % Error

1

9

1.6

0






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Practical:


S.No Amplitude(V) Peak-peak

Frequency(KHZ) % Error

1

10

1.5

6.25













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27

Model Graph:


Inferences: A signal of 1.6 kHZ and 0 % of error is obtained by simulation and a
signal of 1.5 kHZ and 6.25% of error is obtained by hardware. The reason for error is
due to the ageing of the components and also slight variations in values.

Result: A wein bridge oscillator with given specifications is designed and is
simulated. Simulation and practical results are compared.

Question & Answers

1. What is oscillator?
a. A circuit which generates ac output signal at any frequency without requiring
input signal.
2. What are BHARKHAUSEN conditions of oscillators?
a. 1.the loop gain of a circuit must be >= 1.
2. Total phase shift around a circuit must be 0 or 360 degrees.
3. Which type of feedback is used in wein bridge oscillator?
a. Both positive and negative feedback.
4. What is the application of wein bridge oscillator?
a. It is used as standard oscillator for generating frequency with the range of 10HZ to
100KHZ.Hence it is used almost in all commercial audio signal generator.






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5. RC PHASE SHIFT OSCILLATOR
Aim:
1. Design RC phase shift oscillator for given specifications.
2. Simulate the designed circuit.
3. Develop the hard ware for designed oscillator.
4. Compare the Simulation and practical values.
Apparatus:

S.No Name of The
Component/equipment
Specifications Qty
1 Transistor (BC 107) Icmax=100mA
P
D
=300mW
Vceo=45V
Vbeo=50V

1
2 Capacitors(designed values) Electrolytic type
Voltage rating= 1.6v
3

3 Resistors (designed values) Power rating=0.5W
Carbon type
4
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1


Theory: RC phase shift oscillators are more suitable oscillators as they occupy
less space. RC phase shift oscillator can be achieved by two means,
1. RC phase shift oscillator using cascade of high pass filters.
2. RC phase shift oscillator using cascade of low pass filters.

If values of R and C are chosen that every RC section provides a phase shift of 60
o
.
thus theoretically RC ladder network produces a total phase shift of 180
0
between
input and output voltages for the given frequency. Therefore at a specified frequency
f
r
the total phase shift from base of transistor around and back to the base will be
360
0
or 0
0
, there by Barkausen condition of oscillation, the frequency of oscillations is
given by
f=1/2RC (6+4K)
1/2
Where C
1
=C
2
=C
3
=C,
K=R
C
/R,
R
1
=R
2
=R
3
=R






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29




Circuit Diagram:-


Design Equations:

Given data: V
CC
=12v, I
C
=1mA, = 100, V
BE
=0.3v, V
CE
=8v,f = 1KHZ

1) The d.c current gain is defined as the ratio of collector current (I
C
) to the base
current (I
B
)
dc
= I
C
/ I
B

I
B
= I
C
/ = 1* 10
-3
/100 = 10A
2) The voltage across the base resistor is
V
CC
= V
B
+ V
BE
= I
B
R
B
+ V
BE

12 = 10* 10
-6
R
B
+ 0.3
R
B
= 12 0.3/10 = 1.17M
3) By choosing drop across R
E
as 0.1 V
CC

V
RE
= V
CC
/ 10 = 1.2V = I
C
R
E

R
E
=1.2/1mA = 1.2K
4) Applying Kirchoffs voltage law to the collector circuit in the diagram
V
CC
I
CQ
(R
C
+R
E
) +V
CE(Q)
R
C
+R
E
= 12-8/1mA =4K
R
C
=4K -1.2K =2.8K








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Capacitor calculations:
To provide low reactances almost short circuit at the operating frequency
f=1KHZ. X
CE
= 0.1R
E
, Xc
O
=0.1 R
O


5) X
CO
= R
O
/10 = R
C
/10 =2.8K/10=0.28K

C
O
=1/(2f R
O
) = 56.8 F

6) Xc
E
= R
E
/ 10 = 1.2K/10=0.12K
C
E
=1/(2f R
E
) = 1.32 F

Theoretical Values:

Assume f=1k HZ, C=0.01 F
f=1/(2RC)((6+4k))
1/2
where k=R
C
/R.
R=5.626K


Procedure:

1. Connections are made as per circuit diagram.
2. Switch on the power supply.
3. Connect the CRO at the output of the circuit and apply supply voltage of
V
CC
=12v.
4. Compare the simulation frequency and practical frequency values.
5. Plot the graph for amplitude versus frequency.

Observations:

Time period, T of the AC signal available at the output = 1ms
The frequency of Oscillations, f = 1 / T = 1 KHz
Tabular Form:
Simulation:


S.NO

Amplitude(v) p-p

Frequency (KHZ)

% Error

1

10

1


0












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Practical:

S.NO
Amplitude(v) p-p
Frequency (KHZ) % Error

1



9.5

1


0













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32




Model Graph:



Precautions:
1. Connections must be done very carefully.
2. Readings should be noted without any parallax error.
3. The applied Voltage and current should not exceed the maximum ratings of the
given transistor.
Inferences: A signal of 1.00 kHz is obtained by simulation and a signal of 1.00
kHz is obtained practically.

Result: An RC phage shift oscillator with given specifications is designed and is
simulated. Simulation and practical results are compared.

Questions & Answers

1. Which type of feedback is used in RC phase shift oscillator?
a. Positive feedback.
2. How many RC networks are used in RC phase shift oscillator?
a. 3 (three).
3. What must be the gain of the internal amplifier in the general RC phase shift
oscillator?





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a. The gain of the internal amplifier in the RC phase shift oscillator must be >=29
In order to produce un damped oscillations.
4. What is the effect of V
CC
, R & C values on output?
a. When V
CC
is applied current through R
c
in creases because of biasing. This
charging the capacitor C and increases the voltage across R.The voltage across
each RC is exactly 60
0
out of phase. Thus total phase shift of 180
0
is obtained
across last combination which is fed to the input of an amplifier produces another
phase shift of 180
0
.Thus total 360
0
or 0
0
phase shift is obtained.
5. How to vary the frequency in worse and fine ways?
a. The frequency of oscillations may be varied by charging the values of C of all the
three sections simultaneously.




































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34


6. CLASS-A POWER AMPLIFIER

Aim:
1. Design a class-A inductor coupled power amplifier to deliver 4W power to 10
Ohms load resistor.
2. Simulate the designed amplifier.
3. Develop the hard ware for designed amplifier.
4 Compare simulation results with practical results.

Apparatus:


S.No Name of the Component
/equipment
Specifications Qty

1 Power transistor (BD139)
V
CE
=60V, V
BE
= 100V
I
C
= 100mA h
fe
= 40 to160
1
2 Resistor (designed values) Power rating=0.5w
Carbon type
4
3 Capacitors(designed values) Electrolytic type Voltage
rating= 1.6v
3
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1
7 Inductor(designed values) Operating
temperature=ambient
1

Theory: The power amplifier is said to be class A amplifier if the Q point is
selected in such a way that output signal is obtained for a full input cycle. For class A
power amplifier position of Q point is at the centre of mid point of load line. For all
values of input signals the transistor remains in the active region and never enters
into the cut off or saturation region. When an ac signal is applied, the collector
current flows for 360
0
of the input cycle. In other words, the angle of collector current
flow is 360
0
i.e... One full cycle. Here signal is faithfully reproduced at the output
without any distortion. This is an important feature of class A operation. The
efficiency of class A operation is very low with resistive load and is 25%. This can be
increased to 50% by using inductive load. In the present experiment inductive load is
used.








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Circuit Diagram:



Design Equations:

Given data: R
L
= 10, P
L max
= 4W, f=1KHZ
1) Selection of L:
L>>R
L

L>>R
L
/2f
L
= 10/6.28(1K) = 1.59mH


2) Selection of V
CC
:
The maximum power which can be delivered is obtained for V
m
= V
CC

(if v
min
=0)

P
L max
V
CC
/2R
L


V
CC
P
Lmax
X 2R
L


V
CC
= 8.94V

3) Selection of R
E
:
I
CQ
= (P
C max
/R
L
)
1/2
=(12.5/10)
1/2
=1.118A

I
CQ
=V
CC
/(R
ac
+R
dc
) where R
ac
= R
L
, R
dc
= R
E







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36
I
CQ
=V
CC
/(R
L
+R
E
) , R
E
= (V
CC
/I
CQ
)

- R
L
, R
E
= 2

4) Selection of biasing resisters R
1
& R
2
:
V
BB
= V
BE
+V
E


V
E
= I
CQ
*R
E
= 2.24V
V
BB
= 0.6+2.24 =2.84V

The voltage across R
2
is
V
BB
=V
CC
R
2
/(R
1
+R
2
)

2.84 = 8.94R
2
/(R
1
+R
2
) => R
2
=0.465 R
1

R
B
= R
1
R
2
/(R
1
+R
2
)

R
1
=50.4, R
2
=23.4

Capacitor calculations:
To provide low reactances almost short circuit at the operating frequency
f=1KHZ. X
CE
= 0.01R
E
, Xc
i
=0.1 R
B
,Xc
0
=0.1 R
L


5) Selection of C
E
:

Xc
E
= R
E
/100 C
E
= 7.95mF

6) Selection of C
i
& C
0
:

Xc
i
R
B
/10=1.6
C
i
= 99F
7) Xc
0
R
L
/10 =1 C
0
= 0.159mF

Procedure:

1. Connect the circuit as shown figure and supply the required DC voltage
2. Feed an AC signal at the input and keep the frequency at1 KHZ and
amplitude 5V.Connect a power o/p meter at the o/p.
3. Change the o/p impedance in steps for each value of impedance and note
down the o/p power.

4. Plot a graph between o/p power and load impedance. From this graph find
the impedance for which the o/p power is maximum. This is the value of
optimum load.
5. Select load impedance which is equal to 0V or near about the optimum
load. See the wave form of the o/p of the C.R.O.
6. Calculate the power sensitivity at a maximum power o/p using the relation.
Power sensitivity = output power / (rms value of the signal)
2







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37

Tabular Form:

Simulation:
Input Power=V
CC
x I
CQ=
5.688W


S.No

R
L
(Ohm)

D.C.Input
Power P
in
(W)

Output Power
P
out
(W)

Efficiency =

p
out
/p
in
*100(%)

1 1 5.688 1.382 24.2
2 2 5.688 2.621 46.0
3 3 5.688 2.765 48.61
4 4 5.688 2.667 46.8
5 5 5.688 2.532 44.51
6 6 5.688 2.404 42.4
7 7 5.688 2.211 38.88
8 8 5.688 2.095 38.2
9 9 5.688 2.003 36.8
10 10 5.688 1.711 35.2
11 15 5.688 1.453 30.0
12 20 5.688 1.268 25.5
13 25 5.688 1.235 22.2












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38

Practical:

S.No R
L
(Ohm) D.C Input
Power P
in
(W)
A.C output
Power P
out
(W)
=(Pac)/(Pdc)*100
1 4 270 2.5 1.11
2 6 270 3 1.85
3 8 270 5 2.22
4 10 270 6 11.5
5 50 270 31 18.5
6 100 270 50 21.5
7 150 270 58 18.5
8 300 270 50 16
9 600 270 31 11.5




Model Graph:













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39
Precautions:

1. Connections should be done care fully.
2. Take the readings with out any parallax error.

Inferences: A class A power amplifier with a maximum efficiency of 48.61 is
obtained in simulation. And a maximum efficiency of 21.5 is obtained from practical
circuit.

Result: Simulation and practical results of class A power amplifier are
observed.

Questions & Answers

1. What is power amplifier?
a. An amplifier which raises the power level of input signal or the device
which converts dc power into ac power and whose action is controlled by
input signal.

2. Why power amplifiers are called as large signal amplifiers?
a. Power amplifiers are required to handle large voltage signals so as to deliver large
power at the output.

3. What is the maximum collector efficiency of transformer load class A
power amplifier?

a. 50 %.

4. What is the maximum collector efficiency of resistive load class A
power amplifier?

a. 25 %















ELECTRONICS & COMMUNICATION ENGINEERING
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40
7. CLASS B COMPLEMENTARY SYMMETRY
POWER AMPLIFIER

Aim:
1. Design a complementary symmetry power amplifier to deliver maximum
power to 10 Ohm load resistor.
2. Simulate the design circuit.
3. Develop the hard ware for design circuit.
4 Compare simulation results with practical results.

Apparatus:

Sl.No Name of the Component
/equipment
Specifications Qty

1 Power transistor (BD139) V
CE
=60V V
BE
= 100V
IC = 100mA hfe = 40 -160
1
2 Resistor (designed values) Power rating=0.5W
Carbon type
4
3 Capacitors(designed values) Electrolytic type Voltage
rating= 1.6v
3
4 Inductor(designed values) Operating temp =ambient

1
5 Function Generator 0 -1MHZ 1
6 Cathode Ray Oscilloscope 20MHZ 1
7 Regulated Power Supply 0-30V,1Amp 1


Theory: In complementary symmetry class B power amplifier one is p-n-p and
other transistor is n-p-n. In the positive half cycle of input signal the transistor Q
1
gets
driven into active region and starts conducting. The same signal gets applied to the
base of the Q
2
. it ,remains in off condition, during the positive half cycle. During the
negative half cycle of the signal the transistor Q
2
p-n-p gets biased into conduction.
While Q
1
gets driven into cut off region. Hence only Q
2
conducts during negative half
cycle of the input, producing negative half cycle across the load.











ELECTRONICS & COMMUNICATION ENGINEERING
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Circuit Diagram:

Design Equations:

Given data: P
L (MAX)
=5 W, R
L
= 10, f = 1KHZ

1. Selection of V
CC
:-
P
L (MAX)
= V
CC
/ 2R
L


V
CC
= P
L (MAX)
2R
L

= 100V
V
CC
= 10V

Selection R and R
B
:-

V
BB
= V
BE
= 0.6V , assume R = 150
V
BB
=V
CC
.R / (R+R
B
)
0.6 = 10*150/ (150+R
B
)
R
B
= 2.35K

Capacitor calculations:-

To provide low reactances almost short circuit at the operating frequency
f=1KHZ.
X
CC1
= XC
C2
= (R \\ R
B
) / 10

= (150)(2350)/(10)(2550) = 14.1
C
C1
= C
C2
= 1/ 2 f X
CC1
= 11.28F






ELECTRONICS & COMMUNICATION ENGINEERING
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42


Procedure:

1. Connect the circuit diagram and supply the required DC supply.
2. Apply the AC signal at the input and keep the frequency at 1 KHz and
connect the power o/p meter at the output. Change the Load resistance in
steps for each value of impedance and note down the output power.
3. Plot the graph between o/p power and load impedance. From this graph
find the impedance for which the output power is maximum. This is the
value of optimum load.
4. Select load impedance which is equal to 0V or near about the optimum
load. See the wave form of the o/p of the C.R.O.
5. Calculate the power sensitivity at a maximum power o/p using the relation.
Tabular Form:

Simulation:

Input power = 2 V
CC
2
/ (R
L
) = 6.36W


S.No Output Impedance() Input
power
(p
i
) (W)
Output
Power(p
o
)
(W)
N=(Po)/( Pi) x100
1 3 6.36 2.114 33.23
2 5 6.36 3.112 48.93
3 7 6.36 4.074 64.05
4 9 6.36 4.959 77.97
5 10 6.36 3.471 54.5
6 12 6.36 3.373 53.03
7 14 6.36 3.319 52.18


















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43



Practical:

Input power = 360mW

S.No Output
Impedance()
Input power
(p
i
) (mW)
Output
Power(p
o
)
(mW)
N=(Po)/( Pi) x100
1 4 360 75 20.8
2 6 360 90 25
3 8 360 105 29.2
4 10 360 108 30
5 50 360 82.5 22.9
6 100 360 45 12.5
7 150 360 39 10.8
8 300 360 18 5
9 600 360 9 2.5




Model Graph:














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Precautions:

1. Connections should be made care fully.
2. Take the readings with out parallax error.
3. Avoid loose connections.
4. Simulation switch must be off while changing the values.

Inferences: A class B complementary symmetry power amplifier with a maximum
efficiency of 77.97 is obtained in simulation. And a maximum efficiency of 29.2 is
obtained from hardware.

Result: Class B complementary symmetry amplifier is designed for given
specifications and its performance is observed.


Questions & Answers

1. What is the use of Heat sinks in power amplifiers?
a. Heat sinks are used in a transistor working as power amplifier so as to increase
the collector dissipation rating of transistor.
2. What is cross over distortion?
a. There is a period between the crossing of the half cycles of the input signal, for
which none of the transistors is active and the output is zero. Hence the nature of
the output signal gets distorted and no longer remains same as that of input.
Such a distorted output wave form due to cut-in voltage that is called a cross-over
distortion.

3. What is the maximum efficiency of Class B complementary symmetry
Power amplifier?
a. 78.5%.

4. What are the advantages of Class B complementary symmetry amplifier?
a. 1. It is a transformer less amplifier.
2. Maximum efficiency.








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8. SINGLE TUNED VOLTAGE AMPLIFIER

Aim: 1.Design a class c tuned voltage amplifier for the input signal frequency of
5 kHz
2. Simulate the design circuit.
3. Develop the hard ware for design circuit.
4 Compare simulation results with practical results

Apparatus:

Sl.No Name of the
Component / equipment
Specifications Qty
1 Power transistor Ic
max
=100mA
p
Dmax
=300mW
V
ceo
(max)=45v
V
cbo
(max)=50v


1
2 capacitor(designed values) Max temp : 65c
Electrolytic type
capacitor

3
3 Resistors(designed values)

Power rating=0.5W
Carbon type

2
4 Inductors(designed values) Internal resistance=
Operating point :
Ambient
1
5 Function Generator 0 -1MHZ 1
6 Cathode Ray Oscilloscope 20MHZ 1
7 Regulated Power Supply 0-30V,1Amp 1

Theory:
In class C amplifier, the Q point and input signal are selected such that the output
signal is obtained for less than a half cycle, for a full wave input. Due to such a
selection of Q point, transistor remains active , for less than a half cycle, For
remaining cycle of input cycle, the transistor remains cut off and no signal is
produced at the output. When a class C amplifier is connected to a parallel tuned
circuit, there fore the output voltage is maximum at the resonant frequency. The
resonant frequency for parallel tuned circuit is given by f
r
= 1/2 LC .
Tuned Amplifiers are used at radio frequencies. The amplifier consists of LC
Circuit for tuning certain frequency. The resonant frequency of lc circuit is equal to
input frequency.








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Circuit diagram:







Design equations:

Given data:
f
r
=5KHz , C=0.01F,R
B
=1KHz,R
L
=1M
1. selection of L:
f
r
= 1/2 LC
L =101.3 mH
Capacitor calculations:
To provide low reactances almost short circuit at the operating frequency
f=5KHZ.
X
C1
= 0.1R
B
, X
C2
=0.1 R
L
,

2. selection of capacitor c
1
:






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X
C1
=R
B
/ 10

C
1
=1/2 (5k)(100) = 0.3F
3. selection of capacitor c
2
:
X
c2
= R
L
/10
C
2
=1/2 (5K)(100000) =0.3pF.

Procedure:

1. Connect the circuit as per the circuit diagram.
2. Apply input signal of some fixed amplitude.
3. Set input signal frequency at some frequency (say 100 KHz).
4. Increase the frequency in steps of KHz and observe the output.
5. Measure the output voltage for each value of input frequency.
6. Find the frequency at which maximum output is obtained.
7. Tabulate the readings and find voltage gain.
8. Draw the graph between frequencies vs. gain.
9. Locate two points on either side of the amplitude peak value on the graph at
which the gain is 70.7% of maximum gain.

Tabular Form:


Simulation:
Input voltage = 2V (peak-peak)

S.No Frequency
(KHZ)
Output Voltage (V
o
)
(peak-peak) volts

Gain in dB A
V=
20 log (V
o
/ V
i
)
1 1 18 19.08
2 2 20 20.00
3 3 21 20.42
4 4 23 21.21
5 5 28 22.92
6 5.3 30 23.52
7 5.5 29 23.22
8 6 24 21.58
9 7 11 14.80
10 8 6 9.54
11 10 4 6.03







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Practical:

Input voltage = 2V (peak-peak)


S. No Frequency
(KHZ)
Output Voltage (V
o
)
(volts p-p)

Gain in dB =
20log (Vo/Vi)
1 1 14 16.90
2 2 18 19.08
3 3 20 20
4 4 23 21.21
5 5 25 21.93
6 6 16 18.06
7 7 9 13.06
8 8 7 10.88
9 9 6 9.54
10 10 5 7.95










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Model graph:



























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Precautions:

1. Connections should be made care fully.
2. Take the readings with out parallax error

Inferences: A single tuned voltage amplifier with a maximum gain 23.52 at 5.3
kHz is obtained in simulation. And a maximum gain of 21.93 at 5 kHz is obtained
practically.

Result:

A single tuned voltage amplifier is designed with given specifications.


Questions & Answers

1. What are the applications of Tuned amplifiers?

a. 1.Used in Radio receivers to amplify a particular band of frequencies for which
the radio receiver is tuned.
2. used in active filters such as low pass ,high pass and bandpass to
allow amplification of signal only in desired narrow-band.

2. What are the requirements of tuned amplifiers?
a. 1. The amplifier must provide selectivity of resonant frequency over a
narrow band.
2. The signal should be amplified equally well at all frequencies in the
selected narrow band.

3. What is Q-factor?
a. It is the ratio of reactance to the resistance. higher the Q of an inductor
fewer the losses in the inductor. It can also be defined as measure of
efficiency with which inductor can store the energy.
Q = W L
S
/ R
S











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9. SERIES VOLTAGE REGULATOR
Aim:

1. Design series voltage regulator to operate on supply of 15v.
2. Simulate the design of regulator.
3. Develop the hardware for design of voltage regulator.
4. Compare the practical results with theoretical results.



Apparatus:

S.No Name of the
component/equipment
Specifications Qty
1

Zener diode (Bz6.5) V
z
=6.5v 1
2 Transistors (BC 107)

I
c max
=100ma,
V
CEO
=45v,
P
d(min)
=300mw
1
3 Resistors(designed values) Power dissipation=0.5w
Carbon type Tolerance 5%
1

4 Regulated power supply 0-30 V,1Amp 1


Theory: A regulator is an electronic circuit which maintains a constant output
irrespective of change in input voltage, load resistance and change in temperature.
Series voltage regulator is one type of regulator. If in a voltage regulator circuit , the
control element is connected in series with the load ,then the circuit is called series
voltage regulator circuit. The unregulated d.c voltage is the input to the circuit. The
control element controls the input voltage, that gets to the output. The sampling
circuit provides the necessary feed back signal. The comparator circuit compares the
feed back with the reference voltage to generate appropriate control signal. In a
transistorized series feedback type regulator the output voltage is given by
V
o
= (1+R
1
/R
2
) (V
BE2
+V
z
)











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Circuit Diagram:

Design Equations:

Given data:
V
L
= 9V, I
L
= 40mA, I
Z
= 1mA, V
Z
= 6.5V V
i
=15V, I
B
=1mA, h
fe
=100

1. Assume the current flowing through the resistor R
1
& R
3
is 1/10 of the I
L

I
1
=I
3
=I
L
/10 =40mA / 10 = 4mA

2. I
E1
=I
1
+I
3
+I
L
= 48mA


3. R
L
=V
L
/I
L
= 9/(40 X 10
-3
) = 225

4. V
O
=V
L
=R
3
I
3
+V
Z

R
3
=V
L
-V
Z
/I
3
= 375

5. R
1
I
1
+V
BE2
+V
Z
=V
O


R
1
=V
O
-(V
BE2
+V
Z
)/I
1
= 220

4 R
2
I
2
= V
BE2
+ V
Z

R
2
= 2.04K

h
fe
= 100, I
C2
= 3mA

5 I
2
= I
1
-I
B2
( Since h
fe
= I
C2
/I
B2
)
I
2
= 3.97mA
6 I
4
= I
B1
+ I
C2

I
B1
= I
C1
/ hfe1 (I
C1
= I
E1
)
I
4
= 3.48mA
7 Vi = I
4
R
4
+ V
BE1
+ V
O

R
4
= 2.98K







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Procedure:

1. Connect the Circuit diagram as shown in the fig:
2. Apply the input voltage of 15V
3. Keep the input Voltage constant. Vary the load resistance and measure the
output Voltage and output current
4. Tabulate the readings
5. Plot the graph between Load current versus Load Resistance and Output
Voltage versus Load resistance.


Tabular forms:

Simulation:

S.No Load resistance
R
L
(Ohms)
Output Voltage (v) Output Current
I
L
(mA)
1 225 9.03 40
2 300 9.03 28
3 350 9.03 24
4 400 9.03 22
5 500 9.03 18
6 600 9.03 17
7 700 9.03 15
8 800 9.03 12
9 1K 9.03 10
10 1.2K 9.03 8
11 5K 9.03 1.5
















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Practical

S.No Load resistance
(R
L
in Ohms)
o/p voltage
(v)
o/p current
I
L
(mA)
1 225 9.03 40
2 300 9.03 30.25
3 350 9.03 25.9
4 400 9.03 22.69
5 500 9.03 18.15
6 600 9.03 15
7 700 9.03 12
8 800 9.03 11
9 1K 9.03 9
10 1.2K 9.03 7.5
11 1.4K 9.03 6.5




















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Model graph:









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Precautions:

1. Connections should me made care fully.
2. Take the readings with out parallax error.

Inferences: A voltage series regulator with an output voltage of 9.03V and a
maximum current of 40 mA is obtained.

Result: A series voltage regulator of 9V output is designed and verified.

Questions & Answers

1. What is voltage regulator?
a. A circuit which supplies a constant voltage regardless of variations in
load current and ac mains voltage.
2. Why series regulators are called as linear voltage regulators.
a. The pass transistor used in series regulators operate in linear
portion of its output characteristics.
3. What are the applications of series voltage regulator?
a. It is preferred for fixed as well as variable voltage applications.
4. What are the characteristics of series voltage regulator?
a. 1. Regulation is good
2. Design is complex.
3. The control element is high current, low voltage rating component
5. How the regulation is obtained in series regulator.
a. Any variations in output voltage is compensated by changing the voltage
across the control element as per the control signal.
6.What is the effect of output short on circuit operation?
a. If output terminals are short circuited then laod current becomes too high and
power supply unit may damage.To avoid this current limiting circuits are used in
regulators.
7.What is the range of input voltage for which output is constant?
a.The input voltage V
in
should be such that the zenor diode must operate in the break
down region and it can acts as a battery v. Maximum input voltage depends on
specifications of transistors and zener diode.






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8. Define line and load regulations?
a. Line regulation is defined as the change in the regulated output voltage due to the
change in the unregulated input voltage over a specified range.Load regulation is
defined as the change of output voltage over a specified load current.






































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10. SHUNT VOLTAGE REGULATOR



Aim:

1. Design a Voltage Shunt regulator for a supply of 15V to provide an o/p of 7V with
load current 40 mA.
2. Simulate the designed regulator.
3. Develop the hardware for designed Regulator.
4. Compare the practical values with theoretical values.

Apparatus:


S.No Name of the component
/Equipment
Specifications Qty

1 Resistors ( designed values) 0.5w , Tolerance 5% 1

2 Transistor (BC107) I
Cmax
=100mA, V
ce
= 5V
V
ceo
=45v,
Pd(min
)=300mw,
h
fe
=100

1
3 Zener diode(BZ6.5) 6.5V 1

4 Regulated Power Supply 0-30V,1Amp 1


Theory: The heart of any regulator circuit is a control element. If such a control
element is connected in shunt with the load, the regulator is called shunt voltage
regulator. The unregulated input voltage V
m
tries to provide the load current but path
of current is taken by the control element to maintain the constant voltage across the
load. The control element remains constant voltage by shunting the current. Hence
regulated power supply is called voltage shunt regulated circuit. The output voltage
and output current of emitter follower series regulator is

V
L
= V
z
+ V
BE
------1

I
L
= V
L
/R
L
------ 2.










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Circuit Diagram:




Design Equations:
Given data : V
L
= 7V, I
L
= 40mA, I
Z
= 1mA, V
Z
= 6.5V V
i
=15V, I
B
=1mA, h
fe
=100

1) R
L
= V
L
/ I
L
= 7/40mA = 175
2) By applying kirchoffs current law
I
S
= I
Z
+I
C
+I
L
; where I
C
= hfe I
B
=100*1mA=100mA
= 40 mA + 1 mA +100mA =141mA
3) Choose the zener breakdown voltage as less (0.5v-1v) than the
required output voltage.
V
L
= V
Z
+V
BE

V
Z
= V
L
- V
BE

= 7 0.6 = 6.4V
4) R
S
= (Vi V
L
) / I
S
= 15-7/141mA= 56.73

Procedure:

1) Connect the circuit as per the circuit diagram
2) Keep the input voltage constant vary the load resistance R
l
and
measure the o/p voltage and o/p current.
3) Plot the graph between V
O
and I
L
.
4) Plot the graph between I
L
and R
L
.





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Tabular forms:

Simulation:

S.No Load resistance R
L

(ohms)
O/P Voltage Vo
(volts)
Load Current I
L

(mA)
1 175 6.93 39.32
2 300 6.93 23.02
3 350 6.93 19.75
4 400 6.93 17.29
5 450 6.93 15.37
6 500 6.93 13.84
7 600 6.93 11.54
8 800 6.93 8.66
9 1000 6.93 6.93
10 1.2k 6.93 5.77
11 1.5k 6.93 3.2
12 3k 6.93 2.1










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Practical:

S.No Load resistance R
L

(ohms)
O/P Voltage Vo
(volts)
Load Current I
L

(mA)
1 175 6.9 40
2 300 6.9 25
3 350 6.9 22
4 400 6.9 20
5 450 6.9 18
6 500 6.9 16
7 600 6.9 13
8 800 6.9 10
9 1000 6.9 8
10 1.2k 6.9 7
11 1.5k 6.9 3.2
12 3k 6.9 2.1







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Model Graph:



Precautions:

Connections should me made care fully.
Take the readings with out parallax error.
Avoid loose connections

Inferences: A voltage series regulator with an output voltage of 6.9 V and a
maximum current of 42mAmps is obtained

Result: A shunt voltage regulator of 7V o/p is designed and verified.


Questions & Answers
1. What are the applications of shunt voltage regulator?
a. It is suitable for fixed voltage applications.
2. What are the characteristics of shunt voltage regulator?
A.1.Regulation is poor
2. Design is simple
3. The control element is low current, high voltage rating component
3. How is the regulation obtained in shunt regulator?
a. Any variations in output voltage is compensated by changing the current I
SH

through the control element as per the control signal.







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4. What is the effect of output short on circuit operation?
a. If output terminals are short circuited then laod current becomes too high and
power supply unit may damage. To avoid this current limiting circuits are used in
regulators.
5.What is the range of input voltage for which output is constant?
a.The input voltage V
in
should be such that the zenor diode must operate in the break
down region and it can acts as a battery v. Maximum input voltage depends on
specifications of transistors and zener diode.
6.Define line and load regulations?
a. Line regulation is defined as the change in the regulated output voltage due to the
change in the unregulated input voltage over a specified range. Load regulation is
defined as the change of output voltage over a specified load current.






























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11. CLASS-B POWER AMPLIFIER

Aim:

1. Design a class B power amplifier to deliver 5W to 10 Ohm load resistor
2. Simulate the designed regulator.
3. Develop the hardware for designed Regulator.
4. Compare the practical values with theoretical values.

Apparatus:

S.No Name of the component
/Equipment
Specifications Qty
1 Power transistors
BD 138, BD139
P
c
max =12.5W
I
c
max=1.5A
V
ce
max=80V,h
fe
=100
2
2 I/P Transformer Turns Ratio 1:1 1
3 O/P Transformer Turns Ratio 4:1 1
4 Resistor (designed values) Power rating=0.5W
Carbon type
4
5 Function Generator 0 -1MHZ 1
6 Cathode Ray Oscilloscope 20MHZ 1
7 Regulated Power Supply 0-30V,1Amp 1

Theory: The two transistors are biased to work in class-B operation. This
increases the power efficiency of the circuit. When the signal is applied, the
transformer Q
1
works as a phase splitter. It produces two signals (for the two
transistors) which are equal in magnitude but opposite in phase. During positive half-
cycle of the input signal, the base of the transistor Q
1
is driven positive..so,it will be in
the conducting state. The base of the transistor Q2 is driven negative. It remains cut-
off. Current i
c1
flows, but i
c2
is zero. During the negative half cycle of the input signal,
the opposite happens. Q2 conducts, but Q1 does not.












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Circuit diagram:

Design Equations:
Given data: P
L
(max) = 5W, P
C

(max)
= 12.5 W, I
C

(max)
= 1.5A, V
CC

(max)
= 80V,
S = 8

1. Selection of V
cc:


P
L
(max) =V
CC
X I
C

(MAX)
/ 2
V
cc
= 2 X 5/1.5 = 6.66V

2. Selection of R
L


I
C

(max)
=V
CC
/ N X R
L

R
L
=6.66/4 X 1.5 = 1.11

3. Selection of R
E
:
R
E
<< R
L


R
E
=R
L
/10 = 44.44

4. Selection of R
1
& R
2
:

V
E
=

I
CQ
X R
E


V
E
=I
CQ
X R
E


= 0.0697v

I
CQ
=P
C

(max)
/ V
CE


= 0.15A


S=R
B
// R
E
=R
1
// R
2
// R
E






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R
2
=94.69R
1


V
E
= V
cc
X R
1
/ (R
1
+R
2
)

R
1
= 3.61, R
2
= 341.95

Procedure:
1. Connect the circuit as per the circuit diagram

2. Connect the required supply from the regulated R.P.S
3. Feed the AC signal at the I/p and keep the frequency at 1 KHz . connect the
power o/p meter at the o/p. Change the o/p impedance in steps for each
value of impedance and note down the o/p power.
4. Plot a graph between o/p power and load impedance. From this graph find
the impedance for which the output power is maximum. This is the value of
optimum load.
5. Select load impedance which is equal to optimum load. See the wave form of
the output on C.R.O.
6. Calculate the conversion efficiency..

Tabular form

Simulation:


S.NO Load resistance
R
L
(Ohms)
P
ac
(W) P
dc
(W)
% = ((Pac)
/ (Pdc))*100
1 5 265.52mW 2.54 10.4
2 10 530.39mW 2.53 2.09
3 15 795.60mW 2.53 31.3
4 20 1.06 2.57 41.2
5 25 1.325 2.568 51.59
6 30 1.59 2.563 62
7 35 1.855 2.535 73.16
8 37 1.955 2.555 76.6












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Practical:

S.NO Load resistance
R
L
(Ohms)
P
ac
(W) P
dc
(W)
% = ((Pac)
/ (Pdc))*100
1 3 1 0.275 0.36
2 5 1.5 0.279 0.54
3 8 2.5 0.279 0.90
4 16 6 0.279 1.96
5 50 15 0.279 5.40
6 75 30 0.266 9.375
7 600 100 0.266 44.16
8 1k 90 0.199 45.04
9 2K 70 0.166 42.04
10 5K 40 0.113 35.29















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Model Graph:










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Precautions:

1. Connections should be made care fully.
2. Take the readings with out parallax error.

Inferences: A Class B power Amplifier with a maximum efficiency of 76.6 % at 37
ohms by using simulation. and a maximum efficiency of 45.04 % at 1K ohms by using
Hardware.

Result: The class B power amplifier is designed .Both the simulation and hardware
results are verified and compared.

Questions & Answers
1. What are the advantages of class B power amplifier?

a. 1. Harmonic distortion is low.
2. Efficiency is much higher than class A operation.
3. Impedance matching is possible due to transformer.
2. What is the period of conduction in class B power amplifier?

a. 180
0
3. How is the cross over distortion eliminated?

a. To eliminate the cross over distortion, the two transistors of a push-pull are slightly
Forward biased so that the circuit works in class-AB.




















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References:

1. Electronic Devices and circuit theory Robert L. Boylestad and Louis
Nashelsky,Pearson/Printice hall
2. Microelectronic circuits- serda A.S. and K.C. Smith,Oxford University
Press
3. Microelectronic circuits analysis analysis and design M.H.
Rashid,PWS Publications
4. principles of Electronics circuits S.G .Burns and P.R Bond

websites:

1. www.google.com
2. www.discovercircuits.com
3. www.datasheetcatlog.com
4. www.dmoz.com