All GATEs Using VHDL

INDEX
S.NO
NAME OF THE EXPERIMENT
PAGE NO
BASIC LOGIC GATES

OR
AND
NAND
EXOR
NOR
NOT
BASIC LOGIC GATES

AIM: To write a verilog code explaining the function of all basic gates.
`timescale 1 ns / 1 ps
module allgates ( p ,q ,a ,r ,b ,s ,m ,n ,o );
input a ;
wire a ;
input b ;
wire b ;
output p ;
wire p ;
output q ;
wire q ;
output r ;
wire r ;
output s ;
wire s ;
output m ;
wire m ;
output n ;
wire n ;
output o ;
wire o ;
or
g1(m,a,b);
and
g2(n,a,b);
nand g3(o,a,b);
nor
g4(p,a,b);
xor
g5(q,a,b);
xnor g6(r,a,b);
not
g7(s,a);
endmodule
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p
q
r
s
m
n
o
a
b
FLIP FLOPS
SYNCHRONOUS S-R FLIP FLOP
ASYNCHRONOUS S-R FLIP FLOP
SYNCHRONOUS J-K FLIP FLOP
ASYNCHRONOUS J-K FLIP FLOP
SYNCHRONOUS D FLIP FLOP
ASYNCHRONOUS D FLIP FLOP
SYNCHRONOUS T FLIP FLOP
ASYNCHRONOUS T FLIP FLOP
260
280
300 ns
SYNCHRONOUS S-R FLIP FLOP

AIM: To write a verilog code for synchronous S-R flip flop.
module sr_ff (q89,s,r,clk);
input s,r,clk;
output q89;
reg q89;
always @(posedge clk)
begin
case(s)
0:if(r)
q89=0;
else
q89=q89;
1:if(r)
q89=1'bx;
else
q89=1;
endcase
end
endmodule
module sr_ff_tb;
reg s,r,clk;
wire q89;
sr_ff s1(q89,s,r,clk);
initial
$monitor($time,"q89=%b,s=%b,r=%b",q89,s,r);
initial
begin
clk=1;
forever #5 clk=~clk;
end
initial
begin
s=0;r=0;
#15 s=0;r=1;
#15 s=1;r=0;
#15 s=1;r=1;
end
endmodule
10
s
r
clk
q89
output:
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20
30
45
50
q89=x,s=0,r=0
q89=x,s=0,r=1
q89=0,s=0,r=1
q89=1,s=1,r=0
q89=1,s=1,r=1
q89=x,s=1,r=1
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130
140
ns
ASYNCHRONOUS S-R FLIP FLOP

AIM: To write a verilog code for asynchronous S-R flip flop.
module jk_ff (j,k,q89,clk,res);
input j,k,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else
begin
case(j)
0:if(k)
q89=0;
else
q89=q89;
1:if(k)
q89=~q89;
else
q89=1;
endcase
end
end
endmodule
module jk_tb;
reg j,k,clk,res;
wire q89;
jk_ff j1(j,k,q89,clk,res);
initial
$monitor($time,"j=%b,k=%b,q89=%b",j,k,q89);
initial
begin
clk=1;
end
initial
begin
j=0;k=0;res=0;
#15j=0;k=1;
#15 j=1;k=0;
#15 j=1;k=1;
#15 res=1;
end
endmodule
10
j
k
clk
res
q89
output:
0
15
20
30
45
50
j=0,k=0,q89=x
j=0,k=1,q89=x
j=0,k=1,q89=0
j=1,k=0,q89=1
j=1,k=1,q89=1
j=1,k=1,q89=0
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120
130
140
ns
SYNCHRONOUS J-K FLIP FLOP

AIM: To write a verilog code for synchronous J-K flip flop.
module jk_ff (j,k,q89,clk,res);
input j,k,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else
begin
case(j)
0:if(k)
q89=0;
else
q89=q89;
1:if(k)
q89=~q89;
else
q89=1;
endcase
end
end
endmodule
module jk_tb;
reg j,k,clk,res;
wire q89;
jk_ff j1(j,k,q89,clk,res);
initial
initial
begin
clk=1;
end
initial
begin
j=0;k=0;res=0;
#15
j=0;k=1;
#15 j=1;k=0;
#15 j=1;k=1;
#15 res=1;
end
endmodule
10
j
k
clk
res
q89
output:
0
15
20
30
45
50
j=0,k=0,q89=x
j=0,k=1,q89=x
j=0,k=1,q89=0
j=1,k=0,q89=1
j=1,k=1,q89=1
j=1,k=1,q89=0
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120
130
140
ns
ASYNCHRONOUS J-K FLIP FLOP

AIM: To write a verilog code for Asynchronous J-K flip flop.
module jkff_asyn (j,k,q89,clk,res);
input j,k,clk,res;
output q89;
reg q89;
always @(posedge clk or negedge res)
begin
if(res)
q89=0;
else
begin
case(j)
0:if(k)
q89=0;
else
q89=q89;
1:if(k)
q89=~q89;
else
q89=1;
endcase
end
end
endmodule
module jk_asyn_tb;
reg j,k,clk,res;
wire q89;
jkff_asyn j1(j,k,q89,clk,res);
initial
initial
begin
clk=1;
end
initial
begin
j=0;k=0;res=0;
#15
j=0;k=1;
#15 j=1;k=0;
#15 j=1;k=1;
#15 res=1;
end
endmodule
10
j
k
clk
res
q89
output:
0
15
20
30
45
50
j=0,k=0,q89=x
j=0,k=1,q89=x
j=0,k=1,q89=0
j=1,k=0,q89=1
j=1,k=1,q89=1
j=1,k=1,q89=0
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100
110
120
130
140
ns
SYNCHRONOUS D FLIP FLOP

AIM: To write a verilog code for synchronous D flip flop.
module d_ff(q89,d,clk,res);
input d,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else
q89=d;
end
endmodule
module d_ff_tb;
reg d,clk,res;
wire q89;
d_ff d1( q89,d,clk,res);
initial
$monitor($time,"q89=%b,d=%b",q89,d);
initial
begin
clk = 1'b0;
forever #5 clk =~clk;
end
initial
begin
d=0;res=0;
#15 res=1;
#15 res=0;
d=1;
#15 d=0;
end
endmodule
10
d
clk
res
q89
output:
0
5
30
35
45
q89=x,d=0
q89=0,d=0
q89=0,d=1
q89=1,d=1
q89=0,d=0
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110
120
130
140
ns
ASYNCHRONOUS D FLIP FLOP

AIM: To write a verilog code for Asynchronous D flip flop.
module dff_asyn(q89,d,clk,res);
input d,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else
q89=d;
end
endmodule
module d_ff_asyn_tb;
reg d,clk,res;
wire q89;
dff_asyn d1( q89,d,clk,res);
initial
$monitor($time,"q89=%b,d=%b",q89,d);
initial
begin
clk = 1'b0;
forever #5 clk =~clk;

end
initial
begin
d=0;res=0;
#15 res=1;
#15 res=0;
d=1;
#15 d=0;
end
endmodule
10
d
clk
res
q89
output:
0
30
45
q89=0,d=0
q89=1,d=1
q89=0,d=0
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140
ns
SYNCHRONOUS T FLIP FLOP

AIM: To write a verilog code for synchronous T flip flop.
module t_ff (t,q89,clk,res);
input t,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else if(t)
q89=~q89;
else
q89=q89;
end
endmodule
module t_ff_tb;
reg t,clk,res;
wire q89;
t_ff t1(t,q89,clk,res);
initial
$monitor($time,"t=%b,q89=%b,clk=%b,res=%b",t,q89,clk,res);
initial
begin
clk=1'b0;
end
initial
begin
t=1;res=0;
#15 res=1;
#15 res=0;
#15 t=1;
#15 t=0;
end
endmodule
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t
clk
res
q89
output:
0
5
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100
t=1,q89=x,clk=0,res=0
t=1,q89=0,clk=1,res=1
t=1,q89=0,clk=0,res=1
t=1,q89=0,clk=1,res=1
t=1,q89=0,clk=0,res=0
t=1,q89=1,clk=1,res=0
t=1,q89=1,clk=0,res=0
t=1,q89=0,clk=1,res=0
t=1,q89=0,clk=0,res=0
t=1,q89=1,clk=1,res=0
t=0,q89=1,clk=0,res=0
t=0,q89=1,clk=1,res=0
t=0,q89=1,clk=0,res=0
t=0,q89=1,clk=1,res=0
t=0,q89=1,clk=0,res=0
t=0,q89=1,clk=1,res=0
t=0,q89=1,clk=0,res=0
t=0,q89=1,clk=1,res=0
t=0,q89=1,clk=0,res=0
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140
ns
ASYNCHRONOUS T FLIP FLOP

AIM: To write a verilog code for asynchronous T flip flop.
module t_ff_asyn(t,q89,clk,res);
input t,clk,res;
output q89;
reg q89;
begin
if(res)
q89=0;
else if(t)
q89=~q89;
else
q89=q89;
end
endmodule
module t_ff_asyn_tb;
reg t,clk,res;
wire q89;
t_ff_asyn t1(t,q89,clk,res);
initial
$monitor($time,"t=%b,q89=%b ",t,q89);
initial
begin
clk=1'b0;
end
initial
begin
t=1;res=0;
#15 res=1;
#15 res=0;
#15 t=1;
#15 t=0;
end
endmodule
10
t
clk
res
q89
output:
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60
t=1,q89=x
t=1,q89=0
t=1,q89=1
t=1,q89=0
t=1,q89=1
t=1,q89=0
t=0,q89=0
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100
110
120
130
140
ns
REALISATION OF 4 VARIABLE
FUNCTIONS
REALISATION OF FOUR VARIABLE FUNCTION

AIM: To realize a four variable function f(a,b,c,d) for 0,1,2,5,8,9,10 using gate level
modelling
module real1 ( a ,b ,pos89 ,sop89 ,c ,d );
input a ;
wire a ;
input b ;
wire b ;
input c ;
wire c ;
input d ;
wire d ;
output pos89 ;
wire pos89 ;
output sop89 ;
wire sop89 ;
wire abar,bbar,cbar,dbar;
wire x,y,z,x1,y1,z1;
not g1(abar,a);
not g2(bbar,b);
not g3(cbar,c);
not g4(dbar,d);
and g5(x,a,cbar,d);
and g6(y,bbar,cbar);
and g7(z,c,bbar,dbar);
or g8(sop89,x,y,z);
or g9(x1,b,c);
or g10(y1,dbar,c,abar);
or g11(z1,b,d,cbar);
and g12(pos89,x1,y1,z1);
endmodule
REALISATION OF FOUR VARIABLE FUNCTION

AIM: To realize a four variable function f(a,b,c,d) for 0,1,2,5,8,9,10 using data level
modeling.
module real2 (x,y,z,w,sop89,pos89);
input x,y,z,w;
output sop89,pos89;
wire x,y,z,w,sop89,pos89;
assign sop89=(~z&~y)|(~w&~y)|(~z&w&~x);
assign pos89=(~z|~w)&(w|~y)&(~x|~y);
endmodule
module stimulus;
reg x,y,z,w;
wire sop89,pos89;
real2 r1(x,y,z,w,sop89,pos89);
initial
begin
$monitor($time,"x=%b,y=%b,z=%b,w=%b,sop89=%b,pos89=
%b",x,y,z,w,sop89,pos89);
end
initial
begin
x=1'b0;y=1'b1;z=1'b0;w=1'b1;
#10
x=1'b1;y=1'b0;z=1'b0;w=1'b0;
#10
x=1'b1;y=1'b1;z=1'b0;w=1'b0;
#10
x=1'b1;y=1'b1;z=1'b1;w=1'b1;
end
endmodule
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x
y
z
w
sop89
pos89
REGISTERS
4 BIT SHIFT REGISTER
n BIT SHIFT REGISTER
180
200
ns
FOUR BIT SHIFT REGISTER

AIM: To write a verilog code for a 4 bit shift register using behavior level modeling.
module shift_4 (ld,Din,R,Q89,clk);
input ld,clk,Din;
input [3:0]R;
output [3:0]Q89;
reg [3:0]Q89;
begin
if(ld)
Q89<=R;
else
begin
Q89[0]<=Din;
Q89[1]<=Q89[0];
Q89[2]<=Q89[1];
Q89[3]<=Q89[2];
end
end
endmodule
module shift_tb;
reg ld,clk,Din;
reg
[3:0]R;
wire [3:0]Q89;
shift_4 s1(ld,Din,R,Q89,clk);
initial
begin
clk=0;
end
initial
$monitor($time,"ld=%b,Din=%b,R=%b,Q89=%b,clk=
%b",ld,Din,R,Q89,clk);
initial
begin
R=4'b0101; Din=1'b1;
ld=1'b1;
#25 ld=1'b0;
#50 R=4'b1111;
#80 ld=1'b1;
end
endmodule
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ld
clk
Din
R
Q89
F
5
output:
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100
ld=1,Din=1,R=0101,Q89=xxxx,clk=0
ld=1,Din=1,R=0101,Q89=0101,clk=1
ld=1,Din=1,R=0101,Q89=0101,clk=0
ld=0,Din=1,R=0101,Q89=0101,clk=0
ld=0,Din=1,R=0101,Q89=1011,clk=1
ld=0,Din=1,R=0101,Q89=1011,clk=0
ld=0,Din=1,R=0101,Q89=0111,clk=1
ld=0,Din=1,R=0101,Q89=0111,clk=0
ld=0,Din=1,R=0101,Q89=1111,clk=1
ld=0,Din=1,R=1111,Q89=1111,clk=1
ld=0,Din=1,R=1111,Q89=1111,clk=0
ld=0,Din=1,R=1111,Q89=1111,clk=1
ld=0,Din=1,R=1111,Q89=1111,clk=0
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200
220
240
ns
n- BIT SHIFT REGISTER

AIM: To write a verilog code for a n bit shift register using behavior level modeling.
module shift_nbit (ld,Din,R,Q89,clk);
input ld,clk,Din;
parameter n=4;
input [n-1:0]R;
output [n-1:0]Q89;
reg [n-1:0]Q89;
integer i;
begin
if(ld)
Q89<=R;
else
begin
Q89[0]<=Din;
for(i=0;i<n-1;i=i+1)
Q89[i+1]<=Q89[i];
end
end
endmodule
module shiftn_tb;
parameter n=4;
reg ld,clk,Din;
reg
[n-1:0]R;
wire [n-1:0]Q89;
shift_nbit s1(ld,Din,R,Q89,clk);
initial
begin
clk=0;
end
initial
$monitor($time,"ld=%b,Din=%b,R=%b,Q89=%b,clk=
%b",ld,Din,R,Q89,clk);
initial
begin
R=4'b1100; Din=1'b1;
ld=1'b1;
#25 ld=1'b0;
Din=1'b0;
#5
Din=1'b1;
#5
Din=1'b0;
#5
Din=1'b1;
#50 R=4'b1111;
#80 ld=1'b1;
end
endmodule
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ld
clk
Din
R
R(3)
R(2)
R(1)
R(0)
Q89
Q89(3)
Q89(2)
Q89(1)
Q89(0)
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200
220
240
ns
output:
0
ld=1,Din=1,R=1100,Q89=xxxx,clk=0
10
ld=1,Din=1,R=1100,Q89=1100,clk=1
20
ld=1,Din=1,R=1100,Q89=1100,clk=0
25
ld=0,Din=0,R=1100,Q89=1100,clk=0
30
ld=0,Din=1,R=1100,Q89=1001,clk=1
35
ld=0,Din=0,R=1100,Q89=1001,clk=1
40
ld=0,Din=1,R=1100,Q89=1001,clk=0
50
ld=0,Din=1,R=1100,Q89=0011,clk=1
60
ld=0,Din=1,R=1100,Q89=0011,clk=0
70
ld=0,Din=1,R=1100,Q89=0111,clk=1
80
ld=0,Din=1,R=1100,Q89=0111,clk=0
90
ld=0,Din=1,R=1111,Q89=1111,clk=1
100
ld=0,Din=1,R=1111,Q89=1111,clk=0
110
ld=0,Din=1,R=1111,Q89=1111,clk=1
120
ld=0,Din=1,R=1111,Q89=1111,clk=0
130
ld=0,Din=1,R=1111,Q89=1111,clk=1
140
ld=0,Din=1,R=1111,Q89=1111,clk=0
150
ld=0,Din=1,R=1111,Q89=1111,clk=1
160
ld=0,Din=1,R=1111,Q89=1111,clk=0
170
ld=1,Din=1,R=1111,Q89=1111,clk=1
180
ld=1,Din=1,R=1111,Q89=1111,clk=0
190
ld=1,Din=1,R=1111,Q89=1111,clk=1
200
ld=1,Din=1,R=1111,Q89=1111,clk=0
COUNTERS
DOWN COUNTER
UP COUNTER
UP DOWN COUNTER
RIPPLE CARRY COUNTER
DOWN COUNTER
AIM: To write a verilog code for a down counter using behavior level modeling.
module downcounter_beh (ld,res,R,clk,Q89);
input ld,clk,res;
input [3:0]R;
output [3:0]Q89;
reg [3:0]Q89;
begin
if(res)
Q89<=4'b0000;
else if(ld)
Q89<=R;
else
Q89<=Q89-1;
end
endmodule
module downcount_tb;
reg
ld,clk,res;
reg [3:0]R;
wire [3:0]Q89;
downcounter_beh u1(ld,res,R,clk,Q89);
initial
begin
clk=1'b0;
end
initial
$monitor($time,"ld=%b,res=%b,R=%b,clk=%b,Q89=
%b",ld,res,R,clk,Q89);
initial
begin
res=1'b1;
R=4'b1001;
#15 ld=1'b1;
#25 ld=1'b0; res=1'b0;
#40 R=4'b1001;
end
endmodule
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ld
clk
res
R
Q89
9
F
output:
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30
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90
100
110
120
ld=x,res=1,R=1001,clk=0,Q89=xxxx
ld=x,res=1,R=1001,clk=1,Q89=1111
ld=1,res=1,R=1001,clk=1,Q89=1111
ld=1,res=1,R=1001,clk=0,Q89=1111
ld=1,res=1,R=1001,clk=1,Q89=1111
ld=0,res=0,R=1001,clk=0,Q89=1111
ld=0,res=0,R=1001,clk=1,Q89=1110
ld=0,res=0,R=1001,clk=0,Q89=1110
ld=0,res=0,R=1001,clk=1,Q89=1101
ld=0,res=0,R=1001,clk=0,Q89=1101
ld=0,res=0,R=1001,clk=1,Q89=1100
ld=0,res=0,R=1001,clk=0,Q89=1100
ld=0,res=0,R=1001,clk=1,Q89=1011
ld=0,res=0,R=1001,clk=0,Q89=1011
400
ns
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ld=0,res=0,R=1001,clk=1,Q89=1010
ld=0,res=0,R=1001,clk=0,Q89=1010
ld=0,res=0,R=1001,clk=1,Q89=1001
ld=0,res=0,R=1001,clk=0,Q89=1001
ld=0,res=0,R=1001,clk=1,Q89=1000
ld=0,res=0,R=1001,clk=0,Q89=1000
ld=0,res=0,R=1001,clk=1,Q89=0111
ld=0,res=0,R=1001,clk=0,Q89=0111
ld=0,res=0,R=1001,clk=1,Q89=0110
ld=0,res=0,R=1001,clk=0,Q89=0110
ld=0,res=0,R=1001,clk=1,Q89=0101
ld=0,res=0,R=1001,clk=0,Q89=0101
ld=0,res=0,R=1001,clk=1,Q89=0100
ld=0,res=0,R=1001,clk=0,Q89=0100
ld=0,res=0,R=1001,clk=1,Q89=0011
ld=0,res=0,R=1001,clk=0,Q89=0011
ld=0,res=0,R=1001,clk=1,Q89=0010
ld=0,res=0,R=1001,clk=0,Q89=0010
ld=0,res=0,R=1001,clk=1,Q89=0001
ld=0,res=0,R=1001,clk=0,Q89=0001
ld=0,res=0,R=1001,clk=1,Q89=0000
ld=0,res=0,R=1001,clk=0,Q89=0000
ld=0,res=0,R=1001,clk=1,Q89=1111
UP COUNTER
AIM: To write a verilog code for a up counter using behavior level modeling.
module upcounter_beh (ld,res,R,clk,Q89);
input ld,clk,res;
input [3:0]R;
output [3:0]Q89;
reg [3:0]Q89;
begin
if(res)
Q89<=4'b0000;
else if(ld)
Q89<=R;
else
Q89<=Q89+1;
end
endmodule
module upcount_tb;
reg
ld,clk,res;
reg [3:0]R;
wire [3:0]Q89;
upcounter_beh u1(ld,res,R,clk,Q89);
initial
begin
clk=1'b0;
end
initial
initial
begin
res=1'b1;
R=4'b1001;
#15 ld=1'b1;
#25 ld=1'b0; res=1'b0;
#40 R=4'b1001;
end
endmodule
50
100
150
200
250
ns
300
ld
clk
res
R
Q89
X 0
output: 0
10
ld=x,res=1,R=1001,clk=1,Q89=0000
15
ld=1,res=1,R=1001,clk=1,Q89=0000
20
ld=1,res=1,R=1001,clk=0,Q89=0000
30
ld=1,res=1,R=1001,clk=1,Q89=0000
40
ld=0,res=0,R=1001,clk=0,Q89=0000
50
ld=0,res=0,R=1001,clk=1,Q89=0001
60
ld=0,res=0,R=1001,clk=0,Q89=0001
70
ld=0,res=0,R=1001,clk=1,Q89=0010
80
ld=0,res=0,R=1001,clk=0,Q89=0010
90
ld=0,res=0,R=1001,clk=1,Q89=0011
100
ld=0,res=0,R=1001,clk=0,Q89=0011
110
ld=0,res=0,R=1001,clk=1,Q89=0100
120
ld=0,res=0,R=1001,clk=0,Q89=0100
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
ld=0,res=0,R=1001,clk=1,Q89=0101
ld=0,res=0,R=1001,clk=0,Q89=0101
ld=0,res=0,R=1001,clk=1,Q89=0110
ld=0,res=0,R=1001,clk=0,Q89=0110
ld=0,res=0,R=1001,clk=1,Q89=0111
ld=0,res=0,R=1001,clk=0,Q89=0111
ld=0,res=0,R=1001,clk=1,Q89=1000
ld=0,res=0,R=1001,clk=0,Q89=1000
ld=0,res=0,R=1001,clk=1,Q89=1001
ld=0,res=0,R=1001,clk=0,Q89=1001
ld=0,res=0,R=1001,clk=1,Q89=1010
ld=0,res=0,R=1001,clk=0,Q89=1010
ld=0,res=0,R=1001,clk=1,Q89=1011
ld=0,res=0,R=1001,clk=0,Q89=1011
ld=0,res=0,R=1001,clk=1,Q89=1100
ld=0,res=0,R=1001,clk=0,Q89=1100
ld=0,res=0,R=1001,clk=1,Q89=1101
ld=0,res=0,R=1001,clk=0,Q89=1101
ld=0,res=0,R=1001,clk=1,Q89=1110
ld=0,res=0,R=1001,clk=0,Q89=1110
ld=0,res=0,R=1001,clk=1,Q89=1111
ld=0,res=0,R=1001,clk=0,Q89=1111
ld=0,res=0,R=1001,clk=1,Q89=0000
UP DOWN COUNTER
AIM: To write a verilog code for a up down counter using behavior level modeling.
module updowncounter (ld,res,R,clk,Q89,upd);
input ld,clk,res,upd;
input [3:0]R;
output [3:0]Q89;
reg [3:0]Q89;
begin
if(res)
Q89<=4'b1111;
else if(ld)
Q89<=R;
else if(upd)
Q89<=Q89+1;
else
Q89<=Q89-1;
end
endmodule
module updwn_tb;
reg
ld,clk,res,upd;
reg [3:0]R;
wire [3:0]Q89;
updowncounter u1(ld,res,R,clk,Q89,upd);
initial
begin
clk=1'b0;
end
initial
initial
begin
res=1'b1;upd=1'b1;
R=4'b1001;
#15 ld=1'b1;
#25 ld=1'b0; res=1'b0;
#40 R=4'b1001;
#20 upd=1'b0;
end
endmodule
50
100
150
200
250
300
350
ld
clk
res
upd
R
Q89
9
F
output:0
10
ld=x,res=1,R=1001,clk=1,Q89=1111
15
ld=1,res=1,R=1001,clk=1,Q89=1111
20
ld=1,res=1,R=1001,clk=0,Q89=1111
30
ld=1,res=1,R=1001,clk=1,Q89=1111
40
ld=0,res=0,R=1001,clk=0,Q89=1111
50
ld=0,res=0,R=1001,clk=1,Q89=0000
60
ld=0,res=0,R=1001,clk=0,Q89=0000
70
ld=0,res=0,R=1001,clk=1,Q89=0001
80
ld=0,res=0,R=1001,clk=0,Q89=0001
90
ld=0,res=0,R=1001,clk=1,Q89=0010
100
ld=0,res=0,R=1001,clk=0,Q89=0010
110
ld=0,res=0,R=1001,clk=1,Q89=0001
120
ld=0,res=0,R=1001,clk=0,Q89=0001
130
ld=0,res=0,R=1001,clk=1,Q89=0000
140
ld=0,res=0,R=1001,clk=0,Q89=0000
400
ns
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
ld=0,res=0,R=1001,clk=1,Q89=1111
ld=0,res=0,R=1001,clk=0,Q89=1111
ld=0,res=0,R=1001,clk=1,Q89=1110
ld=0,res=0,R=1001,clk=0,Q89=1110
ld=0,res=0,R=1001,clk=1,Q89=1101
ld=0,res=0,R=1001,clk=0,Q89=1101
ld=0,res=0,R=1001,clk=1,Q89=1100
ld=0,res=0,R=1001,clk=0,Q89=1100
ld=0,res=0,R=1001,clk=1,Q89=1011
ld=0,res=0,R=1001,clk=0,Q89=1011
ld=0,res=0,R=1001,clk=1,Q89=1010
ld=0,res=0,R=1001,clk=0,Q89=1010
ld=0,res=0,R=1001,clk=1,Q89=1001
ld=0,res=0,R=1001,clk=0,Q89=1001
ld=0,res=0,R=1001,clk=1,Q89=1000
ld=0,res=0,R=1001,clk=0,Q89=1000
ld=0,res=0,R=1001,clk=1,Q89=0111
ld=0,res=0,R=1001,clk=0,Q89=0111
ld=0,res=0,R=1001,clk=1,Q89=0110
ld=0,res=0,R=1001,clk=0,Q89=0110
ld=0,res=0,R=1001,clk=1,Q89=0101
RIPPLE CARRY COUNTER
AIM: To write a verilog code for a ripple carry counter using behavior level modeling.
module ripple_carry (q,clk,res);
input clk,res ;
output [3:0]q;
wire [3:0]q;
tff t1(clk,res,q[0]);
tff t2(q[0],res,q[1]);
endmodule
module dff(d,clk,res,q);
input d,clk,res;
output q;
reg q;
always @(negedge clk or posedge res)
begin
if(res)
q<=0;
else
q<=d;
end
endmodule
module tff(clk,res,q);
input clk,res;
output q;
wire d;
dff f1(d,clk,res,q);
not n1(d,q);
endmodule
module ripple_tb;
reg clk,res;
wire [3:0]q;
ripple_carry r1(q,clk,res);
initial
$monitor($time,"q=%b,res=%b",q,res);
initial
begin
clk=1'b0;
end
initial
begin
res=1;
#20 res=0;
#50 res=1;
#30 res=0;
end
endmodule
20
40
60
80
100
120
140
160
180
200
clk
res
q
Output:
0
20
30
q=0000,res=1
q=0001,res=0
q=0010,res=0
220
240
260
280
ns
40
50
60
70
100
110
120
130
140
150
160
170
180
190
200
q=0011,res=0
q=0100,res=0
q=0101,res=0
q=0000,res=1
q=0001,res=0
q=0010,res=0
q=0011,res=0
q=0100,res=0
q=0101,res=0
q=0110,res=0
q=0111,res=0
q=1000,res=0
q=1001,res=0
q=1010,res=0
q=1011,res=0
FINITE SEQUENCE MACHINES
MOORE SEQUENCE DETECTOR 101
MEALEY SEQUENCE DETECTOR 101
MOORE SEQUENCE DETECTOR

AIM: To write a verilog code for detecting the sequence 101 using behavior level
modeling.
`timescale 1ns/1ps
module moore(in,out89,clk,res);
input in,clk,res;
output out89;
reg out89;
reg [1:0]state,nxt_state;
parameter s0=0,s1=1,s2=2,s3=3;
always @ (in or state)
begin
case(state)
s0:begin
out89=0;
if(in)
nxt_state=s1;
else
nxt_state=s0;
end
s1:begin
out89=0;
if(in)
nxt_state=s1;
else
nxt_state=s2;
end
s2:begin
out89=0;
if(in)
nxt_state=s3;
else
nxt_state=s0;
end
s3:begin
out89=1;
if(in)
nxt_state=s1;
else
nxt_state=s2;
end
default:begin
out89=0;
nxt_state=s0;
end
endcase
end
begin
if(res)
state<=s0;
else
state<=nxt_state;
end
endmodule
module moore_tb;
reg
in,clk,res;
wire out89;
moore m1(in,out89,clk,res);
initial
$monitor($time,"in=%b,out89=%b",in,out89);
initial
begin
clk=1'b1;
end
initial
begin
in=0;res=1;
#10 in=1;res=0;
#10 in=0;
#10 in=0;
#10 in=1;
#10 in=0;
#10 in=1;
#10 in=1;
end
endmodule
10
20
30
in
clk
res
out89
output:
:
:
:
:
:
:
:
:
0in=0,out89=0
10in=1,out89=0
20in=0,out89=0
40in=1,out89=0
50in=0,out89=0
60in=1,out89=0
70in=1,out89=1
80in=1,out89=0
40
50
60
70
80
90
100
110
120
130
140
150
ns
MEALEY SEQUENCE DETECTOR

AIM: To write a verilog code for detecting the sequence 101 using behavior level
modeling.
module mealey(in,out89,clk,res);
input in,clk,res;
output out89;
reg out89;
reg [1:0]state,nxt_state;
parameter s0=0,s1=1,s2=2;
always @ (in or state)
begin
case(state)
s0:if(in)
begin
nxt_state=s1;
out89=0;
end
else
begin
nxt_state=s0;
out89=0;
end
s1:if(in)
begin
nxt_state=s1;
out89=0;
end
else
begin
nxt_state=s2;
out89=0;
end
s2:if(in)
begin
nxt_state=s1;
out89=1;
end
else
begin
nxt_state=s0;
out89=0;
end
endcase
end
begin
if(res)
state<=s0;
else
state<=nxt_state;
end
endmodule
module mealey_tb;
reg
in,clk,res;
wire out89;
parameter s0=0,s1=1,s2=2;
mealey m1(in,out89,clk,res);
initial
$monitor($time,"in=%b,out89=%b",in,out89);
initial
begin
clk=1'b1;
end
initial
begin
in=0;res=1;
#10 in=1;res=0;
#10 in=0;
#10 in=0;
#10 in=1;
#10 in=0;
#10 in=1;
#10 in=1;
end
endmodule
10
in
clk
res
out89
Output:
0
10
20
40
50
60
70
in=0,out89=0
in=1,out89=0
in=0,out89=0
in=1,out89=0
in=0,out89=0
in=1,out89=1
in=1,out89=0
20
30
40
50
60
70
80
90
100
110
120
130
140
150
ns
ARITHMETIC UNITS
ADDERS
SUBTRACTORS
HALF ADDER
AIM: To write a verilog code for half adder using gate level modeling.
module halfadder ( a ,b ,c ,s );
input a ;
wire a ;
input b ;
wire b ;
output c ;
wire c ;
output s ;
wire s ;
xor g1(s,a,b);
nd g2(c,a,b);
endmodule
20
40
60
80
100
120
140
160
a
b
c
s
FULL ADDER
AIM: To write a verilog code for full adder using data level modeling.
module fa_conc (a,b,cin,s89,c89);
input [3:0]a,b;
input cin;
output [3:0]s89;
output c89;
wire [3:0]a,b,s89;
wire cin,c89;
assign {c89,s89}=a+b+cin;
endmodule
module stimulus;
reg [3:0]a,b;
reg cin;
180
200
220
240
260
280
ns
wire [3:0]s89;
wire c89;
fa_conc f1(a,b,cin,s89,c89);
initial
$monitor($time,"a=%d,b=%d,cin=%d,s89=%d,c89=%d",a,b,cin,s89,c89);
initial
begin
a=3;b=4;cin=0;
end
endmodule
50
100
150
200
250
300
350
cin
s89
c89
FULL ADDER
AIM: To write a verilog code for full adder using gate level modeling.
module fulladder ( a ,cin ,b ,cout ,s );
input a ;
wire a ;
input cin ;
wire cin ;
input b ;
wire b ;
output cout ;
wire cout ;
output s ;
wire s ;
wire x;
wire y;
400
ns
wire z;
xor g1(x,a,b);
and g2(y,a,b);
and g3(z,cin,x);
xor g4(s,x,cin);
or g5(cout,y,z);
endmodule
140
160
180
200
220
240
260
280
300
320
340
360
x
y
z
a
cin
b
cout
s
1-BIT FULL ADDER

AIM: To write a verilog code for 1-bit full adder using data level modeling.
module fa ( a ,cin ,b ,s89 ,c89 );
input a ;
wire a ;
input cin ;
wire cin ;
input b ;
wire b ;
output s89 ;
wire s89 ;
output c89 ;
wire c89 ;
assign s89=a^b^cin;
assign c89 =((a&b)|(b&cin)|(cin&a));
380
ns
endmodule
5
10
15
20
25
30
35
40
a
cin
b
s89
c89
4-BIT FULL ADDER

AIM: To write a verilog code for 4-bit full adder using data level modeling.
module fa ( a ,cin ,b ,s89 ,c89 );
input a ;
wire a ;
input cin ;
wire cin ;
input b ;
wire b ;
output s89 ;
wire s89 ;
output c89 ;
wire c89 ;
assign s89=a^b^cin;
assign c89 =((a&b)|(b&cin)|(cin&a));
ns
endmodule
module fa4(a,b,cin,s89,c89);
input [3:0]a,b;
input cin;
output [3:0]s89;
output c89;
wire [3:0]a,b,s89;
wire cin,c89;
wire c1,c2,c3;
fa f1(a[0],b[0],cin,s89[0],c1);
fa f2(a[1],b[1],c1,s89[1],c2);
fa f3(a[2],b[2],c2,s89[2],c3);
fa f4(a[3],b[3],c3,s89[3],c89);
endmodule
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
c1
c2
c3
a
cin
s89
c89
GENERIC FULL ADDER

AIM: To write a verilog code for generic full adder using behavior level modeling.
module gen_fuladd (a,b,cin,s89,cout);
parameter n=4;
input [n-1:0]a,b;
input cin;
output [n-1:0]s89;
output cout;
reg [n-1:0]s89;
reg cout;
reg [n:0]co;
integer k;
always @(*)
begin
170
ns
co[0]=cin;
for(k=0;k<n;k=k+1)
begin
s89[k]=a[k]^b[k]^co[k];
co[k+1]=(a[k]&b[k])|(a[k]&co[k])|(b[k]&co[k]);
end
cout=co[n];
end
endmodule
module gen_tb;
parameter n=4;
reg [n-1:0]a,b;
reg cin;
wire [n-1:0]s89;
wire cout;
gen_fuladd g1(a,b,cin,s89,cout);
initial
$monitor($time,"a=%b,b=%b,cin=%b,s89=%b,cout=
%b",a,b,cin,s89,cout);
initial
begin
a=5;b=4;cin=0;
#10 a=13;
#10 cin=1;
end
endmodule
10
20
30
40
cin
s89
cout
output:
0
10
20
a=0101,b=0100,cin=0,s89=1001,cout=0
a=1101,b=0100,cin=0,s89=0001,cout=1
a=1101,b=0100,cin=1,s89=0010,cout=1
50
60
70
80
ns
HALF SUBTRACTOR
AIM: To write a verilog code for half subtractor using gate level modeling.
module halfsub ( a ,b ,b89 ,s89 );
input a ;
wire a ;
input b ;
wire b ;
output b89 ;
wire b89 ;
output s89 ;
wire s89 ;
wire abar;
xor g1(s89,a,b);
not g2(abar,a);
and g3(b89,abar,b);
endmodule
60
70
80
90
100
110
120
130
140
150
160
170
abar
a
b
b89
s89
FULL SUBTRACTOR
AIM: To write a verilog code for full subtractor using gate level modeling.
module fulsub ( a ,b ,bor ,s ,c );
input a ;
wire a ;
input b ;
wire b ;
input c ;
wire c ;
output bor ;
wire bor ;
output s ;
wire s ;
wire abar, x, y, z;
xor g1(s,a,b,c);
not g2(abar,a);
180
190
ns
xor g3(x,b,c);
and g4(y,b,c);
and g5(z,abar,x);
or g6(bor,z,y);
endmodule
270
280
290
300
310
320
330
340
350
360
370
abar
x
y
z
a
b
bor
s
c
FULL SUBTRACTOR
AIM: To write a verilog code for full subtractor using data level modeling.
module sub_conc (a,b,bin,b89,d89);
input [3:0]a,b;
output [3:0]d89;
input bin;
output b89;
wire [3:0]a,b,d89;
wire b89,bin;
assign {b89,d89}=a-b-bin;
endmodule
module stimulus;
reg [3:0]a,b;
reg bin;
wire[3:0]d89;
380
390
ns
wire b89;
sub_conc s1(a,b,bin,b89,d89) ;
initial
begin
$monitor($time,"a=%d,b=%d,bin=%d,d89=%d,b89=
%d",a,b,bin,d89,b89);
end
initial
begin
a=5;b=3;bin=0;
#10 a=9;b=10;bin=1;
#10 a=2;b=7;bin=1;
#10 a=7;b=7;bin=1;
end
endmodule
20
40
60
80
100
120
140
160
180
200
bin
d89
b89
1-BIT FULL SUBTRACTOR

AIM: To write a verilog code for 1-bit full subtractor using data level modeling.
module sub_1 (d89,b89,a,b,bin);
input a,b,bin;
output d89,b89;
wire a,b,bin,d89,b89;
assign d89=a^b^bin;
assign b89=(~a&b)|(~a&bin)|(b&bin);
endmodule
module stimulus;
reg a,b,bin;
wire d89,b89;
sub_1 s1(d89,b89,a,b,bin);
initial
begin
ns
$monitor($time,"a=%b,b=%b,bin=%b,d89=%b,b89=
%b",a,b,bin,d89,b89);
end
initial
begin
a=1'b0;b=1'b0;bin=1'b0;
#10 a=1'b0;b=1'b0;bin=1'b1;
#10 a=1'b0;b=1'b1;bin=1'b0;
#10 a=1'b0;b=1'b1;bin=1'b1;
#10 a=1'b1;b=1'b0;bin=1'b0;
#10 a=1'b1;b=1'b0;bin=1'b1;
#10 a=1'b1;b=1'b1;bin=1'b0;
#10 a=1'b1;b=1'b1;bin=1'b1;
end
endmodule
20
d89
b89
a
b
bin
40
60
80
100
120
140
160
180
200
ns
DIGITAL UNITS
MULTIPLEXERS
DEMULTIPLEXERS
ENCODERS
DECODERS
ALU
COMPARATOR
MULTIPLXER 4 TO 1
AIM: To write a verilog code for 4 to 1 multiplexer using data level modeling.
module mux_df (i0,i1,i2,i3,s0,s1,y89);
input i0,i1,i2,i3,s0,s1;
output y89;
wire i0,i1,i2,i3,s0,s1,y89;
assign y89=(~s0&~s1&i0)|(~s0&s1&i1)|(s0&~s1&i2)|(s0&s1&i3);
endmodule
module stimulus;
reg i0,i1,i2,i3,s0,s1;
wire y89;
mux_df m1(i0,i1,i2,i3,s0,s1,y89);
initial
begin
$monitor($time,"i0=%b,i1=%b,i2=%b,i3=%b,s0=%b,s1=
%b,y89=%b",i0,i1,i2,i3,s0,s1,y89);
end
initial
begin
i0=1'b1;i1=1'b0;i2=1'b0;i3=1'b0;s0=1'b0;s1=1'b0;
#10 i0=1'b0;i1=1'b1;i2=1'b0;i3=1'b0;s0=1'b0;s1=1'b1;
#10 i0=1'b0;i1=1'b0;i2=1'b1;i3=1'b0;s0=1'b1;s1=1'b0;
#10 i0=1'b0;i1=1'b0;i2=1'b0;i3=1'b1;s0=1'b1;s1=1'b1;
end
endmodule
20
i0
i1
i2
i3
s0
s1
y89
40
60
80
100
120
140
160
180
200
ns
MULTIPLXER 4 TO 1
AIM: To write a verilog code for 4 to 1 multiplexer using behavior level modeling.
module muxbf (y89,s,i);
input [1:0]s;
input [3:0]i;
output y89;
reg y89;
always @(*)
case(s)
0:y89=i[0];
1:y89=i[1];
2:y89=i[2];
3:y89=i[3];
endcase
endmodule
module muxbf_tb;
reg [1:0]s;
reg [3:0]i;
wire y89;
muxbf m1(y89,s,i);
initial
$monitor($time,"y89=%b,s=%b,i=%b",y89,s,i);
initial
begin
i=1;s=0;
#10 i=2;s=1;
#10 i=4;s=2;
#10 i=8;s=3;
end
endmodule
10
20
30
y89
40
50
60
70
80
90
100
ns
Output:
0
10
20
30
y89=1,s=00,i=0001
y89=1,s=01,i=0010
y89=1,s=10,i=0100
y89=1,s=11,i=1000
DEMULTIPLXER
AIM: To write a verilog code for demultiplexer using gate level modeling.
module demux ( i ,s0 ,s1,y );
input i ;
wire i ;
input s0 ;
wire s0 ;
input s1 ;
wire s1 ;
wire s0bar,s1bar;
output [3:0]y;
wire [3:0]y;
not n1(s0bar,s0);
not n2(s1bar,s1);
and g1(y[0],i,s0bar,s1bar);
and g2(y[1],i,s0bar,s1);
and g3(y[2],i,s0,s1bar);
and g4(y[3],i,s0,s1);
endmodule
module demux_tb;
reg i,s0,s1;
wire [3:0]y;
demux h( i ,s0 ,s1,y );
initial
begin
$monitor($time ,"i=%b,s0=%b,s1=%b,y=%b",i,s0,s1,y);
i=1'b1;
s0=1'b0;s1=1'b0;
#10 s0=1'b0;s1=1'b1;
#10
s0=1'b1;s1=1'b0;
#10
s0=1'b1;s1=1'b1;
end
endmodule
20
40
i
s0
s1
y
y(3)
y(2)
y(1)
y(0)
60
80
100
120
140
160
180
200
ns
DEMULTIPLXER
AIM: To write a verilog code for demultiplexer using data flow modeling.
module demux_df (y89,i,s0,s1);
input i,s0,s1;
output [3:0]y89;
assign y89[0]=~s0&~s1&i,
y89[1]=~s0&s1&i,
y89[2]=s0&~s1&i,
y89[3]=s0&s1&i;
endmodule
module de_tb;
reg i,s0,s1;
wire [3:0]y89;
demux_df d1(y89,i,s0,s1);
initial
begin
$monitor($time,"y89=%b,i=%b,s0=%b,s1=%b",y89,i,s0,s1);
end
initial
begin
i=1'b1;s0=1'b0;s1=1'b0;
#10 s0=1'b0;s1=1'b1;
#10 s0=1'b1;s1=1'b0;
#10 s0=1'b1;s1=1'b1;
end
endmodule
10
20
30
i
s0
s1
y89
output:
0 y89=0001,i=1,s0=0,s1=0
10 y89=0010,i=1,s0=0,s1=1
20 y89=0100,i=1,s0=1,s1=0
30 y89=1000,i=1,s0=1,s1=1
40
50
60
70
80
90
100
ns
DEMULTIPLXER 2 TO 4
AIM: To write a verilog code for demultiplexer 2 to 4 using behavior level modeling.
module demuxbf (y89,i,s);
input [1:0]s;
input i;
output y89;
reg [3:0]y89;
always @(*)
if(i)
begin
case(s)
0:y89=4'b0001;
1:y89=4'b0010;
2:y89=4'b0100;
3:y89=4'b1000;
endcase
end
else
y89=4'b0000;
endmodule
module demuxbf_tb;
reg i;
reg [1:0]s;
wire [3:0]y89;
demuxbf d1(y89,i,s);
initial
$monitor ($time,"y89=%b,i=%b,s=%b",y89,i,s);
initial
begin
i=1;s=0;
#10 s=1;
#10 s=2;
#10 s=3;
#10 i=0;
end
endmodule
10
20
30
40
i
s
y89
50
60
70
80
90
100
ns
output:
0
10
20
30
40
y89=0001,i=1,s=00
y89=0010,i=1,s=01
y89=0100,i=1,s=10
y89=1000,i=1,s=11
y89=0000,i=0,s=11
ENCODER 8 T0 3
AIM: To write a verilog code for 8 to 3 encoder using gate level modeling.
module encoder (a,y);
input [7:0]a;
wire [7:0]a;
output [2:0]y;
wire [2:0]y;
or g1(y[2],a[4],a[5],a[6],a[7]);
or g2(y[1],a[2],a[3],a[6],a[7]);
or g3(y[0],a[1],a[3],a[5],a[7]);
endmodule
module encoder_tb;
reg [7:0]a;
wire [2:0]y;
encoder h1(a,y);
initial
begin
$monitor($time,"a=%h,y=%h",a,y);
a=8'h01;
#10 a=8'h02;
#10 a=8'h04;
#10 a=8'h08;
#10 a=8'h10;
#10 a=8'h20;
#10 a=8'h40;
#10 a=8'h80;
end
endmodule
20
40
60
80
01 02 04 08 10
20 40 80
a(7)
a(6)
a(5)
a(4)
a(3)
a(2)
a(1)
a(0)
y
y(2)
y(1)
y(0)
100
120
140
160
180
200
ns
ENCODER 8 T0 3
AIM: To write a verilog code for 8 to 3 encoder using data flow modeling.
module encoder_df_8to3 (y89,a);
input [7:0]a;
output [2:0]y89;
assign y89[0]=a[1]|a[3]|a[5]|a[7],
y89[1]=a[2]|a[3]|a[6]|a[7],
y89[2]=a[4]|a[6]|a[5]|a[7];
endmodule
module enco_tb;
reg [7:0]a;
wire [2:0]y89;
encoder_df_8to3 e1(y89,a);
initial
begin
$monitor($time,"y89=%b,a=%b",y89,a);
end
initial
begin
a=8'b00000001;
#10 a=8'b00000010;
#10 a=8'b00000100;
#10 a=8'b00001000;
#10 a=8'b00010000;
#10 a=8'b00100000;
#10 a=8'b01000000;
#10 a=8'b10000000;
end
endmodule
20
40
60
80
01 02 04 08 10
20 40 80
y89
100
120
140
160
180
200
ns
output:
0
10
20
30
40
50
60
70
y89=000,a=00000001
y89=001,a=00000010
y89=010,a=00000100
y89=011,a=00001000
y89=100,a=00010000
y89=101,a=00100000
y89=110,a=01000000
y89=111,a=10000000
ENCODER 8 TO 3
AIM: To write a verilog code for 8 to 3 encoder using behavior level modeling.
module encoderbf (in,out);
input [7:0]in;
output out;
reg [2:0]out;
always @(*)
begin
if(in[1]|in[3]|in[5]|in[7])
out[0]=1;
else out[0]=0;
if(in[2]|in[3]|in[6]|in[7])
out[1]=1;
else out[1]=0;
if(in[4]|in[5]|in[6]|in[7])
out[2]=1;
else out[2]=0;
end
endmodule
module encobf_tb;
reg [7:0]in;
wire[2:0]out;
encoderbf e1(in,out);
initial
$monitor($time,"in=%b,out=%b",in,out);
initial
begin
in=8'h01;
#10 in=8'h02;
#10 in=8'h04;
#10 in=8'h08;
#10 in=8'h10;
#10 in=8'h20;
#10 in=8'h40;
#10 in=8'h80;
end
endmodule
10
20
30
40
50
60
70
in
01
02
04
08
10
20
40
80
out
80
90
100
ns
output:
0
10
20
30
40
50
60
70
in=00000001,out=000
in=00000010,out=001
in=00000100,out=010
in=00001000,out=011
in=00010000,out=100
in=00100000,out=101
in=01000000,out=110
in=10000000,out=111
DECODER 2 T0 4
AIM: To write a verilog code for 2 to 4 decoder using data flow modeling.
module decoder_df_2to4 (i0,i1,e,out89);
input e,i0,i1;
output [3:0]out89;
assign out89[0]=e&~i0&~i1,
out89[1]=e&~i0&i1,
out89[2]=e&i0&~i1,
out89[3]=e&i0&i1;
endmodule
module deco_tb;
reg e,i0,i1;
wire [3:0]out89;
decoder_df_2to4 d1(out89,e,i0,i1);
initial
begin
$monitor($time,"out89=%b,e=%b,i0=%b,i1=%b",out89,e,i0,i1);
end
initial
begin
e=1'b1;i0=1'b0;i1=1'b0;
#10 i0=1'b0;i1=1'b1;
#10 i0=1'b1;i1=1'b0;
#10 i0=1'b1;i1=1'b1;
end
endmodule
10
20
30
e
i0
i1
out89
output:
0 out89=0001,e=1,i0=0,i1=0
10 out89=0010,e=1,i0=0,i1=1
20 out89=0100,e=1,i0=1,i1=0
30 out89=1000,e=1,i0=1,i1=1
40
50
60
70
80
90
100
ns
DECODER 2 T0 4
AIM: To write a verilog code for 2 to 4 decoder using behavior level modeling.
module decoder_bf (i,e,y89);
input e;
input [1:0]i;
output y89;
reg [3:0]y89;
always @(*)
if(e)
begin
case(i)
0: y89=4'b0001;
1: y89=4'b0010;
2: y89=4'b0100;
3: y89=4'b1000;
endcase
end
else
y89=4'bxxxx;
endmodule
module decobf_tb;
reg e;
reg [1:0]i;
wire [3:0]y89;
decoder_bf d1(i,e,y89);
initial
begin
$monitor($time,"y89=%b,e=%b,i=%b",y89,e,i);
end
initial
begin
e=1'b1;i=2'b00;
#10 i=2'b01;
#10 i=2'b10;
#10 i=2'b11;
#10 e=1'b0;
end
endmodule
10
20
30
40
e
i
y89
50
60
70
80
90
100
ns
output:
0
10
20
30
40
y89=0001,e=1,i=00
y89=0010,e=1,i=01
y89=0100,e=1,i=10
y89=1000,e=1,i=11
y89=xxxx,e=0,i=11
ALU
AIM: To write a verilog code for an ALU using behavior level modeling.
module alu (s,en,out89,a,b);
input [2:0]s;
input [3:0]a,b;
input en;
output [3:0]out89;
reg [3:0]out89;
always @(*)
if(en)
begin
case(s)
0:out89=a+b;
1:out89=a-b;
2:out89=a/b;
3:out89=a*b;
4:out89=a%b;
5:out89=~a;
6:out89=~b;
7:out89=a^b;
endcase
end
else
out89=4'bxxxx;
endmodule
module alu_tb;
reg
[2:0]s;
reg [3:0]a,b;
reg en;
wire [3:0]out89;
alu a1(s,en,out89,a,b);
initial
$monitor($time,"s=%b,en=%b,out89=%b,a=%b,b=%b",s,en,out89,a,b);
initial
begin
en=1'b0;a=5;b=4;
#10 en=1'b1;s=0;
#10 s=1;
#10 s=2;
#10 s=3;
#10 s=4;
#10 s=5;
#10 s=6;
#10 s=7;
end
endmodule
20
40
2
60
80
100
en
out89
output:
0
10
20
30
40
50
60
70
80
s=xxx,en=0,out89=xxxx,a=0101,b=0100
s=000,en=1,out89=1001,a=0101,b=0100
s=001,en=1,out89=0001,a=0101,b=0100
s=010,en=1,out89=0001,a=0101,b=0100
s=011,en=1,out89=0100,a=0101,b=0100
s=100,en=1,out89=0001,a=0101,b=0100
s=101,en=1,out89=1010,a=0101,b=0100
s=110,en=1,out89=1011,a=0101,b=0100
s=111,en=1,out89=0001,a=0101,b=0100
120
140
160
180
200
ns
4-BIT COMPARATOR
AIM: To write a verilog code for a 4-bit comparator using behavior level modeling.
`timescale 1ns/1ps
module comp(a,b,e,g,l);
input [3:0]a,b;
output e,g,l;
reg e,g,l;
always @(a or b)
begin
if(a>b)
begin
e=0;
g=1;
l=0;
end
else if(a<b)
begin
e=0;
g=0;
l=1;
end
else
begin
e=1;
g=0;
l=0;
end
end
endmodule
module comp_tb;
reg [3:0]a,b;
wire e,g,l;
comp c1(a,b,e,g,l);
initial
$monitor($time,"a=%b,b=%b,e=%b,g=%b,l=%b",a,b,e,g,l);
initial
begin
a=8;
b=8;
#20 a=5;
#20 b=2;
end
endmodule
10
20
30
40
50
5
2
e
g
l
output:
0
20
40
a=1000,b=1000,e=1,g=0,l=0
a=0101,b=1000,e=0,g=0,l=1
a=0101,b=0010,e=0,g=1,l=0
60
70
80
90
100
110
120
130
140
150
ns

All GATEs Using VHDL

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All GATEs Using VHDL

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INDEX

NAME OF THE EXPERIMENT

BASIC LOGIC GATES

BASIC LOGIC GATES

SYNCHRONOUS S-R FLIP FLOP

ASYNCHRONOUS S-R FLIP FLOP

SYNCHRONOUS J-K FLIP FLOP

ASYNCHRONOUS J-K FLIP FLOP

SYNCHRONOUS D FLIP FLOP

ASYNCHRONOUS D FLIP FLOP

forever #5 clk =~clk;

SYNCHRONOUS T FLIP FLOP

ASYNCHRONOUS T FLIP FLOP

REALISATION OF FOUR VARIABLE FUNCTION

REALISATION OF FOUR VARIABLE FUNCTION

4 BIT SHIFT REGISTER

n BIT SHIFT REGISTER

FOUR BIT SHIFT REGISTER

n- BIT SHIFT REGISTER

FINITE SEQUENCE MACHINES

MOORE SEQUENCE DETECTOR 101

MEALEY SEQUENCE DETECTOR 101

MOORE SEQUENCE DETECTOR

MEALEY SEQUENCE DETECTOR

1-BIT FULL ADDER

4-BIT FULL ADDER

GENERIC FULL ADDER

1-BIT FULL SUBTRACTOR

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