74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

February 1994 Revised May 2005

74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
General Description
The LCX16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LCX16245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.

Features
s 5V tolerant inputs and outputs s 2.3V3.6V VCC specifications provided s 4.5 ns tPD max (VCC

3.3V), 20 PA ICC max

s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r24 mA output drive (VCC

3.0V)

s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human body model ! 2000V Machine model ! 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.

Ordering Code:
Order Number 74LCX16245G (Note 2)(Note 3) 74LCX16245MEA (Note 3) 74LCX16245MTD (Note 3) Package Number BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 2: Ordering code G indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Logic Symbol

2005 Fairchild Semiconductor Corporation

DS012001

www.fairchildsemi.com

74LCX16245

Connection Diagrams
Pin Assignment for SSOP and TSSOP

Pin Descriptions
Pin Names OEn T/Rn A0A15 B0B15 NC Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs No Connect

FBGA Pin Assignments

1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCC GND GND GND VCC NC T/R2 4 OE1 NC VCC GND GND GND VCC NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15

Truth Tables
Inputs Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H T/R2 L H X Outputs Bus B8B15 Data to Bus A8A15 Bus A8A15 Data to Bus B8B15 HIGH Z State on A8A15, B8B15 T/R1 L H X Outputs Bus B0B7 Data to Bus A0A7 Bus A0A7 Data to Bus B0B7 HIGH Z State on A0A7, B0B7

(Top Thru View)

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Logic Diagrams

Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com

74LCX16245

Absolute Maximum Ratings(Note 4)

Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI  GND VO  GND VO ! VCC V mA mA mA mA mA

0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC  0.5 50 50 50 r50 r100 r100 65 to 150

qC

Recommended Operating Conditions (Note 6)

Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V2.0V, VCC 3.0V 3.0V  3.6V 2.7V  3.0V 2.3V  2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V

r24 r12 r8 40

0 85 10

mA

qC
ns/V

't/'V

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs or I/O's must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ IOFF Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current Conditions VCC (V) 2.3  2.7 2.7  3.6 2.3  2.7 2.7  3.6 TA

40qC to 85qC
Max

Min 1.7 2.0

Units V

0.7 0.8 VCC  0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55

100 PA 8 mA 12 mA 18 mA 24 mA

100 PA 8mA 12 mA 16 mA 24 mA

2.3  3.6 2.3 2.7 3.0 3.0 2.3  3.6 2.3 2.7 3.0 3.0 2.3  3.6 2.3  3.6 0

0 d VI d 5.5V 0 d VO d 5.5V VI V IH or VIL 5.5V VI or VO

r5.0 r5.0
10

PA PA PA

www.fairchildsemi.com

74LCX16245

DC Electrical Characteristics
Symbol ICC Parameter Quiescent Supply Current Increase in ICC per Input VI VIH

(Continued)
VCC (V) VCC or GND VCC 0.6V 2.33.6 2.33.6 2.33.6 TA

Conditions

40qC to 85qC
Max 20

Units

Min

3.6V d VI, VO d 5.5V (Note 7)

r20
500

PA PA

'ICC

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics
TA Symbol Parameter VCC CL Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 8) Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 3.3V r 0.3V 50 pF Max 4.5 4.5 6.5 6.5 6.4 6.4 1.0 1.0

40qC to 85qC, RL
VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.7V 50 pF Max 5.2 5.2 7.2 7.2 6.9 6.9

500: VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.5V r 0.2V 30 pF Max 5.4 5.4 8.5 8.5 7.7 7.7 ns ns ns ns Units

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

Dynamic Switching Characteristics

Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30 pF, VIH 50 pF, VIH 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC 0.8 0.6 Typical Units V V

0.8 0.6

Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 20 Units pF pF pF

www.fairchildsemi.com

74LCX16245

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND

Waveform for Inverting and Non-Inverting Functions

3-STATE Output High Enable and Disable Times for Logic

Propagation Delay. Pulse Width and trec Waveforms

Setup Time, Hold Time and Recovery Time for Logic

3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL  0.3V VOH  0.3V 2.7V 1.5V 1.5V VOL  0.3V VOH  0.3V

trise and tfall

2.5V r 0.2V VCC/2 VCC/2 VOL  0.15V VOH  0.15V

www.fairchildsemi.com

74LCX16245

Schematic Diagram Generic for LCX Family

www.fairchildsemi.com

74LCX16245

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A

www.fairchildsemi.com

74LCX16245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A

www.fairchildsemi.com

74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com