Cpe358/Cs381 Switching Theory and Logical Design Class 6

CpE358/CS381 Switching Theory and Logical Design Class 6
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
Copyright 2004 Stevens Institute of Technology All rights reserved
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Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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Characteristics of Combinatorial Circuits

Linear signal flow input to output No feedback paths No storage elements I0 I1 I2 I3 S1 S0 Y
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Asynchronous Sequential Circuit
G I
n inputs
Combinational Circuit
JG O
m outputs
Delay Element(s)
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Synchronous Sequential Circuit
G I
n inputs
JG O
m outputs
Storage Element(s) Clock
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Feedback Paths in Logic Circuits

Condition of signal leads is indeterminate
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td
td
td
With some technologies (e.g., CMOS) this can actually be used to build an oscillator (f ~ 1/(3td) )
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Basic Storage Element - Latches

NOR gate S-R Latch R Q
S 1 0 0 0 R 0 0 1 0 1 Q 1 1 0 0 0 Q 0 0 1 1 0
Values Held
S R Q Q
S Q
R Q
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NAND gate S-R Latch S Q
S 1 1 0 1 R 0 1 1 1 1 Q 0 0 1 1 1 Q 1 1 0 0 1
Values Held
Q R
S R Q Q
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
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NAND gate S-R Latch with control input S Q C Q R S R C Q No change ? S Q C R Q
C 0 1 1 1 1 S X 0 0 1 1 R X 0 1 0 1 Qi+1 Qi Qi 0 1 ?
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D Latch with control input D Q C Q
C 0 1 1 D X 0 1 Qi+1 Qi 0 1
D C Q D Q C Q
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Limitations of Level Sensitive Latches

What is timing of D vs. C?
D C Q
A slight change in timing could product different results: D C Q
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Master-Slave D Flip-Flop
Q(t + 1) = D
D Q C Q
D Q
D Q C Q
D Q C Q
Q D Q
Clock Q
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Master-Slave Timing
D C Q
Master D C Master Q Slave D C Slave Q Slave Q guaranteed stable

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Master doesnt change while C high
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Variations of D Flop-flops
D Q
D Q
Q Positive Edge Triggered D Q
Q Negative Edge Triggered D Q
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J-K Flip Flop

Q(t + 1) = JQ '+ K ' Q
J K 0 0 1 1 Qi+1 Qi 1 0 Qi Meaning No change Clockin 1 Clockin 0 Toggle
J Q
0 1 0 1
K Q
Constructing a J-K from a D J K D Q Q D
Constructing a D from a J-K J Q Q
K Q Q Q
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Toggle Flip Flop

Q(t + 1) = T Q
T Qi+1 Qi Qi Meaning No change Toggle
T Q
0 1
Constructing a T from a JK
Constructing a T from a D
J Q
D Q
K Q
Q
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Immediate Inputs to Flip-Flops

Sometimes referred to as Preset and Clear, the immediate inputs can be used to preset a known state at startup
J 0 K 0 0 1 1 X X X S 1 1 1 1 0 1 0 R 1 1 1 1 1 0 0 Qi+1 Qi 1 0 Qi 1 0 ? Meaning No change Clockin 1 Clockin 0 Toggle Set Reset Undefined
1 0 1 X X X
K R Q
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Generic Sequential Clocked Sequential Circuit
G I
n inputs
JG O
m outputs
Storage Element(s) Clock
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Generic Sequential Clocked Sequential Circuit

Storage elements contain system state Combinational circuit determines next state
G I
n inputs
JG O
m outputs
System State
Storage Element(s)
Next State
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Abstraction of Sequential Circuit
State
Outputs
State Transition Controls
Inputs
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State
Outputs
Boolean Equations Truth Table Karnaugh Map Logic Diagram
Inputs
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State
Outputs
Boolean Equations Truth Table Karnaugh Map Logic Diagram
State Transition Controls State equations State table State diagram

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Inputs
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Typical Sequential Circuit With No Inputs
D Q
D Q
D Q
Clock
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Description by State Equations
D Q Q
D Q Q
D Q Q
A(t + 1) = B(t ) C (t ) B(t + 1) = A(t ) C (t + 1) = B(t )
Clock
A(t+1) = B(t+1) = A(t) C(t+1) = B(t)
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Description by State Table
Present State
D Q Q A D Q Q B D Q Q C
Input C 0 1 0 1 0 1 0 1 A 0 1 1 0 0 1 1 0
Next State B 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1
Output -
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Clock
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Description by State Diagram
001
D Q Q A D Q Q B D Q Q C
011 000 111
100
Clock
010
110
101
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Mealy/Moore Models
Output is a function of state only = Moore Model
State
Outputs
Inputs
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Mealy/Moore Models
Output is a function of state and inputs = Mealy Model
State
State Transition Controls Output Logic
Inputs
Outputs
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Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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Homework 6 due in Class 8

As always, show all work Problems 5-6, 5-8, 5-9
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Cpe358/Cs381 Switching Theory and Logical Design Class 6

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Cpe358/Cs381 Switching Theory and Logical Design Class 6

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CpE358/CS381 Switching Theory and Logical Design Class 6

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Characteristics of Combinatorial Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Asynchronous Sequential Circuit

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Synchronous Sequential Circuit

Storage Element(s) Clock

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Feedback Paths in Logic Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Feedback Paths in Logic Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Feedback Paths in Logic Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Feedback Paths in Logic Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Feedback Paths in Logic Circuits

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Basic Storage Element - Latches

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Basic Storage Element - Latches

Basic Storage Element - Latches

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Basic Storage Element - Latches

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Limitations of Level Sensitive Latches

A slight change in timing could product different results: D C Q

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Master D C Master Q Slave D C Slave Q Slave Q guaranteed stable

Master doesnt change while C high

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Q Positive Edge Triggered D Q

Q Negative Edge Triggered D Q

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

J-K Flip Flop

Constructing a J-K from a D J K D Q Q D

Constructing a D from a J-K J Q Q

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Toggle Flip Flop

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Immediate Inputs to Flip-Flops

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004