Class 3

CpE358/CS381 Switching Theory and Logical Design Class 3
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
Copyright 2004 Stevens Institute of Technology All rights reserved
1-85
Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Hazards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-86
Boolean Functions in Terms of Minterms

A logical function is TRUE if any of its minterms are true:
x y z x y z x y z
x y z m1
m4
x y z F(x,y,z) = (1,4,7) = x y z + x y z + x y z = m1 + m4 + m7 xyz
m7
Algebraic manipulation of the literal expression of the function is one way to minimize it, manipulation of minterms is another
www.UandiStar
1-87
Two Variable Minterm Map

Represent Boolean functions in terms of minterms in a Karnaugh map: y x m0 m1 m2 m3 x 0 1 0 y 1
xy xy xy xy
www.UandiStar
1-88

Represent Boolean functions in terms of a Karnaugh map: y x m0 m1 m2 m3 Consider the XOR function x 0 1 0 y 1
xy xy xy xy
F ( x, y ) = x y = x ' y + xy ' = m1 + m2
y x 0 x 1 1
www.UandiStar
y 0 1 1
1-89

Represent Boolean functions in terms of a Karnaugh map: y x m0 m1 m2 m3 Consider the XOR function x 0 1 0 y 1
xy xy xy xy
F ( x, y ) = x y = x ' y + xy ' = m1 + m2
y x 0 x 1 1 0 y 1 1 x x 0 1 y 0 0 1 y 1 1 0 Set the non-asserted minterms to zero
www.UandiStar
1-90
Minimizing Function of Two Variables

y x 0 x 1 0 y 1
xy xy xy xy
F ( x, y ) = xy '+ xy = m2 + m3 = = x( y '+ y ) x
x Covering adjacent minterms with a single region defines the variables needed to represent the function 0 x 1 y 0 0 1 y 1 0 1
www.UandiStar
1-91
Minimizing Function of Three Variables

yz x m0 m1 m3 m2 m4 m5 m7 m6 x y 00 01 11 10 0 xyz xyz xyz xyz 1 xyz xyz xyz xyz z Minterms are numbered in Gray code order adjacent minterms differ in only one variable If the function is asserted (i.e., TRUE) for both of these adjacent minterms, then the terms defined by those minterms do not depend on the variable that is changing between them
www.UandiStar
1-92
Three Variable Map

yz x m0 m1 m3 m2 m4 m5 m7 m6 x y 00 01 11 10 0 xyz xyz xyz xyz 1 xyz xyz xyz xyz z Consider F(x,y,z)=(1,3,7)
F ( x, y, z ) = m1 + m3 + m7 F ( x, y , z ) = x ' y ' z + x ' yz + xyz = x ' y ' z + x ' yz + x ' yz + xyz x '( y '+ y ) z + ( x '+ x) yz = =
yz x 0 x 1
xz
00 01 11 10
0 0 1 0 1 1 0 0
x ' z + yz
yz
www.UandiStar
1-93
Three Variable Map

yz x m0 m1 m3 m2 m4 m5 m7 m6 x y 00 01 11 10 0 xyz xyz xyz xyz 1 xyz xyz xyz xyz z Observations: All minterms must be covered Number of variables defining a sum term inversely proportional to number of minterms covered Number of sum terms required to define function equal to number of separate regions Maximize region size Minimize number of regions
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
yz x 0 x 1
xz
00 01 11 10
0 0 1 0 1 1 0 0
yz
www.UandiStar
1-94
Three Variable Map

For a 3-variable map: Covering 4 minterms with one 4-minterm region defines the function in terms of a single variable yz x 0 x 1 y 00 01 11 10
0 0 1 1 1 1 0 0
yz yz Covering the same 4 minterms with 2 2minterm regions defines the function in terms of two terms, each requiring two variables. x 0 x 1 y 00 01 11 10
0 0 1 1 1 1 0 0
z
yz
www.UandiStar
1-95
Three Variable Map

Adjacency sometimes exists in subtle ways: x These four minterms are obviously adjacent to each other. x 0 1 yz y 00 01 11 10
1 1 0 0 1 1 1 1
www.UandiStar
1-96
Three Variable Map

Adjacency sometimes exists in subtle ways: x These four minterms are obviously adjacent to each other. x 0 1 yz y 00 01 11 10
1 1 0 0 1 1 1 1
yz But so are these, if we consider the map to wrap around on itself x 0 x 1
y 00 01 11 10
1 1 0 0 1 1 1 1
z
www.UandiStar
1-97
Four Variable Map

yz wx
m0 m4 m12 m8 m1 m5 m13 m9 m3 m7 m15 m11 m2 m6 m14 m10
y 00 01 11 10
00 wxyz wxyz wxyz wxyz 01 wxyz wxyz wxyz wxyz 11 wxyz wxyz wxyz wxyz w 10
wxyz wxyz wxyz wxyz
z The 4-variable map extends the concept of the 2- and 3-variable map
www.UandiStar
1-98
Minimizing Four Variable Map

yz wx
m0 m4 m12 m8 m1 m5 m13 m9 m3 m7 m15 m11 m2 m6 m14 m10
y 00 01
0 1 1 0
11
1 1 1 1
10
1 0 0
00 01 11 10
1 0 0 1
w
1
z Minimize F(w,x,y,z)=(0,2,3,5,7,8,10,11,13,15) F(w,x,y,z)=xz+xz+yz xz yz xz
www.UandiStar
1-99
Five Variable Map

yz wx 00 01 11 10 00
m0 m4 m12 m8
y 01
m1 m5 m13 m9
yz 10
m2 m6 m14
y 00 01
m17 m21 m29 m25
11
m3 m7 m15 m11
wx 00 01 11 w 10
11
m19 m23 m31 m27
10
m18 m22 m30
m16 m20 m28 m24
w
m26
m10
z v=0
z v=1
5-variable map is extension of 4-variable map, adjacency must be considered between pairs of 4-variable maps
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-100
Minimizing Five Variable Map

yz wx 00 01 11 10 00
1 0 0 1
y 01
0 0 1 1
yz 10 xyz
0 0 0
y 00 01
1 0 1 1
11
0 0 1 1
wx 00 01 11 w 10
11
0 0 1 1
10
0 0 0
vxy
1 0 0 1
w
0
z v=0 wz
z v=1
Minimize F(v,w,x,y,z)=(0,8,9,11,16,17,24,25,27,29,31) F(v,w,x,y,z)=wz+xyz+vxy

www.UandiStar
Six Variable Map

yz y 00 00 01 x 11 10
m0 m4 m12 m8
yz 10
m2 m6
y 00 01
m33 m37 m45 m41
Keeping track of what minterms are adjacent becomes tedious Ensuring the maximum coverage for each term is challenging 6-variable maps usable, but perhaps the design needs to be modularized instead
wx
01
m1 m5 m13 m9
11
m3 m7 m15 m11
wx u=0 x 00 01 11 w 10
11
m35 m39 m47 m43
10
m34 m38 m46 m42
m32 m36 m44 m40
m14 m10
z v=0 yz wx 00 01 x 11 10
m12 m8 m13 m9 m15 m11 m14 m10
z v=1 y yz 10
m2 m6
y 00 01
m49 m53 m61 m57
00
m0 m4
01
m1 m5
11
m3 m7
wx u=1 00 01 x 11 w 10
11
m51 m55 m63 m59
10
m50 m54 m62 m58
m48 m52 m60 m56
z
z www.UandiStar
1-102
Product of Sums Covering 0s Instead of 1s

A function of N variables, F(v1,v2,,vN) , can be represented by a Karnaugh map with 2N cells. (v1,v2,,vN) = (0,0,0), (0,1,0), , (1,1,,1) F( ), and its Karnaugh map have K minterms (1s) and 2N-K maxterms (0s) If K > 2N-K, it might be easier to cover the maxterms rather than the minterms. E.g.:
yz wx 00 01 11 10 00 1 0 1 1 01 1 1 1 0 v=0 11 1 1 1 1 10 0 1 1 1 wx 00 01 11 10 yz 00 1 0 1 1 01 1 0 1 0 v=1 11 1 1 1 1 10 0 1 1 1
www.UandiStar
1-103
Product of Sums Covering 0s Instead of 1s
yz wx 00 01 11 10 00 1 0 1 1 01 1 1 1 0 v=0 11 1 1 1 1 10 0 1 1 1 wx 00 01 11 10
yz 00 1 0 1 1 01 1 0 1 0 v=1 11 1 1 1 1 10 0 1 1 1 wx
yz 00 00 01 11 10 1 0 1 1 01 1 1 1 0 v=0 11 1 1 1 1 10 0 1 1 1 wx 00 01 11 10
yz 00 1 0 1 1 01 1 0 1 0 v=1 11 1 1 1 1 10 0 1 1 1
F(v,w,x,y,z) has 4 terms F(v,w,x,y,z) = wxyz + wxyz + vwxy +wxyz
F(v,w,x,y,z) has 7 terms F(v,w,x,y,z) = wxy + yz + vxz + xy + wx + wyz + wy
www.UandiStar
1-104
Dont Care Conditions

Sometimes, not all possible output values are specified in system design, e.g.:
b
w=8
Calculator, Clock, or Counter Circuit
x=4 y=2 z=1
a g f e
c 0 d 1 2 3 4
BCD data
7 segment LCD
Consider the horizontal line in the middle of the display (segment g): Fg(w,x,y,z)=(2,3,4,5,6,8,9), but we dont care what happens to minterms 10, 11, 12, 13, 14, or 15, since the display will not be sent those states
www.UandiStar
1-105
Dont Care Conditions

wx\yz 00 01 11 10 00 0 1 X 1 01 0 1 X 1 11 1 0 X X 10 1 1 X X wx\yz 00 01 11 10 00 0 1 X 1 01 0 1 X 1 11 1 0 X X 10 1 1 X X
F(w,x,y,z) = xy + xz + xy + w
F(w,x,y,z) = wxy + xyz
We are free to assign whatever values we want to for minterms 10, 11, 12, 13, 14, and 15. Assign them a value X to indicate they may be covered, or not, whichever results in the simplest expression
www.UandiStar
1-106
Logical Completeness
1. AND, OR, NOT can implement any Boolean function They form a Logically Complete set of operators
www.UandiStar
1-107
1. 2. AND, OR, NOT can implement any Boolean function They form a Logically Complete set of operators NAND can implement AND and NOT directly: NOT =
AND
www.UandiStar
1-108
1. 2. AND, OR, NOT can implement any Boolean function They form a Logically Complete set of operators NAND can implement AND and NOT directly: NOT =
AND
3.
NAND can implement OR by DeMorgans Law: = =
NAND is logically complete (so is NOR)

www.UandiStar
1-109
NAND Implementation of Sum of Products

Consider an arbitrary Sum of Products:
mA
(A,B,C)
mB
mC
www.UandiStar
1-110

Consider an arbitrary Sum of Products: Add inversions at each term. This is allowed, since (x)=x
mA
(A,B,C)
mB
mC
www.UandiStar
1-111

Consider an arbitrary Sum of Products: Add inversions at each term. This is allowed, since (x)=x Convert output gate by DeMorgans Law:
mA
(A,B,C)
mB
mC
www.UandiStar
1-112
Wired-AND and Open Collector

Typical TTL totem-pole output circuit: +V +V
I1 out I0
I1 out I0
TTL with Open Collector output circuit

www.UandiStar
1-113
Wired-AND and Open Collector

Each gate asserts 0-output with no pull-up transistor, no gate can cause output to become 1. External pull-up resistor needed Used for wiring multiple devices together on bus, but speed is limited +V +V +V +V Pull-up resistor
www.UandiStar
1-114
XOR Function
y Exclusive OR (XOR)
0 1
x
0 0 1 1 1 0
x y = x 'i y + x i y '
x y
x y y
x y
w x y z = ((w x ) y ) z = (w x ) ( y z )
XOR applications: Addition, parity, data scramblers, encryption, shift register sequences
www.UandiStar
N-input XOR
w x y z = ((w x ) y ) z = (w x ) ( y z )
These three designs are all logically equivalent (for static signals)
www.UandiStar
1-116
Hard To Minimize Functions

Consider this map:
wx 00 01 11 10 yz 00 1 0 1 1 01 0 1 0 0 v=0 11 1 0 1 1 10 0 1 0 1 wx 00 01 11 10 yz 00 0 1 0 1 01 1 0 1 0 v=1 11 0 1 0 1 10 1 0 1 1
Isolated minterms cannot be grouped
www.UandiStar
1-117

Consider this map:
wx 00 yz 00 1 0 1 1 01 0 1 0 0 v=0 11 1 0 1 1 10 0 1 0 1 wx 00 01 11 10 yz 00 0 1 0 1 01 1 0 1 0 v=1 11 0 1 0 1 10 1 0 1 1
Cover part of the map with XOR Treat the rest normally
01 11 10
F (v , w , x, y , z ) = (wx ')'i(v w x y z ) + wx ' y ' z '+ wx ' y
www.UandiStar
1-118

Consider this map:
wx 00 yz 00 1 0 1 1 01 0 1 0 0 v=0 11 1 0 1 1 10 0 1 0 1 wx 00 01 11 10 yz 00 0 1 0 1 01 1 0 1 0 v=1 11 0 1 0 1 10 1 0 1 1
Cover part of the map with XOR Treat the rest normally
01 11 10
F (v , w , x, y , z ) = (wx ')'i(v w x y z ) + wx ' y ' z '+ wx ' y
www.UandiStar
1-119
Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Hazards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-120
Homework 3 due in Class 5

As always, show all work: Problems 3-5, 3-7, 3-18. Design a BCD to seven segment decoder for any 2 of the 6 segments (a-f) we did not discuss in class.
www.UandiStar
1-121

Class 3

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Class 3

Загружено:

Авторское право:

Доступные форматы

CpE358/CS381 Switching Theory and Logical Design Class 3

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Boolean Functions in Terms of Minterms

x y z F(x,y,z) = (1,4,7) = x y z + x y z + x y z = m1 + m4 + m7 xyz

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Two Variable Minterm Map

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Two Variable Minterm Map

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Two Variable Minterm Map

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Minimizing Function of Two Variables

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Minimizing Function of Three Variables

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Three Variable Map

Three Variable Map

Three Variable Map

Three Variable Map

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Three Variable Map

yz But so are these, if we consider the map to wrap around on itself x 0 x 1

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Four Variable Map

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Minimizing Four Variable Map

z Minimize F(w,x,y,z)=(0,2,3,5,7,8,10,11,13,15) F(w,x,y,z)=xz+xz+yz xz yz xz

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Five Variable Map

m16 m20 m28 m24

Minimizing Five Variable Map

Minimize F(v,w,x,y,z)=(0,8,9,11,16,17,24,25,27,29,31) F(v,w,x,y,z)=wz+xyz+vxy

Six Variable Map

m32 m36 m44 m40

m48 m52 m60 m56

Product of Sums Covering 0s Instead of 1s

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Product of Sums Covering 0s Instead of 1s

F(v,w,x,y,z) has 4 terms F(v,w,x,y,z) = wxyz + wxyz + vwxy +wxyz

F(v,w,x,y,z) has 7 terms F(v,w,x,y,z) = wxy + yz + vxz + xy + wx + wyz + wy

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Dont Care Conditions

Calculator, Clock, or Counter Circuit

x=4 y=2 z=1

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Dont Care Conditions

F(w,x,y,z) = wxy + xyz

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004