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CMOS Layers
n-well process p-well process Twin-tub process
n-well process
Gate NMOS NMOS FOX PMOS PMOS
n+
n+
n+
n+
p+
p+
p+
p+
n-well p-substrate
Layer Types
p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide
Insulated glass Provide electrical isolation
n+
n+
n+
n+
p+
p+
p+
p+
n-well
Stick Diagrams
Stick Diagrams
N+
N+
Stick Diagrams
Objectives:
To know what is meant by stick diagram. To understand the capabilities and limitations of stick diagram. To learn how to draw stick diagrams for a given MOS circuit.
Outcome:
At the end of this module the students will be able draw the stick diagram for simple MOS circuits.
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Stick Diagrams
VDD VDD
X
X
Stick Diagra m
X Gnd
Gnd
Stick Diagrams
VDD X X X VDD
X Gnd
Gnd
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Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout.
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Stick Diagrams
Does show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing
Stick Diagrams
Does not show
Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries. Any other low level details such as parasitics..
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pdiff
Can also draw in shades of gray/line style.
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Stick Diagram
Stick diagrams are a design technique that represent the layout for a device
diffusion (device well, local interconnect) polysilicon (gate electrode, interconnect) metal (contact, interconnect) contact windows N well (CMOS devices) This colour representation is used during mask layer definition Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward
to two transistors
Notice that Poly and Metal 1 can overlap Avoid routing signals that are side by side for long lengths. This adds capacitance to the device. Avoid all interconnect overlap if possible. This adds capacitance to the device. Strive for simplicity. This will later provide the smallest and fastest devices. You can use Poly, Metal 2 (M2), and even Active to interconnect your device. But keep in mind, Poly and especially Active adds resistance to you device.
Make VDD and GND horizontal and have them stretch from the left to the right of the cells. This allows the cells to be abutted top to bottom or side by side by overlaying the power lines. It will be helpful to make all of your cells the same height (distance between power and ground) so they will line up better when they are abutted.
Keep your inputs and outputs inside the cell, and try to keep them on M1.
M2 should be reserved for your select lines and clock. Data should flow in metal1 horizontally, and control should flow in M2
vertically. Clearly there will be times that this rule must be broken, but it will
save a lot of confusion and hassle if you do all you can to follow this advice.
Use minimum Active. Fully use as much contact area as you have (unless you have a really good reason not to). Some of the Active contacts below are minimum size while they could clearly be larger!
Where possible avoid crossing nets. In other words, don't take a M1 line, change to M2, cross M1, change back to M1 and so on. It is a big space waste to do this. Plan ahead and route the signals in a way where this is avoid as often as possible.
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Lambda-based Rules
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Design Rules
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Design Rules
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Design Rules
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Power
Out
C B
Ground
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Euler Path
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Euler Path
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NOR Gate
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Example
Power
Out
C B
Ground
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