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The Half-Bridge Circuit Revealed

by Bo do s Po wer Systems

Confirm zero-voltage switching during all operating conditions

The half-bridge or totem-pole configuration is one of the most common switch circuit topologies used in power electronics today. It is used in various applications such as synchronous buck converters, resonant converters, electronic ballasts, induction heating and motion control, and offers such benefits as four-quadrant switching, zero-voltage switching (ZVS), zero-current switching (ZCS), high-frequency operation, low EMI and high efficiency. By Tom Ribarich, International Rectifier, Director, Lighting Systems and Applications

As simple as this switch conf iguration appears, it is actually deceptively simple. Much care should be taken during the design of the half -bridge and drive circuitry to avoid many hidden pitf alls. T his article provides a short review of the half -bridge and how it works, illustrates proper gate drive circuits and layout techniques, and describes various circuit pitf alls and how to avoid them.

The Half -Bridge Circuit

T he half -bridge circuit consists of an upper and lower switch (typically MOSFETs) connected in a cascode arrangement (Figure 1). T his 5- terminal circuit includes a DC bus voltage input (1), a mid-point between the two switches (2), a ground return (3), a low-side gate drive input (4) and a high-side gate drive input (5). T he input, output and Miller capacitances, as well as the anti-parallel diodes, of each switch are also included in the circuit and are important f or understanding the half -bridge f unctionality.

T he two switches are turned on and of f complementary to each other (and with a non-overlapping deadtime) by applying the correct voltage wavef orms at each of the gate drive inputs. T he result is a squarewave voltage at the mid-point that switches between the DC bus voltage and ground (Figure 2). With a series R-C-L load connected between the mid-point and ground, an AC current is produced in the load circuit as the square-wave at the mid-point oscillates up and down. A portion of this AC current f lows in each of the half -bridge switches, depending on which switch is on or of f . T he voltage and current wavef orms can be divided up into the f ollowing f our time zones.

Z one I: T he upper switch turns on and the mid-point is connected to the DC bus voltage. Current f lows f rom the (+) side of the DC bus capacitor, through the upper switch, through the R-C-L load, and back to

the (-) ground return path. T he current ramps up to a positive peak level during the on-time of the upper switch. Z one II: T he upper switch turns of f and both switches remain of f during this short dead-time. T he load current continues to f low out of the mid-point node. Half of the load current f lows out of the top of the lower switch output capacitance (CDS2), and the other half f lows out of the bottom of the upper switch output capacitance (CDS1). T his causes the mid-point voltage to slew down to ground at a given dv/dt rate determined by the total capacitance at the mid-point and the instantaneous load current. T he mid-point voltage reaches ground and continues to go negative until it gets limited by the internal antiparallel diode (D2) of the lower MOSFET (S2). T his diode, also known as the f ree-wheeling diode, allows the R-C-L current to f low in the negative direction while the switches are of f . Z one III: T he dead-time ends and the lower switch turns on. Because the mid-point voltage is at ground, zero-voltage switching (Z VS) occurs when the lower switch turns on. Current continues to f low through the channel of lower MOSFET (instead of the diode due to the lower resistance of the channel) and through the R-C-L circuit. T he current crosses zero and continues to ramp down to a negative peak level during the on-time of the lower switch. No current f lows through the DC bus capacitor during this time. Z one IV: T he lower switch turns of f and both switches remain of f again during this deadtime. T he load current continues to f low into the mid-point node and is equally split between both output capacitances (CDS1 and CDS2). T he mid-point voltage slews up at a dv/dt rate determined by the total midpoint capacitance and the instantaneous load current. T he mid-point voltage gets limited by the DC bus voltage plus the diode drop of the internal anti-parallel diode (D1) of the upper MOSFET (S1). T he current continues to f low through this diode until the upper switch is turned on again at the start of Z one I. Because the mid-point voltage is at the DC bus voltage at the end of Z one IV, zero-voltage switching (Z VS) is achieved when the upper switch is turned on again at the beginning of Z one I. In order to maintain Z VS across both switches, it is necessary that the mid-point voltage leads the load current during each switching cycle. T his ensures that the mid-point voltage properly slews to the opposite rail during each dead-time. If the mid-point voltage is in-phase or lags the load current, then mid-point voltage will not slew to the opposite rail during the dead-time and hardswitching will occur (Figure 3). A large spike of current will occur at the turn-on of each switch as the mid-point capacitance is instantly charged or discharged. T his gives high switching losses and can cause the switches to thermally destruct.

When Z VS is achieved in this resonant application, switching losses and EMI are signif icantly reduced. T he reduced switching losses then allows f or higher switching speeds f or reducing the size of the magnetics. T he f our-quadrant operation of the half bridge also allows f or the load current to f low in the positive and negative directions without interruption.

Gat e Drive Circuit s

T he half -bridge requires a low-side gate drive circuit (ref erenced to ground) f or turning the lower MOSFET on and of f , and requires a f loating high-side driver (ref erenced to the mid-point) f or turning the upper MOSFET on and of f (Figure 4). T he type of gate drive circuit used depends on the input and Miller

capacitances of the MOSFET, the switching f requency, and the half -bridge current amplitude. If the current is low (<500mA) and the switching f requency is low (<100kHz), then a standard 600V, high and low-side gate driver IC (such as the IRS2101) and series gate resistors (RG1, RG2) are usually suf f icient. If the half bridge current is higher (1A), then it is desirable to turn of f each MOSFET quickly to minimize switching losses at turn-of f . Usually the higher half -bridge currents require larger MOSFETs with larger parasitic capacitances. In this case, an anti-parallel diode (DG1) is placed in parallel to the gate resistor to discharge the gate capacitance quickly during turn-of f . However, care must be taken f or the current that f lows through the Miller capacitance and back into the gate driver IC when the mid-point voltage slews to the opposite rail during each dead-time. An additional smaller resistor (RG3) should be placed in series with the anti-parallel diode to limit high Miller currents f rom causing latch-up inside the gate driver IC. Also, the RDSon of the sink current gate driver switch becomes critical and can cause a voltage of f set to occur due to the Miller current that can momentarily turn the MOSFET back on. An external PNP transistor (Figure 4) can be used instead of a diode to increase the sink current capability of the gate drive circuit, or, a gate drive IC with larger I/O current capability can be used (such as IRS21856). At higher f requencies (<500kHz), the switching losses at turn-of f increase, as well as the internal losses of the gate drive switches and level-shif ting losses when turning the high-side MOSFET on and of f . A gate driver IC that is specif ically designed f or higher f requencies and higher gate drive currents is typically required (such as IRS2795).

PCB Layout
T he pcb layout is a critical piece of the overall design and needs to be properly designed f or good robustness. A poor layout can cause reliability issues that go undetected until the product reaches high volume manuf acturing or is working in the f ield. T he half -bridge midpoint is a major source of noise in the circuit as it oscillates between ground and the DC bus voltage at a given f requency. T his node should theref ore be kept as f ar away as possible f rom any critical low-voltage control or sensing circuits to avoid noise coupling due to parasitic pcb capacitances. T he IC and small-signal component grounds should all be connected together and then connected to the power ground trace at a single point only (do not run power ground through the small-signal ground!). Multiple connections f rom the ground pads of the small-signal components to the power ground add invisible parasitic inductors into the control circuit that cause unwanted noise spikes each time high currents f low in the power ground. T hese spikes can cause f aulty switching, jittering, or electrical over-stress across components or at the pins of ICs. For the gate drive, the half -bridge MOSFETs should be placed as close as possible to the gate drive circuits to reduce any possible parasitic inductance. Each time the MOSFETs are turned on or of f , this network of parasitic inductors and MOSFET capacitances can cause ringing at the gates that can swing below ground or above VCC. T his can then cause high currents to f low in or out of the gate drive pins of the IC and result in destruction due to latch-up. For higher current applications, it is good practice to add additional zener diodes f rom the gate to the source of each switch. T his will help limit the voltage f rom swinging too f ar below ground or above VCC. A typical half -bridge layout using SMT components f or the schematic in Figure

4 is shown in Figure 5 to help illustrate good pcb techniques.

Conclusion
T he half -bridge circuit is an elegant solution f or many switched-mode applications that of f ers many benef its. But these benef its are realizable only when the half -bridge circuit, the gate drive circuit, and layout, are all properly designed. T he half -bridge mid-point voltage and current wavef orms should be checked caref ully to conf irm that Z VS is maintained during all operating conditions. Partial or hard-switching can give high switching losses and cause the switches to overheat and thermally destruct. T he gate drive circuit should be properly designed so that it is suitable f or the size of the MOSFET being driven, the amplitude of the half bridge current, and the operating f requency. Finally, much care should be taken during the design of the layout to avoid long gate drive loops or poor grounding that can cause IC latch-up, EMI, or f aulty switching.

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