WEEK 10-2013

Exceptions and interrupts

ELEC2142: Embedded Systems Design

Overview
Definitions Hardware interrupts and error conditions Exception modes Vector table Exception handlers SWI Interrupts IRQ and FIQ Vector interrupt controller A complete structure for handlers

Definitions
Exception is an event that requires the CPU to perform an action breaking the normal flow of a program.
Benign events like someone moving a mouse or pushing a button Catastrophic faults such as bus error

Exceptions should be anticipated to help find the cause of the problem during application development or to plan for graceful shutdown. Exceptions can be categorized into two large classes: interrupts and error conditions Interrupts are exceptions raised asynchronously by I/O devices so that they can be served by the CPU. Software Interrupt is an exception that can be raised within the application using SWI instruction. It is a user defined synchronous exception.
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Hardware Interrupts (I/O)

An interrupt is an efficient way that I/O ( peripheral) devices use to get the attention of the microprocessor. There are two external interrupt lines that are connected to the control unit of the CPU. They are a low priority interrupt (IRQ) and a high priority interrupt called FIQ I/O interrupts are asynchronous More information needs to be conveyed An I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction

Hardware Interrupts

External lines for I/O Interrupt

ERROR CONDITIONS
Error exceptions occur quite often in an embedded system. So often that software needs to be sufficiently robust to handle them. Undefined instruction
Floating-point instructions and emulate them in software.

Data aborts
occurs when the processor attempts to grab data in memory that does not physically exist occurs when the processor attempts to write data in read only memory region

Prefetch abort
occurs when the processor attempts to grab an instruction from a memory and something goes wrong
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Exception sources in ARM

Reset: Occurs when the processor reset pin is asserted. (Signalling power-up)
Undefined Instruction: Occurs if the processor, does not recognize the currently executing instruction. Software Interrupt (SWI): This is a user-defined intentional synchronous interrupt instruction.

Prefetch Abort: Occurs when the processor attempts to execute an instruction that was not fetched, because the address was illegal.
Data Abort: Occurs when a data transfer instruction attempts to load or store data at an illegal address. IRQ: Occurs when the processor external Interrupt ReQuest pin is asserted FIQ: Occurs when the processor external Fast Interrupt reQuest pin is asserted

ARM modes of operation

10000 User 10001 FIQ 10010 IRQ 10011 SVC 10111 Abort 11011 Undef 11111 System Non-Privileged Normal user code Mode Processing fast interrupts Processing standard interrupts Processing software interrupts (SWIs) Processing memory faults Handling undefined instruction traps Running privileged operating system tasks

Privileged Modes
CPSR
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CPSR Encoding for exception modes

CPSR
mode T Mode of Operation ARM vs Thumb State

F I NZCV

FIQ Fast interrupts Disable bit IRQ Normal interrupt Disable bit Condition Flags

Changing mode bits is only possible in privileged modes

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User modes versus privileged modes

User Applications run in User Mode Privileged modes, used to service interrupts exceptions access protected resources (via SWI Instruction)

Privileged modes User mode OK

User mode Privileged modes NOT OK Only possible through Controlled mechanisms: SWI, Exceptions, Interrupts
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ARM modes and Registers

Each mode has some set of registers that swap in and replace normal registers

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Switching between modes (User to FIQ)

Registers in use User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr
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Registers in use
FIQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) cpsr
spsr_fiq

EXCEPTION r8 r8_fiq r9 r9_fiq r10_fiq r10 r11 r11_fiq r12_fiq r12 r13_fiq r13 (sp) r14_fiq r14 (lr) Return address calculated from User mode PC value and stored in FIQ mode LR
spsr_fiq

User mode CPSR copied to FIQ mode SPSR

Processor exception sequence

When exception occurs, the ARM7TDMI processor has a defined sequence of events to start the handling and recovery of exception. Except a reset exception, in all cases, the current instruction is allowed to complete. Exception handling sequences are The CPSR is copied into SPSR_<mode>, where <mode> is a new mode to which the processor is about to change. The appropriate CPSR bits are set. The core will switch to ARM state if it was in THUMB state The core will also change to the new exception mode, setting the least significant bits in CPSR register. 13

Processor exception sequence

The core will switch to ARM state if it was in THUMB state The core will also change to the new exception mode, setting the least significant bits in CPSR register. IRQ interrupts are disabled automatically on entry to all exceptions. FIQ interrupts are disabled on entry to reset and FIQ exceptions. The program counter changes to the appropriate vector address in memory. This forces the processor to branch into an exception handler.

Note that the processor is responsible for the above actions- no code needs to be written
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Processor exception sequence

Once the handler completes, the processor should return to the main code. The following actions must be done by the software handler:
The CPSR must be restored from SPSR_<mode>, where <mode> is the exception mode that the processor is currently in The PC must be restored from LR_<mode>

The above actions can only be done in ARM state, and fortunately, the software can usually do these two operations with a single instruction at the end of the handler. MOVS PC, lr or SUBS PC, lr, #4
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Processor exception sequence

Adding the S flag (update condition codes) to a data processing instruction when in a privileged mode with the PC as the destination register, also transfers the SPSR to CPSR Same thing for Load Multiple instruction (using the ^ qualifier) LDMFD sp!, {r0-r12, PC}^

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The Vector Table

The Program counter will be loaded with one of the following vector address depending on the particular exception occurred
0x1C 0x18 0x14 0x10 0x0C 0x08 FIQ IRQ (Reserved) Data Abort

Prefetch Abort Software interrupt Undefined instruction Reset

In the vector address, ARM uses actual instructions, often a change-of flow instruction types.

0x04 0x00
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The Vector Table

0xFFFFFFFF
0x30080000 0x30000000 >32MB 0x2000000 Undef handler SWI handler IRQ handler 0x3008000 FIQ handler Undefined handler outside 32MB branch instruction range SWI exception handler placed appropriate address boundary IRQ handler within 32MB branch instruction range

0x1000 < 4KB

0xFFC

Literal pool containing address of undef handler FIQ handler follows vector table

0x18
0x14 0x10 0x0C 0x08 0x04 18 0x00

B IRQ_handler
(Reserved)

Data Abort
Prefetch Abort MOV PC,#0x30000000 LDR PC, [PC,#0xFF0] Reset

The Vector Table

For each type of exception, there is usually a dedicated block of code, called an exception handler, that is responsible for acknowledging an exception condition and fixing it. The vector table contains change-of-flow instructions that forces the processor to begin fetching instructions from its handler. The change -of-flow instructions can be one of the followings:
Branch instruction use B instruction to jump to exception handler that is within 32MB range. MOV instruction A MOV instruction can change the PC simply by loading the register with a value LDR instruction The address cab be stored in memory and accessed by using an offset to the program counter. The instruction would have the form

LDR PC, [PC, #offset]

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The Vector Table

The last exception vector, FIQ vector, contains the first instruction of the handler. This allows FIQ interrupts to be serviced immediately by spending as little time as possible getting to the handler.
No branch is needed The FIQ handler is executed as the program counter increments through memory

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Exception Handlers
When an exception occurs, the processor responds
by saving CPSR into SPSR_<mode> by modifying the appropriate bits of the CPSR ( mode change) by saving the return address to LR_<mode> by loading the PC with the appropriate vector address in memory

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All the above tasks are done by the processor, the focus for the programmer is to write the appropriate exception handler. Once the mode of the processor has been changed, the exception handler will have to access its own stack pointer, link register, and SPSR. Although there are some general purpose registers that can be used only by the handler, it is important to save off other registers that are common to previous mode to a stack before using them. STMFD SP!, {r0-r12, lr}

Exception Handlers
This process of storing registers on the stack can introduce unacceptable delay depending on the type of exception. To reduce such delay, FIQ mode has five additional general registers that the FIQ handler can access to. At the end of all handlers, the programmer is responsible for storing the state of the machine and returning back to the original instruction stream before the exception. This is done through an atomic operation, where the contents of SPSR are stored back into the CPSR while moving the Link register into the program counter. The instructions to do the atomic operation exist only in the ARM instruction set, that is why the processor had to switch from THUMB to ARM if it was executing THUMB code.
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Exception Priorities
When multiple exceptions occur at the same time, the processor should know which one to attend first.
Suppose A/D converter has asserted IRQ line and at the same time the processor tries to access a memory location that is undefined while another high-priority interrupt tries to tell the processor that we are about to lose power in two minutes
Exception priorities
Priority Exception comment

Highest

Reset Data Abort FIQ IRQ Prefetch Abort SWI

Handler usually branches straight to main routine Can sometimes be helped with MMU Current instruction completes, then the interrupt is acknowledged Current instruction completes, then interrupt is acknowledged. Can sometimes be helped with hardware (MMU) Execution of the instruction causes the exception
SWI and Undef are actually exclusive, so they have the same priority

Lowest

Undefined instruction

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Exception Priorities
In the above scenario, the data abort will be handled first, followed by the FIQ interrupt alerting the system to a power failure, and then the A/D converter will have its turn. Placing the Data Abort exception above the FIQ exception in the priority list ensures that the Data Abort is actually registered before the FIQ is handled. The Data Abort handler is entered first but control is then passed immediately to the FIQ handler. Once the FIQ has been handled, control returns to the Data Abort Handler. This means that the data transfer error does not escape detection as it would if the FIQ were handled first.

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Exception Priorities
What if an exception occurs while the processor is handling an exception?
For example, data abort occurs while the processor is executing FIQ handler. In this case, the processor will attend to data abort first suspending FIQ handler. Once it has handled the data abort, the processor will resume FIQ handler from where it left off. Before jumping to the data abort handler, the processor will save the CPSR onto SPSR_<data abort>, modify the CPSR bits, save the return address on LR_<data abort> For example, another FIQ occurs while the processor is executing FIQ handler. In this case, the processor will block the new FIQ as FIQ interrupts are automatically disabled by the processor upon entry to FIQ mode.
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Reset
Reset occurs when power is first connected to the CPU or when a reset switch is operated. Reset causes the program counter to be set to zero, receives its first instruction, which is usually a branch, interrupts are disabled and the CPU is in supervisor mode; CPSR bits F and I are set to 1, T is set to 0 indicating ARM mode. The branch instruction takes the reset to the first instruction of the reset handler, where initialization of the processor or micorcontroller is started.
Initialize the memory system. Initialize all required processor mode stacks and registers. Initialize any critical I/O devices Initialize any peripheral registers, control registers, or clocks such as PLL Enable interrupts Change processor mode and/or state
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Software interrupts (SWI)

SWIs occurs when a program executes SWI instruction with syntax SWI{<cond>} <immediate_24> Binary code format for the instruction is

The instruction will raise an exception and forces the processor to go into a supervisor mode. The 24-bit immediate value is not used by the CPU; however, the programmer may use the 24-bit value to devise a system of a multiple software interrupts each leading to a different set of actions.
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Software interrupts (SWI)

How does the programmer access the 24 bit immediate value in SWI instruction? R14_svc will hold the return address once the exception (SWI) occurs. This address is four bytes a head of the SWI instruction and the 32-bit binary code for SWI may loaded into a destination register, rd , using LDR rd, [lr,#-4] The 24 immediate bit can be extracted through bits manipulation instruction such as BIC rd, rd, #0xFF000000 For efficient coding, a jump table may be used to select a particular action
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Software interrupts (SWI)

swi_cases EQU 4 swi_handler ldr ip, [lr, #-4] ; load 32-bit binary code for swi into ip bic ip, ip, #0xFF000000 ; extract the 24-bit immediate cmp ip, #swi_cases ; check if the 24-bit immediate is within range ldrlo pc, [pc, ip, lsl #2] ; If it is, jump to code pointed by the value PC + 4*IP b swi_outofrange ; otherwise, jump to error handler swi_jump_table DCD swi_c0, swi_c1, swi_c2,swi_c3 swi_c0 ; handler for case 0 b swi_exit swi_c1 ; handler for case 1 b swi_exit swi_outofrange mov ro, #0 ; throw error to user swi_exit movs pc, lr ; return from the handler 29

Software interrupts (SWI)

Uses of SWI
Allows application to use hardware facilities through operating system swi instruction: invoke the OS code (Go to 0x00000008, change to privileged mode) By software convention, number xxx in swi xxx has system service requested: OS performs request In some ARM systems, the following routine is used to send character in the bottom byte of r0 to the user display device:

SWI_WriteC EQU 0x0 MOV r0, # A ; move ASCII code for character A into ro SWI SWI_WriteC ; output character in r0
The following call returns control from a user program back to the monitor program SWI_Exit EQU 0x11 SWI SWI_Exit ; finish
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Software interrupts (SWI)

System loads user program into memory and gives it use of the processor Switch back
swi request service I/O User
Proc Mem

System
I/O Bus

status reg. data reg.

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Software interrupts (SWI)

Uses of SWI
To implement the semihosting functions: semihosting allows a program under development to use the computer running the development system as a terminal providing input and output for the target while performing debugging tasks. ARM development systems such as ADS and RealView have semihosting functionality vision tools do not support semihosting
Sequences of Code Action

MOV r0, #0x03 LDR r1, =address SWI 0x123456

MOV r0, #0x07 LDR r1, =0x0 SWI 0x123456 MOV r0, #0x18 LDR r1, =0x20026 SWI 0x123456 32

causes the 8-bit value stored in the memory location stored in r1 to be sent to the host and the corresponding character is shown in the display window
causes the ARM program to wait until the semihosting window is active and a key is pressed on the host keyboard. The corresponding character to the key is returned in r0. The program uses the code to indicate that it has finished running to the host computer.

Software interrupts (SWI)

Uses of SWI
To support run time fault detection and reporting For example, if a program includes division operations, run time fault detection may be included to detect attempts to divide by zero. The SWI handler can output a message indicating the fault and where it occurred. The handler may either terminate the program or wait for the user to indicate the next action. A simple method of performing this divison by zero detection in a division subroutine is to include the sequence below immediately after the STMFD instruction at the start of the division subroutine MOVS rX, rX ; check divisor held in rX SWIEQ <value> ; if divisor zero cause exception The exception handler can determine the position of the fault because the user r14 register will hold the address of the division call instruction. The SWI operand value can be used as a code number to identify the problem

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CPSR and SPSR Transfer Instructions

The MRS instruction moves the value of the CPSR or the SPSR of the current mode into a general-purpose register
syntax: MRS {<cond>} Rd, CPSR MRS {<cond>} Rd, SPSR Binary format for MRS
31 28 27 26 2524 23 22 21 20 19 16 15 12 11 87 0

cond

0 0 0 1 0 R 0 0 1 1 1 1 Rd

000000000000

For CPSR, R = 0. For SPSR, R = 1.

CPSR
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CPSR and SPSR Transfer Instructions

The MSR instruction transfers the value of the generalpurpose register to the CPSR or the SPSR of the current mode. This is used to update the value of the condition code flags, interrupt enables, or the processor mode. The MSR also moves the value of the 32-bit immediate to the CPSR or the SPSR.
syntax: MSR {<cond>} CPSR_f, #32bit immediate MSR {<cond>} CPSR_<fields>, Rm MSR {<cond>} SPSR_f, #32bit immediate MSR {<cond>} SPSR_<fields>, Rm

Binary formats for MSR ( immediate)

31 28 27 26 2524 23 22 21 20 19 16 15 12 11 87 0

cond
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0 0 0 1 0 R 0 0 fields 1111 rot_im 8_bit_imme

CPSR and SPSR Transfer Instructions

Binary format for MSR ( register)
31 28 27 26 2524 23 22 21 20 19 16 15 12 11 4 3 0

cond

0 0 0 1 0 R 0 0 fields 1111 0 0 0 0 0 0 0 0 Rm

R = 0 for CPSR R = 1 for SPSR Condition code for <fields> is one of

_c _x _s _f sets bit[16]- control field mask bit CPSR or SPSR [7:0] sets bit [17]- extension field mask bit CPSR or SPSR [15:8] sets bit [18]- the status field mask bit CPSR or SPSR [23:16] sets bit [19] the flags field mask bit CPSR or SPSR [31:24]

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Modifying CPSR
Unused reserved bits, may be used in future, therefore: they must be preserved when altering PSR the value they return must not be relied upon when testing other bits. Thus read-modify-write strategy must be followed when modifying any PSR: Transfer PSR to register using MRS Modify relevant bits Transfer updated value back to PSR using MSR Example: Change mode to supervisor MRS a1, CPSR BIC a1, a1,#0x1F ORR a1, a1, #0x13 MSR CPSR, a1 Note: In User Mode, all bits can be read but only the flag bits can be written to.

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Interrupts
Hardware and software interrupts are handled by OS (Operating System)

Responsibilities leading to OS (Operating System)

The I/O system is shared by multiple programs using the processor Low-level control of I/O devices is complex because requires managing a set of concurrent events and because requirements for correct device control are often very detailed I/O systems often use interrupts to communicate information about I/O operations Would like I/O services for all user programs under safe control
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Interrupts
Functions provided by OS (Operating System)
OS guarantees that users program accesses only the portions of I/O device to which user has rights (e.g., file access) OS provides abstractions for accessing devices by supplying routines that handle low-level device operations OS handles the interrupts generated by I/O devices (and other exceptions generated by a program) OS tries to provide equitable access to the shared I/O resources, as well as schedule accesses in order to enhance system performance

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Interrupts
How to turn off interrupts during Exception routine? Bits in CPSR determines whether or not interrupts disabled: Interrupt Request bit (I) (1 disabled, 0 enabled) Once an exception occurs (I) bit sets to 1 automatically Return from exception restores the original value Fast Interrupt Request bit (F) only gets disabled if a fast Interrupt occurs How to prevent user program from turning off interrupts (forever)? Interrupt Request bit (I) and Fast Interrupt Request bit (F) bits can only be changed from the privileged modes

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Interrupts
Preempting exceptions by interrupts? Suppose were dealing with a computer running a nuclear facility. What of were handling a floating-point divide by 0 exception and a nuclear meltdown imminent interrupt comes in? We need to categorize and allow some interrupts preempt other exceptions so we can handle them in order of urgency: emergency vs luxury

ARM Architecture Support to simplify software: An Exception Process sets IRQ bits (disables it). No further IRQ interrupt is possible However, No exception can disable FIQ interrupt

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Interrupts
If an FIQ interrupt comes while servicing an exception Take FIQ immediately Return to interrupted exception code as soon as no more FIQ Interrupt State information for the preempted exception are saved on banked registers and as well as some internal registers All exceptions set IRQ disable interrupt bit (I) FIQ can interrupt IRQ and other exceptions How allow IRQ interrupts to interrupt other exceptions (other than IRQ and FIQ exceptions)? Interrupt service Routine needs to save: all registers that it is going to use on IRQ Mode Stack Reset the IRQ disable bit
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 ARM cores have two interrupt lines one for a fast interrupt (FIQ) and one for a low-priority interrupt (IRQ) Two interrupt request signals FIQ and IRQ never enough for all of the I/O devices Need a mechanism to attach multiple devices to the same IRQ pin. Two ways to do this:
to wire AND-OR the interrupts coming from the peripherals or external devices together. requires polling by the processor to determine the source of the interrupt ( not effective) To use an external interrupt controller, which is a specialized pieces of hardware that takes in all of the interrupt lines, assigns priorities to them and often provides additional information to help the processor, such as a register that can be read for to quickly determine who requested the interrupt.

Interrupts

IRQ CPSR 7 ARM Processor Core

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Vectored Interrupt Controllers

The modern method to handle multiple interrupt sources is to use whats known as a vectored interrupt controller. A vectored interrupt controller (VIC) is often connected to AHB bus and appears as a memory-mapped device. In LPC24xx microcontrollers, the VIC occupies memory addresses ranging from 0xFFFFF000-0xFFFFFF00 for various registers in the controller. The VIC has multiple inputs (32 interrupt inputs) and only two outputs ( the FIQ and the IRQ interrupt lines) that are fed to the ARM7TDMI-S core. It also provides the address of the interrupt handler. The processor then loads this value into the program counter by the way of an LDR PC instruction in IRQ exception vector.
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Vectored Interrupt Controllers

P0
0 1 2

VIC address
0xFFFFFF00 VIC FIQ

P29 P31 P0 : WDT P29: UART3 P31: I2S

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29 30 31

Processor

IRQ
0x18 : LDR PC, [PC, #-0x12]

When LDR instruction is executed, PC will contain 0x20 0x20 0x12 = 0xFFFFFF00

Vectored Interrupt Controllers

UART0 is connected to slot 6 of VIC Slot 1 is reserved for software interrupt Hardware interrupts of Timer0 and Timer1 are connected to slot 4 and 5 of VIC, respectively

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Vectored Interrupt Controllers

The VIC has a number of registers that can be used for configuration.
Register VICIntEnable (0xFFFFF010) VICIntSelect (0xFFFFF00C) VICVectaddr0 (0xFFFFF100) VICVectaddr31 (0xFFFFF17C) VICVectPriority0 (0xFFFFF200) .. VICVectPriority31 (0xFFFFF27C) 47 Description 32-bit register for which each bit corresponds to a slot in the VIC, 1 enables interrupt 0 disable interrupt 32-bit register for which each bit corresponds to a slot in the VIC, 1 signifies FIQ 0 signifies IRQ Each stores the address of an interrupt handler function for the corresponding interrupt slot

First four bits of these registers define the IRQ priority level for each interrupt slot. Lower number indicates higher priority

 To configure the VIC so that UART0 is interrupt enabled as IRQ interrupt with priority level of 4
VICIntEnable EQU VICIntSelect EQU VICVectPriority6 EQU 0xFFFFF010 0xFFFFF00C 0xFFFFF218

Vectored Interrupt Controllers

LDR r4, =VICIntEnable LDR r5, [r4] ORR r5, r5, #0x20 STR r5, [r4] ; Enable UART0 interrupt LDR LDR BIC STR r4, =VICIntSelect r5, [r4] r5, r5,#0x20 r5, [r4] ; UART0 interrupt is FIQ

LDR r4, =VICVectPriority6 LDR r5, #0x4 STR r5, [r4] ; UART0 with priority level of 4
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Vectored Interrupt Controllers

Setting up UART0 IRQ handler address
VICVectAddr6 EQU 0xFFFFF118

LDR r4, =VICVectAddr6 LDR r5, =IRQ_Handler STR r5, [r4] . .

IRQ_Handler SUB LR, LR, #4 ; Update Link register STMFD SP!, {R0-R12, LR} ; save workspace & LR . . LDR R0, =0xFFFFFF00 ; handler address to CPU LDR R1, =0x0 ; to clear VIC address LDR R1, [R0] ; disables the interrupt request LDMFD SP!, {R0-R12, PC}^ ; return to program restoring state
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Returning from interrupt handler

Note that the link register is adjusted before it is loaded to PC for returning to the program. (why?)
SUB LR, LR, #4
Cycle address 0x8000 0x8004 0x8008 0x800C 0x0018 0x001C 0x0020 Operation ADD SUB MOV X B (to 0xAF00) XX XXX F D F 1 E Decode IRQ F F F D F E D F Execute IRQ Linkret
(0x800C)

Adjust (0x8008)

0xAF00 0xAF04 0xAF08

STMFD MOV LDR

D F

E D F

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Returning from interrupt handler

Note also that an interrupt handler should always contains code that clears the source of the interrupt.
Peripheral flag clear Disable the interrupt request by writing to the VICAddress register

In addition to configuring the VIC to accept interrupt from a particular peripheral , the peripheral device should also be configured to raise interrupt along with control and pin settings.
The interrupt register of a peripheral device is used to configure the device for raising interrupt flag(s).

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Configuring Peripheral for interrupt

The following ARM code configure UART0 of LPC2478 microcontroller to raise interrupt when the transmit buffer is empty

U0START IER

EQU 0xE000C000 EQU 0x04

LDR r4, =U0START LDRB r5, [r4,#IER] BIC r5,r5,#0x3F ORR r5,r5,#0xC2 ; enable THRE interrupt STRB r5, [r4,#IER]
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A complete program framework

At power on an ARM processor will execute the instruction at address zero except when connected to special hardware development systems The complete program must have instructions at all the exception vector addresses with each one causing execution of appropriate exception handler. The most general form has instructions of the form LDR PC, <label> at every vector addresses and a table of handler addresses. ( often followed approach) An alternative form of start up code is one with branch instructions BAL <label> at each vector address. ( must ensure if label is within range> Every handler should have an STMFD instruction on entry and an LDMD instruction on exit as every register used by the handler, including r0 to r3, must be saved.
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A complete program framework

;start up code framework using LDR instructions and table AREA Vector_set, CODE, READONLY LDR PC, initial ; to normal reset start up LDR PC,undef ; handle co-processor instructions LDR PC,soft_int ; SWI processing LDR PC, prefetch ; invalid instruction address LDR PC, data_abt ; invalid data address DCD 0 LDR PC, int_req ;normal interrupt handler fiq_handler ; insert the fast interrupt handler code here. SUBS PC, r14, #4 ; exit handler to instruction after ;the one completed before FIQ accepted initial undef soft_int prefetch data_abt int_req 54 DCD DCD DCD DCD DCD DCD uni_handler und_handler swi_handler pre_handler abt_handler irq_handler

A complete program framework

ini_handler ;Put all the hardware and software initialization code here. ;IMPORTANT:- separate stacks should be set for each exception ; usually change to user mode with IRQ and FIQ as required main ; The main function actions here. Most systems loop for ever. B main ; loop forever if a simple program uni_handler ; Insert handler invalid instruction codes. Emulate a co-processor ; if not fitted, detect all other invalid code and attempt recovery. MOVS PC, r14 ; if sensible return to the instruction immediately ; after the invalid one swi_handler ; Insert handler for SWI instructions here MOVS PC, r14 ;if appropriate return to instruction ; immediately after SWI
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A complete program framework

pre_handler ;Insert code here to handle fetch from memory which does not exist SUBS PC, r14, #4 ; if sensible ( not often true) return to try ;instruction again else add special code abt_handler ; Insert code here to handle access to memory which does not exist SUBS PC, r14, #8 ; if sensible return to retry data transfer else try ; to recover irq_handler ; Insert interrupt IRQ handler here SUBS PC, r14, #4 ; go to instruction after the one completed before ;IRQ accepted

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