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FPGA-01: SPARTAN - III Protoboard

FPGA-01 MODEL : MXS3FK-PQ208-IM Rev: 003 OPERATIONAL MANUAL

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Welcome
Introduction
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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Safety Guidelines
Read carefully and follow the instructions mentioned in this manual. This user manual includes all the important points about the installation, use and the maintenance of the product. Keep this manual always with you, for quick reference. After unpacking the product, arrange all the accessories in proper order, so that their integrity is checked with the packing list. Also, ensure that the accessories have no visible damage. Before connecting the power supply to the kit, be sure that the jumpers and the connecting chords are connected correctly, as per the experiment. This kit must be employed only for the use for which it has been conceived, i.e. as educational kit and must be used under the direct survey of expert personnel. Any other use is inadvisable and dangerous too. The manufacturer cannot be considered responsible for eventual damages due to improper, wrong or unreasonable uses. In case of any fault or malfunctioning in the trainer kit, turn off the power supply. Please do not tamper the kit. If you require our service, kindly contact the service centre for technical assistance. The kits are liable to malfunction/ underperforms if it is not operated under following conditions: Ambient temperature: Between 0 to 45 C Relative humidity: Between 20 to 80 % Avoid any immediate/significant change of temperature and humidity.

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Warranty
This kit is warranted against defects in workmanship and materials. Any failure due to defect in either workmanship or material should occur under normal use within a year from the original date of purchase, such failure will be corrected free of charge to the purchaser by repair or replacement of defective part or parts. When the failure is result of users neglect, natural disaster or accident, we would charge for repairs, regardless of the warranty period. The warranty does not cover include perishable items like connecting chords, crystals, etc. and other imported items.

Conditions and Limitations


The warranty is void and inapplicable if the defective product is not brought or sent to our authorized service center or sales outlet within the warranty period. Defective product will be Falcon Electro - Tek Pvt. Ltds sole judgment. The defective product will be replaced with a new one or repaired, without charge or with charge. In the warranty period if the service is needed, the purchaser should get in touch with the service center or the sales outlet. The purchaser should return the product to the service center or the sales outlet at his or her sole expense. The loss and damage in transit will be outside the preview of this warranty. A returned product must be accompanied by a written description of the defects. Type and Model No. of the kit has to be mentioned specifically. We return the product to the purchaser at our expense. In case the warranty does not cover the product on Falcon Electro-Tek Pvt. Ltd.s judgment, we would repair the product after obtaining prior permission from purchaser who would receive an estimate statement about the repairing charges. In such cases, Falcon Electro-Tek Pvt. Ltd. bares the transporting expenses required to send back all the repaired products for the moment, and then repairs and transporting expenses will be charged against the purchaser by the statement of accounts. When the authorized sales agents sell our products, they must notify the purchaser of the warranty contents, but they have no rights to stretch the meaning of original warranty contents or to offer an additional warranty. Falcon Electro-Tek Pvt. Ltd. does not provide any other promise or suggestive warranty and hold no liability for the damage caused by negligence, abnormal use or natural disaster. Falcon Electro-Tek Pvt. Ltd. is not responsible for the damages even if it is notified of above dangers in advance as well. For more special service or overall repairs, maintenance and up gradation of products, be sure to contact our service center or the sales outlet.

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

FALCON ELECTRO TEK PVT. LTD Title: Test Report Of Product

PRD / F03 / 0 1- 9 - 04

Test Report
Customer Name : Distributor Name : Model Serial No. Sr. No. 1. 2. 3. 4. 5. 6. 7. 8. : FPGA-01: SPARTAN - III Protoboard : Types Of Tests Visual Inspection Electrical Check Functional Settings Functional Test Burning Test Final Check Accessories Check As Per List Packing Report

Checked By Signature Installed By Signature

: ______________________________ : ______________________________ : ______________________________ : ______________________________

Date: ________

Date: ________

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

FALCON ELECTRO TEK PVT. LTD Title: Test Report Of Product

PRD / F03 / 0 1- 9 - 04

Test Report
Customer Name : Distributor Name : Model Serial No. Sr. No. 1. 2. 3. 4. 5. 6. 7. 8. : FPGA-01: SPARTAN - III Protoboard : Types Of Tests Visual Inspection Electrical Check Functional Settings Functional Test Burning Test Final Check Accessories Check As Per List Packing Report

Checked By Signature Installed By Signature

: ______________________________ : ______________________________ : ______________________________ : ______________________________

Date: ________

Date: ________

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Table Of Content
PREFACE ...............................................................................................................................1 About This Manual..................................................................................................................1
Manual Contents .................................................................................................................................1

CHAPTER 1 ............................................................................................................................2 INTRODUCTION ....................................................................................................................2


Features ..............................................................................................................................................2

CHAPTER 2 ............................................................................................................................4 Seven Segment LED Display .................................................................................................4 CHAPTER 3 ............................................................................................................................6 Serial Interface .......................................................................................................................6
3.1 RS- 232 Interface ..........................................................................................................................6

CHAPTER 4 ............................................................................................................................7 LCD Interface .........................................................................................................................7


4.1 Data Lines Connection ..................................................................................................................7 4.2 Control Line Interface: ...................................................................................................................8 4.3 ASCII CODE .................................................................................................................................8

CHAPTER 5 ............................................................................................................................9 Traffic Light controller using FPGA.........................................................................................9


5.1 Design Description:- ......................................................................................................................9 5.2 Experimental Set up:- ..................................................................................................................11 5.3 Component Diagram - .................................................................................................................12 5.4 VHD Code for Traffic Light Controller ..........................................................................................12

CHAPTER 6 ..........................................................................................................................21 real clock timer .....................................................................................................................21


6.1 Description for Real Clock Timer .................................................................................................21 6.2 VHD Code for Real Clock Timer ..................................................................................................21

CHAPTER 7..........................................................................................................................27 ADC - DAC Interface ............................................................................................................27


7.4 Analog INPUT Connector: ...........................................................................................................27 7.1 ANALOG INPUT..........................................................................................................................27 7.3 ANALOG OUTPUT ......................................................................................................................28 7.4 Analog Output Connector: ...........................................................................................................28

VHDL CODE FOR ADC-DAC LOOPBACK .........................................................................30 CHAPTER 8 ..........................................................................................................................33 Connector Details .................................................................................................................33
8.1 DIGITAL IOs. ...............................................................................................................................33

CHAPTER 9 ..........................................................................................................................34 JUMPER SETTINGS............................................................................................................34 CHAPTER 10 ........................................................................................................................35 Clock and Reset Sources .....................................................................................................35 CHAPTER 11 ........................................................................................................................36 Power Supplies.....................................................................................................................36
11.1 Voltage Regulators ....................................................................................................................36

VLSI Training System

FPGA-01: SPARTAN - III Protoboard APPENDIX A ........................................................................................................................37 Consolidated UCF for the Complete Board ..........................................................................37 APPENDIX B ........................................................................................................................40 Operating Instructions To Start A New Design.....................................................................41
B.1 Starting The ISE Software:..........................................................................................................41 B.2 Design Flow ................................................................................................................................41 B.3 Design Description......................................................................................................................41 B.4 Truth Table of Half adder: - .........................................................................................................42 B.5 VHDL Code for Half adder ..........................................................................................................42 B.6 Steps to implement the Half adder in the FPGA using Xilinx ISE(8.1i) ........................................42

APPENDIX C ........................................................................................................................57 SAMPLE CODES .................................................................................................................57


C.1 keyboard-display & I/O interface test code..................................................................................57

LIST OF FIGURES
Figure1: Block Diagram ................................................................................................................3 Figure 2: Seven Segment Display ................................................................................................4 Figure 3: FPGA RS232 Interface ...............................................................................................6 Figure 4: LCD Interface to SPARTAN-3 FPGA.............................................................................7 Figure 5: ASCII Code for 5 x 7 LCD display .................................................................................8 Figure 6: State Diagram for Traffic Light Controller ....................................................................10 Figure 7: Traffic Light Interface to SPARTAN-3 FPGA ...............................................................11 Figure 8: FPGA ADC DAC Interface........................................................................................27 Figure 9: Input Channel of ADC..................................................................................................28

LIST OF TABLES
Table 1: Seven Segment Display Interface to SPARTAN-3 FPGA...............................................5 Table 2: RS232 Interface to SPARTAN -3 FPGA .........................................................................6 Table 3: Data Line Interface to SPARTAN-3 FPGA......................................................................7 Table 4: Control Line Interface to SPARTAN-3 FPGA..................................................................8 Table 5: Traffic light controller Interface to SPARTAN-3 FPGA..................................................20 Table 6: Real Clock Timer Interface to SPARTAN-3 FPGA........................................................26 Table 7 : Analog Input.................................................................................................................27 Table 8: Analog Output ...............................................................................................................28 Table 9: ADC Interface to SPARTAN III FPGA...........................................................................28 Table 10: Control Inputs to ADC .................................................................................................28 Table 11: DAC Interface to FPGA...............................................................................................29 Table 12: IO Connector Interface to FPGA.................................................................................33 Table 13: IO Clock-Reset Interface to FPGA..............................................................................35 Table 14: Power Supply Details..................................................................................................36

VLSI Training System

FPGA-01: SPARTAN - III Protoboard

PREFACE
About This Manual
This manual gives operational details for all the interfaces.

Manual Contents
This manual contains following chapters: Chapter 1, Introduction Chapter 2, Seven Segment LED Display Chapter 3, Serial Interface Chapter 4, LCD Interface Chapter 5, Traffic Light Controller using FPGA Chapter 6, Real Clock Timer Chapter 7, ADC And DAC Interface Chapter 8, Connector Details Chapter 9, Jumper Settings Chapter 10, Clock And Reset Sources Chapter 11, Power Supplies Appendix A Consolidated UCF for the complete Board Appendix B, Operating Instructions To Start New Design Appendix C, Sample Codes

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

CHAPTER 1
INTRODUCTION
Spartan-3 trainer Development Board (MXS3FK-PQ208-IM) provides an easy to use development platform for realizing various designs around SPARTAN-3 FPGA.

Features
Figure 1 shows the SPARTAN-3, which includes the following components and features: SPARTAN -3 FPGA : 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat Package (MXS3FK-PQ208-IM ) Three families Spartan 3 /Spartan 3L/Spartan 3 XA. Very low cost, high-performance logic solution for high-volume, consumer-oriented applications. - Densities as high as 74,880 logic cells. - Three power rails for core (1.2V), I/Os (1.2V to 3.3V) and Auxiliary purposes (2.5V). - 326 MHz system clock rate. - 90 nm process technology. Select IO Signaling. - Up to 784 I/O pins. - 622 Mb/s data transfer rate per IO. - 18 single-ended signal standards. - 6 differential I/O standards including LVDS, RSDS. - Termination by Digitally Controlled Impedance. - Double data Rate (DDR) support. Logic Resources - Abundant Logic cells with shift register capability. - Wide Multiplexers. - Fast look-ahead carry logic. - Dedicated 18 x 18 Multipliers. SelectRAM Hierarchical Memory. - Up to 1,872 Kbits of total block RAM. - Up to 520 Kbits of Distributed RAM. Digital Clock Manager (up to 4DCMs) - Clock skew elimination. - Frequency synthesis - High resolution phase shifting. Eight global clock lines and abundant routing. Micro Blaze processor, PCI and other cores. Traffic Light Control Interface :-16 green LEDS, 8 Red LEDS, 4 Yellow LEDS Traffic Light Interface module will be connected using 60 pin Connector (J5). Analog Interface: 12 bit AD7891 ADC and 12 bit AD7541 DAC.(OPTIONAL) Analog Input Eight channels using ADC using AD7891, (500Ksps, 12 bit). Analog Output- Two channels using Two DACs-AD7541. (12 bit, 100 ns conversion time) Seven Segment Display: Six-character multiplexed seven-segment LED display. DIP Switches: 16 DIP switches. LEDs: 20 onboard LEDS 16 output LEDs (OL 0 OL 15). Done LED.(DONE) 3 Power ON LEDs (LED5V, LED3V3, LED2V5). Push Button Switches: 16 momentary-contact push button switches in 4x4 matrix.

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Figure1: Block Diagram 1. LCD interface: 16 character 2 row LCD. Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector). RS-232 transceiver/level translator using MAX3223 in SSOP package. Uses straight-through serial cable to connect to computer or workstation serial port. User selectable configuration modes - Boundary scan, Master serial. User selectable Interface hardware Traffic Light, RTC, ADC-DAC. Free IOs: 60 pin FRC Connector (J5) and 34 pin FRC Connector (J2) provided for free I/Os. Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source. JTAG port: JTAG download cable (parallel III) interface. Power Supplies: 5 volts regulated power supply provided along with the board. On board 3.3V, 2.5V, 1.2V regulators. FPGA supplies viz. Vccint (1.2V) & Vcco (3.3V) are generated on board

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

CHAPTER 2
Seven Segment LED Display
SPARTAN-3 -IM has a Six multiplexed seven segment .Each individual character has a separate cathode control input. To light an individual signal, drive the individual segment control signal High along with the associated cathode control signal for the individual character. The control signal is high, enabling the control inputs for the left-most character. The segment control inputs, A through G and DP, drive the individual segments that comprise the character. A High value lights the individual segment, a Low turns off the segment.

Figure 2: Seven Segment Display The two types of the seven segment displays are as shown below Common Cathode Display: In this type of display the cathode of all the LEDs are tied together and the anode terminals decides the status of the LED, either ON or OFF. To turn ON the LED i.e. segment value of driven segment should be 1 and 0 for turn OFF.

Common Anode Display: In this type of display all the anode terminals of LEDs are tied together and the cathode terminals decide the status of the LED either ON or OFF. To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF.

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Interface details for the seven segment display with SPARTAN-3 display is as follows Table 1: Seven Segment Display Interface to SPARTAN-3 FPGA
Control Bit "SEGA" "SEGB" "SEGC" "SEGD" FPGA Pin p144 p143 p141 p140 p139 p138 p137 P135 p97 p100 p101 p102 p132 p133

"SEGE" "SEGF" "SEGG" "SEGDP"


"DIS0 " "DIS1 " "DIS2 " "DIS3 " "DIS4 " "DIS5 "

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

CHAPTER 3
Serial Interface
SPARTAN -3 - IM supports RS-232 serial interface. The details of interface are described below.

3.1 RS- 232 Interface


The RS-232 transmit and receive signals appear on the female DB9 connector, indicated as in Figure 3. The connector is a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers and workstations. Use a standard straightthrough serial cable to connect the SPARTAN -3 IM to the PCs serial port.

Figure 3: FPGA RS232 Interface Figure 3 shows the connection between the FPGA and the DB9 connector, including the Maxim MAX3223 RS-232 voltage converter. The FPGA supplies serial output data as LVTTL or LVCMOS levels to the Maxim device, which in turn converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. Hardware flow control is not supported on the connector. The ports DCD, DTR, and DSR signals are left unconnected. Similarly, the ports CTS and Ring Indicator are used as an auxiliary RS232 channel signals The FPGA connections to the Maxim RS-232 translator appear in Table 2. Table 2: RS232 Interface to SPARTAN -3 FPGA
Control Bit "RS232_RXD<1>" "RS232_RXD<2>" "RS232_TXD<1>" "RS232_TXD<2>" FPGA Pin p176 p178 p175 p172

For more details on RS232 UART application please refer the following application note AN2141 from Maxim.

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

CHAPTER 4
LCD Interface
SPARTAN-3 -IM includes a LCD Module, which is a dot matrix liquid crystal display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA. This LCD has a built in Dot Matrix controller, with font 5 X 7 or 5 X 10 dots, display data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10. All the functions required for LCD are provided internally. Internal refresh is provided by the Controller. The Interface details of the LCD display are as shown in figure 4.

Figure 4: LCD Interface to SPARTAN-3 FPGA

4.1 Data Lines Connection


LCD has 8 bit bidirectional data bus interface to FPGA. When Enable signal is at low level, this data bus remains in high impedance state. Interface details of the data lines with SPARTAN-3 FPGA are as in Table 3 Table 3: Data Line Interface to SPARTAN-3 FPGA DATA BIT
"LCD_D<0>" "LCD_D<1>" "LCD_D<2>" "LCD_D<3>" "LCD_D<4>" "LCD_D<5>" "LCD_D<6>" "LCD_D<7>" FPGA Pin p167 p166 p165 p162 p161 p156 p155 p154

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FPGA-01: SPARTAN - III Protoboard

4.2 Control Line Interface:


The control lines of LCD comprises of RS, R/W# and E The significance of the above mentioned control signals is as follows RS: Register select signal used to select Data register or a Command/Status register. High on RS selects the data register. Low on RS selects the Command/Status register. R/W#: Read/Write select control line. High on R/W # selects the read operation Low on R/W # selects the write operation. E: Enable signal used to enable or disable the data bus. Low on the enable signal puts the data bus into a high impedance state. High on the enable signal selects the data bus

The control line interface of LCD with FPGA is as shown in table 4 Table 4: Control Line Interface to SPARTAN-3 FPGA
Control Bit "LCD_E" "LCD_RS" "LCD_RW_BAR" FPGA Pin p168 p171 p169

Note: PR1 is used to adjust the contrast of LCD Display

4.3 ASCII CODE


The ASCII code for 5x 7 LCD Display is given in Figure 5

Figure 5: ASCII Code for 5 x 7 LCD display

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

CHAPTER 5
Traffic Light controller using FPGA
Spartan-3 - IM includes a TRAFFIC LIGHT Interface Module. This module is interfaced to the Trainer using 60 pin FRC cable. Traffic Light controller is implemented in FPGA and verified using Traffic Light Interface Module. There are simple rules for traffic lights on one node, and complex ways of regulating a whole infrastructure of them. It is necessary to adjust general algorithms

5.1 Design Description: Initially all Red Lights will be ON (South, west, North, East, Pedestrian) Green Lights of will be ON, Right, Left & Straight paths are free for Traffic. Yellow Phase is split as yellow1 & yellow2. In yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. In Yellow2 Phase only yellow lights will be ON Same flow is repeated for all four paths. (South, west, north, east).

Flowchart:-

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard To implement Traffic Light controller refer the waveform given below

Algorithm is implemented in VHDL with a 13 state Finite State Machine. Refer Fig

Below. Figure 6: State Diagram for Traffic Light Controller

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FPGA-01: SPARTAN - III Protoboard Abbreviation used:South PSG Pedestrian South Green PSR Pedestrian South Red RS Right South LS Left South SS Straight South YS Yellow South REDS Red South North PNR- Pedestrian North red PNG Pedestrian North green RN Right North LN Left North SN Straight North YN - Yellow North REDN Red North West PWR Pedestrian West Red PWG Pedestrian West Green RW Right West LW Left West SW South West YW Yellow West REDW Red West East PEG Pedestrian East green PER Pedestrian Ease Red RE Right East LE Left East SE Straight East YE Yellow East REDE Red East

5.2 Experimental Set up:-

Figure 7: Traffic Light Interface to SPARTAN-3 FPGA

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard

5.3 Component Diagram -

CONCLUSION:Design of Traffic Light Controller is implemented in Spartan-3 Trainer and is verified using Traffic Light Interface Module according to the following Algorithm.

5.4 VHD Code for Traffic Light Controller


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Traffic_Control is Port ( CLK_4M,RESET : in std_logic; TRC_LS,TRC_LW,TRC_LN,TRC_LE: out std_logic; TRC_SS,TRC_SW,TRC_SN,TRC_SE: out std_logic; TRC_RS,TRC_RW,TRC_RN,TRC_RE : out std_logic; - 12 VLSI Training System

FPGA-01: SPARTAN - III Protoboard TRC_REDS,TRC_REDW,TRC_REDN,TRC_REDE : out std_logic; TRC_YS,TRC_YW,TRC_YN,TRC_YE : out std_logic; TRC_PSR,TRC_PWR,TRC_PNR,TRC_PER : out std_logic; TRC_PSG,TRC_PWG,TRC_PNG,TRC_PEG : out std_logic); end Traffic_Control; architecture Behavioral of Traffic_Control is type state is (start,south_g,south_orange,south_r,west_g,west_orange, west_r,east_g,east_orange,east_r,north_g,north_orange,north_r); signal ps , ns : state; signal div : std_logic_vector(30 downto 0); signal clk_s : std_logic; signal cnt : std_logic_vector(3 downto 0) ; begin --*************************** Divider ************************** process(CLK_4M,RESET) begin if(RESET = '1') then div <= (others => '0'); elsif(CLK_4M'event and CLK_4M = '1') then div <= div + 1; end if; end process; clk_s <= div(20); --*************************** Counter ************************** process(clk_s ,RESET) begin if(RESET = '1') then cnt <= (others => '0'); elsif(clk_s'event and clk_s = '0') then cnt <= cnt + 1; end if; end process; --*************************** Memory_logic ********************* process(clk_s,RESET) begin if (RESET = '1')then ps <= start; elsif(clk_s'event and clk_s = '1') then ps <= ns; end if; end process; --*************************** Input_logic ********************** process(ps) begin case ps is when start => ns <= south_g; when south_g => if(cnt = 10)then ns <= south_orange; else ns <= south_g; end if;

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VLSI Training System

FPGA-01: SPARTAN - III Protoboard when south_orange => if(cnt = 14) then ns <= south_r; else ns <= south_orange; end if; when south_r => if(cnt = 15)then ns <= west_g; else ns <= south_r; end if; when west_g => if(cnt = 10) then ns <= west_orange; else ns <= west_g; end if; when west_orange => if(cnt = 14) then ns <= west_r; else ns <= west_orange; end if; when west_r => if(cnt = 15 )then ns <= north_g; else ns <= west_r; end if; when north_g => if(cnt = 10)then ns <= north_orange; else ns <= north_g; end if; when north_orange => if(cnt = 14)then ns <= north_r; else ns <= north_orange; end if; when north_r => if(cnt = 15)then ns <= east_g; else ns <= north_r; end if; when east_g => if(cnt = 10)then ns <= east_orange; else ns <= east_g; end if; when east_orange => if(cnt = 14)then ns <= east_r; else - 14 VLSI Training System

FPGA-01: SPARTAN - III Protoboard ns <= east_orange; end if; when east_r => if(cnt = 15)then ns <= south_g; else ns <= east_r; end if; when others => ns <= start; end case; end process; --*************************** Output_logic ************************** process(ps) begin TRC_REDS <= '0'; TRC_REDW <= '0'; TRC_REDN <= '0'; TRC_REDE <= '0'; TRC_RS <= '0'; TRC_RW <= '0'; TRC_RN <= '0'; TRC_RE <= '0'; TRC_SS <= '0'; TRC_SW <= '0'; TRC_SN <= '0'; TRC_SE<= '0'; TRC_LS <= '0'; TRC_LW <= '0'; TRC_LN <= '0'; TRC_LE <= '0'; TRC_PSG <= '0'; TRC_PWG <= '0'; TRC_PNG <= '0'; TRC_PEG <= '0'; TRC_YS <= '0'; TRC_YW <= '0'; TRC_YN <= '0'; TRC_YE <= '0'; TRC_PSR <= '0'; TRC_PWR <= '0'; TRC_PNR <= '0'; TRC_PER <= '0'; case ps is when start => TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; when south_g => TRC_LS <= '1'; TRC_RS <= '1'; TRC_SS <= '1'; TRC_LE <= '1'; TRC_REDW <= '1'; - 15 VLSI Training System

FPGA-01: SPARTAN - III Protoboard TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when south_orange => TRC_PNG <= '1'; TRC_LE <= '1'; TRC_LS <= '1'; TRC_YS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PER <= '1'; when south_r => TRC_LS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when west_g => TRC_LW <= '1'; TRC_LS <= '1'; TRC_RW <= '1'; TRC_SW <= '1'; TRC_REDS <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when west_orange => TRC_LW <= '1'; TRC_LS <= '1'; TRC_PEG <= '1'; TRC_YW <= '1'; TRC_REDS <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; when west_r => TRC_LW <= '1'; TRC_REDS <= '1'; TRC_REDN <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; - 16 VLSI Training System

FPGA-01: SPARTAN - III Protoboard when north_g => TRC_LN <= '1'; TRC_RN <= '1'; TRC_SN <= '1'; TRC_LW <= '1'; TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when north_orange => TRC_LN <= '1'; TRC_LW <= '1'; TRC_PSG <= '1'; TRC_YN <= '1'; TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDE <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when north_r => TRC_LN <= '1'; TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDE <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when east_g => TRC_RE <= '1'; TRC_SE<= '1'; TRC_LE <= '1'; TRC_LN <= '1'; TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when east_orange => TRC_LN <= '1'; TRC_LE <= '1'; TRC_PWG <= '1'; TRC_YE <= '1'; TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_PSR <= '1'; TRC_PNR <= '1'; TRC_PER <= '0'; when east_r => TRC_LE <= '1'; - 17 VLSI Training System

FPGA-01: SPARTAN - III Protoboard TRC_REDS <= '1'; TRC_REDW <= '1'; TRC_REDN <= '1'; TRC_PSR <= '1'; TRC_PWR <= '1'; TRC_PNR <= '1'; TRC_PER <= '1'; when others => TRC_REDS <= '0'; TRC_REDW <= '0'; TRC_REDN <= '0'; TRC_REDE <= '0'; TRC_RS <= '0'; TRC_RW <= '0'; TRC_RN <= '0'; TRC_RE <= '0'; TRC_SS <= '0'; TRC_SW <= '0'; TRC_SN <= '0'; TRC_SE<= '0'; TRC_LS <= '0'; TRC_LW <= '0'; TRC_LN <= '0'; TRC_LE <= '0'; TRC_PSG <= '0'; TRC_PWG <= '0'; TRC_PNG <= '0'; TRC_PEG <= '0'; TRC_YS <= '0'; TRC_YW <= '0'; TRC_YN <= '0'; TRC_YE <= '0'; TRC_PSR <= '0'; TRC_PWR <= '0'; TRC_PNR <= '0'; TRC_PER <= '0'; end case; end process; end Behavioral; ***********************Abbreviation used************************** #PS-G Pedestrian South Green #PS-R pedestrian South Red #RS Right South #LS Left South #SS Straight South #YS Yellow South #RED-S Red South #PW-R Pedestrian west red #PW-G Pedestrian west Green #LW Left West #SW South West #RW Right West #YW yellow West #RED-W Red West - 18 #PN-R- Pedestrian North Red #PN-G Pedestrian North Green #RED-E Red East #YE Yellow East #SE Straight East #RE Right East #LE Left East #PE-G Pedestrian East green #PE-R Pedestrian East Red #RED-N Red North #YN - Yellow North #LN Left North #RN Right north #SN Straight North VLSI Training System

FPGA-01: SPARTAN - III Protoboard

Description of above Code:To Start the Traffic light controller 1. Initially the Red light of all the directions is ON. 2. Traffic starts from the South Direction, hence the green light of South direction goes ON. The signals that are ON, now are : ls ( left south ) 1. rs ( right south ) 1. ss ( straight south ) 1. le ( left east ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. Similarly when Orange light of South direction is ON then the signals that are ON, now are ls ( left south ) 1. ys ( yellow south ) 1. le ( left east ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. Similarly when Red light of South direction is ON then the signals that are ON, now are ls ( left south ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. During this time all ways are Blocked for 1 second except left south ( ls -1 ) and so on. After that it goes clockwise for all Direction (i.e.:- South then West then North then East) similarly. Note:-For Pin Locking refers the pin out diagram of the specific adapter and the device used on that adapter. Refer Appendix -A.

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FPGA-01: SPARTAN - III Protoboard Table 5: Traffic light controller Interface to SPARTAN-3 FPGA
SIGNAL NAME "TRC_LE" "TRC_LN" "TRC_LS" "TRC_LW" "TRC_PEG" "TRC_PER" "TRC_PNG" "TRC_PNR" "TRC_PSG" "TRC_PSR" "TRC_PWG" "TRC_PWR" "TRC_RE" "TRC_REDE" "TRC_REDN" "TRC_REDS" "TRC_REDW" "TRC_RN" "TRC_RS" "TRC_RW" "TRC_SE" "TRC_SN" "TRC_SS" "TRC_SW" "TRC_YE" "TRC_YN" "TRC_YS" "TRC_YW" FPGA PIN NO. = "p107"; = "p125"; = "p150"; = "p130"; = "p116"; = "p117"; = "p128"; = "p124"; = "p12"; = "p13"; = "p148"; = "p149"; = "p114"; = "p109"; = "p120"; = "p108"; = "p126"; = "p122"; = "p111"; = "p147"; = "p115"; = "p123"; = "p152"; = "p146"; = "p106"; = "p119"; = "p113"; = "p131"; CONNECTOR J3 PINNO. #J3-20 #J3-9 #J3-25 #J3-6 #J3-16 #J3-15 #J3-7 #J3-10 #J3-28 #J3-27 #J3-2 #J3-1 #J3-18 #J3-22 #J3-13 #J3-21 #J3-8 #J3-12 #J3-23 #J3-3 #J3-17 #J3-11 #J3-26 #J3-4 #J3-19 #J3-14 #J3-24 #J3-5

net net net net net net net net net net net net net net net net net net net net net net net net net net net net

loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc

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CHAPTER 6
real clock timer
6.1 Description for Real Clock Timer
Real Clock timer consists of six character multiplexed display working on system clock of 4 MHz. Out of six displays first two (DIS -6 and DIS- 5) are used to display hours, next two (DIS-4 and DIS-3) are used to display minutes and last two (DIS -2 and DIS-1) are used to display seconds status. Real time status is displayed on these seven segments by writing a HDL functionality of 6 counters cascaded with each other and decoding its output to seven segment equivalents. HDL functionality also offers a provision for loading the real clock timer with a new value using load signal, when high real clock timer is loaded with new value. Control signal is also provided to set 24 or 12 hour mode of operation, when high 24 hour mode is selected whereas low on control signal selects 12 hour mode of operation.

6.2 VHD Code for Real Clock Timer


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ------------------------------------------------------------------------------------This is real time clock in this we use --4mhz clock -- to generate 1 sec clock we use enable signal high for last 1 count -- sec1 counter for reading sec -- sec2 counter for reading sec -- min1 counter for reading min -- min2 counter for reading min -- hr1 counter for reading hr -- hr2 counter for reading hr entity RTC_IM is port(RESET,CLK_4M,load,control:in std_logic; RTC_SEG:out std_logic_vector(7 downto 0); RTC_DIS:out std_logic_vector(5 downto 0)); end RTC_IM; architecture Behavioral of RTC_IM is signal tc,tc1,tc2,tc3,tc4,tc5,tc6,enable:std_logic; signal sec1,sec2,min1,min2,hr1,hr2: std_logic_vector(3 downto 0); signal sec1_rg:std_logic_vector(3 downto 0); signal sec2_rg:std_logic_vector(3 downto 0); signal min1_rg:std_logic_vector(3 downto 0); signal min2_rg:std_logic_vector(3 downto 0); signal hr1_rg:std_logic_vector(3 downto 0); signal hr2_rg:std_logic_vector(3 downto 0); signal pulsegen:std_logic_vector(21 downto 0); signal sel:std_logic_vector(2 downto 0); signal mout:std_logic_vector(3 downto 0); signal sgout:std_logic_vector(7 downto 0); signal dis_sig:std_logic_vector(5 downto 0); signal cnk2:std_logic_vector(2 downto 0); begin

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--*************************** Pulse Generator ****************** p0:process(RESET,CLK_4M,pulsegen) begin if (RESET = '1') then pulsegen <= "0000000000000000000000"; elsif rising_edge (CLK_4M) then if (pulsegen = "1111010000100100000000") then pulsegen <= "0000000000000000000000"; else pulsegen <= pulsegen + 1; end if; end if; end process; ---------- Enable signal to generate 1-sec pulse for sec1 counter enable <= '1' when pulsegen = "1111010000100100000000" else '0'; --************************ Second_cntr1 ************************* --enable signal for sec1 counter

p1:process (RESET,CLK_4M,sec1_rg,enable,load) --decade counter begin if (RESET = '1') then sec1_rg <= "0000"; elsif load = '1' then sec1_rg <= "0100"; elsif rising_edge(CLK_4M) then if (enable = '1') then if (sec1_rg = "1001")then sec1_rg <= "0000"; else sec1_rg <= sec1_rg + 1; end if; end if; end if; sec1 <= sec1_rg; end process ; -----------------------tc signal to start sec2 counter---------------------------------tc <= '1' when (sec1_rg = "1001") and (enable = '1') else --signal for sec2 counter '0'; --************************* Second_cntr2 *********************** p2:process (RESET,CLK_4M,sec2_rg,tc,load) --sec2 counter for reading upto 59 sec begin if (RESET = '1') then sec2_rg <= "0000"; elsif (load = '1') then sec2_rg <= "0100"; elsif rising_edge(CLK_4M) then if (tc = '1') then if (sec2_rg = "0101")then sec2_rg <= "0000"; else sec2_rg <= sec2_rg + 1; end if; end if; end if;

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sec2 <= sec2_rg; end process; -----------------------------tc1 signal to start min1 counter-----------------------tc1 <= '1' when (sec2_rg = "0101") and (tc = '1') else '0' ; --************************ Minute_cntr1 ************************* p3:process(RESET,CLK_4M,min1_rg,tc1,load) begin if (RESET = '1') then min1_rg <= "0000"; elsif load = '1' then min1_rg <= "0100"; elsif rising_edge(CLK_4M) then if (tc1 = '1') then if (min1_rg = "1001")then min1_rg <= "0000"; else min1_rg <= min1_rg + 1; end if; end if; end if; min1 <= min1_rg; end process; --------------------------tc2 signal to start min2 counter---------------------------tc2 <= '1' when (min1_rg ="1001") and (tc1 = '1') else --pulse for min2 counter '0'; --************************ Minute_cntr2 ************************* p4:process(RESET,CLK_4M,min2_rg,tc2,load) begin if (RESET = '1') then min2_rg <= "0000"; elsif load = '1' then min2_rg <= "0100"; elsif rising_edge(CLK_4M) then if (tc2 = '1') then if (min2_rg = "0101")then min2_rg <= "0000"; else min2_rg <= min2_rg + 1; end if; end if; end if; min2 <= min2_rg; end process; --------------------------tc3 signal to start hr1 counter---------------------------------tc3 <= '1' when (min2_rg ="0101") and (tc2 = '1') else '0'; --************************ Hour_cntr1 ************************* --min2 counter -- min1 counter

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p5:process(RESET,CLK_4M,hr1_rg,tc3,load,control,tc6,tc5) begin if (RESET = '1') then hr1_rg <= "0000"; elsif (load = '1') then hr1_rg <= "0001"; elsif rising_edge(CLK_4M) then if control = '1' then if (tc5 = '1') then hr1_rg <= "0000"; else if (tc3 = '1') then if (hr1_rg = "1001")then hr1_rg <= "0000"; else hr1_rg <= hr1_rg + 1; end if; end if; end if; else if (tc6 = '1') then hr1_rg <= "0001"; else if (tc3 = '1') then if (hr1_rg = "1001")then hr1_rg <= "0000"; else hr1_rg <= hr1_rg + 1; end if; end if; end if; end if; end if; hr1 <= hr1_rg; end process; ---------------------tc4 signal to start hr2 counter-------------------------tc4 <= '1' when (hr1_rg ="1001") and (tc3 = '1') else '0'; ------------------------tc5 signal to RESET at 23:59:59-------------------------tc5 <= '1' when (hr2_rg ="0010")and (hr1_rg ="0011") and (tc3 = '1') else '0'; -----------------------------tc6 signal to RESET at 11:59:59--------------tc6 <= '1' when (hr2_rg = "0001") and (hr1_rg = "0010") and (tc3 = '1') else '0'; --************************ Hour_cntr2 ************************* p6:process(RESET,CLK_4M,hr2_rg,tc4,load,control) --hr2 counter begin if (RESET = '1') then hr2_rg <= "0000"; elsif load = '1' then hr2_rg <= "0000"; --hr1 counter

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elsif rising_edge(CLK_4M) then if (control = '1') then if (tc5 = '1') then hr2_rg <="0000"; else if (tc4 = '1') then if (hr2_rg = "0010")then hr2_rg <= "0000"; else hr2_rg <= hr2_rg + 1; end if; end if; end if; else if (tc6 = '1') then hr2_rg <="0000"; else if (tc4 = '1') then if (hr2_rg = "0001")then hr2_rg <= "0000"; else hr2_rg <= hr2_rg + 1; end if; end if; end if; end if; end if; hr2 <= hr2_rg; end process; p14:process(RESET, pulsegen(9)) begin if (RESET = '1') then cnk2 <= "000"; elsif rising_edge(pulsegen(9)) then if (cnk2 = "101") then cnk2 <= "000"; else cnk2 <= cnk2 + 1; end if; end if; end process; mout <= sec1 when cnk2 = "000" else sec2 when cnk2 = "001" else min1 when cnk2 = "010" else min2 when cnk2 = "011" else hr1 when cnk2 = "100" else hr2 when cnk2 = "101"; --********hgfedcba**************************** sgout <= "11000000" when mout = "0000" else "11111001" when mout = "0001" else "10100100" when mout = "0010" else "10110000" when mout = "0011" else "10011001" when mout = "0100" else

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"10010010" when mout = "0101" else "10000010" when mout = "0110" else "11111000" when mout = "0111" else "10000000" when mout = "1000" else "10011000" when mout = "1001" else "11111111" ;

dis_sig <=

"111110" when cnk2 = "000" else "111101" when cnk2 = "001" else "111011" when cnk2 = "010" else "110111" when cnk2 = "011" else "101111" when cnk2 = "100" else "011111" ;--when cnk2 = "101" ;

RTC_SEG <= not sgout; RTC_DIS <= not dis_sig; end Behavioral;

Table 6: Real Clock Timer Interface to SPARTAN-3 FPGA net CLK_4M loc = p181 net RESET loc = p182 net load loc = p57 net control loc = p52 net RTC_SEG<7> loc = p31 net RTC_SEG<6> loc = p33 net RTC_SEG<5> loc = p28 net RTC_SEG<4> loc = p29 net RTC_SEG<3> loc = p26 net RTC_SEG<2> loc = p27 net RTC_SEG<1> loc = p20 net RTC_SEG<0> loc = p24 net RTC_DIS<5> loc = p16 net RTC_DIS<4> loc = p15 net RTC_DIS<3> loc = p19 net RTC_DIS<2> loc = p18 net RTC_DIS<1> loc = p21 net RTC_DIS<0> loc = p22

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CHAPTER 7
ADC - DAC Interface (OPTIONAL)
SPARTAN-III IM Board has a high speed, 8 bit ADC (ADC 0808) and DAC (AD 7541), which are assembled on add on board MXS3DB0507-003-ADC-DAC. This card designed for single channel ADC DAC. A detailed interface is as shown in Figure 2

Figure 8: FPGA ADC DAC Interface

7.4 Analog INPUT Connector:


Vin: One PUT connector (J1) is provided on board for ANALOG INPUT Table 7 : Analog Input Vin Vin Gnd

7.1 ANALOG INPUT


Single channel ADC ADC0808 (Resolution 8 bits, Conversion Time 100 us), as shown in Figure 3. This Add on card has following specifications Input range:-0 to 5 Volts Over voltage Protection on channel input using external clamping diodes. Through Channel 1 takes an external analog input from the TERMINAL BLOCK.

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Figure 9: Input Channel of ADC

7.3 ANALOG OUTPUT


Single analog output channel is provided on-board with DAC AD7541 Output Range +5 V to -5 Volts, single ended Resolution - 12 bit. Conversion time - 100 ns Settling time 600 ns. Output Range -0 to 5 Volts.

7.4 Analog Output Connector:


Vout : One PUT connector (J2) is provided on board for ANALOG OUTPUT Table 8: Analog Output Vout Vout Gnd

Table 9: ADC Interface to SPARTAN III FPGA Data Bits adc_data<0> adc_data<1> adc_data<2> adc_data<3> adc_data<4> adc_data<5> adc_data<6> adc_data<7> FPGA pin p11 p7 p10 p204 p9 p4 p2 p3

Table 10: Control Inputs to ADC Control Inputs clk rst adc_clk ale endconv strtconv FPGA PIN p181 p182 p5 p205 p200 p203

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FPGA-01: SPARTAN - III Protoboard Table 11: DAC Interface to FPGA Data Bits dac_data<0> dac_data<1> dac_data<2> dac_data<3> dac_data<4> dac_data<5> dac_data<6> dac_data<7> dac_data<8> dac_data<9> dac_data<10> dac_data<11> FPGA PIN p184 p187 p190 p194 p197 p198 p199 p196 p191 p189 p185 p183

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VHDL CODE FOR ADC-DAC LOOPBACK


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity test_ADC_DAC is port( clk : in std_logic;---- 4MHz system clk rst : in std_logic ;--- reset -------------------ADC INTERFACE------------------------strtconv : out std_logic;-----convstart ale : out std_logic;--- addr latch enble --addr :out std_logic_vector(1 downto 0);----addr of chanel --channel : in std_logic_vector(1 downto 0);----switch input endconv :in std_logic;--- end of conv adc_clk : out std_logic;----clk to adc adc_data : in std_logic_vector(7 downto 0);---data from adc ------------------DAC LOOP BACK--------------------------dac_data : out std_logic_vector(11 downto 0)---data to dac ); end test_ADC_DAC; architecture Behavioral of test_ADC_DAC is type state is(ale_s0,strt_s0,ale_s1,strt_s1,wait_eoc,read0,read1,end_st); signal ps,ns : state; signal ale_sig,soc_sig,rd : std_logic; signal adcclk_sig,fsmclk : std_logic; signal adcdat_sig : std_logic_vector(11 downto 0); signal counter : std_logic_vector( 5 downto 0); signal clkdiv : std_logic_vector(15 downto 0 ); begin ale <=ale_sig; strtconv<=soc_sig; --------------------------countr for 150KHz----------------------------process (rst,clk,counter) begin if(rst = '1' or counter = "11010")then counter <= (others => '0'); elsif(clk'event and clk= '1') then counter <= counter + 1; end if; end process; fsmclk <= '1' when counter = "11001" else '0'; -------- 150kHz clk for FSM ------------------Frequency Divider for 500KHz------------------------------process( clk,rst) begin if(rst = '1')then clkdiv <= (others=>'0');

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elsif(clk'event and clk ='1') then clkdiv <= clkdiv + 1; end if; end process; adcclk_sig <= clkdiv(1); adc_clk <= adcclk_sig; -----1MHz clk to adc --fsmclk <= adcclk_sig; --fsmclk<= clk; ------------------State machine-----------------------------------------------process(fsmclk,rst) begin if(rst = '1') then ps <= ale_s0; elsif(fsmclk'event and fsmclk='1')then ps <= ns; end if; end process; --------------------------------------------------------------------process(ps) begin case ps is when ale_s0 => ns <= strt_s0; when strt_s0 => ns <= ale_s1; when ale_s1 => ns <= strt_s1; when strt_s1 => ns <= wait_eoc; when wait_eoc => if (endconv ='1') then ns <= read0; else ns <= wait_eoc; end if; when read0 => ns <= read1; when read1 => ns <= end_st; when end_st => ns <= ale_s0; when others => ns <= ale_s0; end case; end process; ------------------------------------------------------------------------process(ps) begin ale_sig<= '0'; soc_sig <= '0'; rd <= '0'; case ps is when ale_s0 => ale_sig <= '1'; soc_sig <= '0'; when strt_s0 => soc_sig <= '1'; ale_sig <= '1'; when ale_s1=> ale_sig <= '0'; soc_sig <= '1';

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when strt_s1 => soc_sig <= '0'; when read0 => rd <= '1'; when read1 => rd <='1'; when others=> ale_sig<= '0'; soc_sig <= '0'; rd <= '0'; end case; end process; -----------------------------Latching ADC output-----------------------process(adcclk_sig,rst) begin if(rst='1')then adcdat_sig <= (others=>'0'); elsif(adcclk_sig'event and adcclk_sig ='1')then if(rd='1')then adcdat_sig <= adc_data & "0000"; end if; end if; end process; dac_data <= adcdat_sig; -------ADC DAC LoopBack ----------------Channel Selection ---------------------------------------addr <= "00" when channel = "00" else ---Input to ADC through Thermister circuit. -"01" when channel = "01" else ---Input to ADC through PUT -"10"; ---Input to ADC through Stereo Jack. end Behavioral;

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CHAPTER 8
Connector Details
SPARTAN 3 IM Board has provision for 3 connectors.

8.1 DIGITAL IOs.


For XC3S400 (PQ208) IOs from FPGA are provided on Connectors as follows: I/O Connector - A 16 pin FRC male connector (J6) for RTC Interface. I/O Connector - A 40 pin FRC male connector (J3) for Traffic Light Controller Interface I/O Connector A 34 pin FRC male connector (J7) Free user IOs JTAG Connector2- A 10 pin FRC male connector (J5).Table 12: IO Connector Interface to FPGA
SIGNAL NAME net "IO<1>" net "IO<2>" net "IO<3>" net "IO<4>" net "IO<5>" net "IO<6>" net "IO<7>" net "IO<8>" net "IO<9>" net "IO<10>" net "IO<11>" net "IO<12>" net "IO<13>" net "IO<14>" net "IO<15>" net "IO<16>" net "IO<17>" net "IO<18>" net "IO<19>" net "IO<20>" net "IO<21>" net "IO<22>" net "IO<23>" net "IO<24>" FPGA PIN NO loc = "p184"; loc = "p183"; loc = "p187"; loc = "p185"; loc = "p190"; loc = "p189"; loc = "p194"; loc = "p191"; loc = "p197"; loc = "p196"; loc = "p199"; loc = "p198"; loc = "p203"; loc = "p200"; loc = "p205"; loc = "p204"; loc = "p3"; loc = "p2"; loc = "p5"; loc = "p4"; loc = "p9"; loc = "p7"; loc = "p11"; loc = "p10"; J7 CONNECTOR #J7-1 #J7-2 #J7-3 #J7-4 #J7-5 #J7-6 #J7-7 #J7-8 #J7-9 #J7-10 #J7-11 #J7-12 #J7-13 #J7-14 #J7-15 #J7-16 #J7-17 #J7-18 #J7-19 #J7-20 #J7-21 #J7-22 #J7-23 #J7-24

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CHAPTER 9
JUMPER SETTINGS
Mode Selection is done by selecting states of the mode configuration pins M0, M1, M2 (Jumpers JP4, JP5, JP6 respectively) of the device on board. Given below is the jumper setting for selecting configuration modes. 1. Boundary Scan Mode is used to configure either the PROM or PLD from PC. Number of devices in daisy chain is selected by jumper JP3 mentioned below. 2. To select boundary scan mode, set mode pin jumpers as follows. Configuration Mode Master Serial Mode Boundary Scan Mode M2 (JP6) 0 1 M1 (JP5) 0 0 M0 (JP4) 0 1

Jumper- JP3 connects PROM in the daisy chain if 1-2 are shorted.

3. Master Serial Mode - Is used when configuring PLD through on Board PROM. Note- Before using this mode, PROM must be programmed using Boundary Scan mode. After programming the PROM, power off the kit and set jumpers as follows to select master serial mode. Configuration Mode M2 (JP6) M1 (JP5) M0 (JP4) Master Serial Mode 0 0 0 Clock Enable Jumpers - Jumpers will enable clock 12 JP1 (oscclk) JP2 (clock)

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CHAPTER 10
Clock and Reset Sources
The SPARTAN-3-IM board has a dedicated 4 MHz oscillator source and an optional socket for another clock oscillator source. This dedicated clock source can be used to derive other frequencies using DLL (Delay locked loops) available in SPARTAN-3 FPGA. Clock DLLs for clock distribution delay compensation and clock domain control. The interface details of clock and reset with FPGA is given in Table 14. Table 13: IO Clock-Reset Interface to FPGA
Control Bit CLOCK OSCLK RESET FPGA Pin 181 180 182

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CHAPTER 11
Power Supplies
SPARTAN-3 -IM board is provided with a regulated power supply of + 5V DC output. This supply is used to generate the required on board supply voltages. Output of the regulated power supply is given to power connector present on board. The power LED (Red LED) lights up when power is properly applied to the board.

11.1 Voltage Regulators


The list of various voltage regulators present on board are as given in Table 15. Table 14: Power Supply Details Voltage + 5 V DC + 3.3 V DC +2.5 V DC +1.2 V DC Source Generated from external power supply provided along with the SPARTAN-3 IM A regulated 3.3 V DC supply is generated on board using a voltage regulator LM317 with input voltage of 5 Volts A regulated 2.5 V DC supply is generated onboard using a voltage regulator LM317 with input voltage of 5 Volts A regulated 1.2 V DC supply is generated on board using a voltage regulator LT1963A with input voltage of 3.3V Volts

Overall, the 9V DC switching power adapter powers the board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the 2.5V and 1.2V regulators. The 3.3V regulator feeds all the VCCIO voltage supply inputs to the FPGAs I/O banks and powers most of the components on the board. The 1.2V regulator feeds to the FPGAs VCCINT voltage inputs, which power the FPGAs core logic.

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APPENDIX A
Consolidated UCF for the Complete Board
Clock and Reset
net "RESET" net "CLK_4M" net "CLK_OPT" loc = "p182"; loc = "p181"; loc = "p180";

KEYS
net net net net net net net net "RL<0>" "RL<1>" "RL<2>" "RL<3>" "SL<0>" "SL<1>" "SL<2>" "SL<3>" loc loc loc loc loc loc loc loc = = = = = = = = "p96"; "p95"; "p94"; "p85"; "p86"; "p87"; "p90"; "p93";

RS232 Interface
net net net net "RS232_RXD<1>" "RS232_RXD<2>" "RS232_TXD<1>" "RS232_TXD<2>" loc loc loc loc = = = = "p176"; "p178"; "p175"; "p172";

LCD Interface
net net net net net net net net net net net "LCD_D<0>" "LCD_D<1>" "LCD_D<2>" "LCD_D<3>" "LCD_D<4>" "LCD_D<5>" "LCD_D<6>" "LCD_D<7>" "LCD_E" "LCD_RS" "LCD_RW_BAR" loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = "p167"; "p166"; "p165"; "p162"; "p161"; "p156"; "p155"; "p154"; "p168"; "p171"; "p169";

Seven Segment Interface


net net net net net net net net "SEGA" "SEGB" "SEGC" "SEGD" "SEGDP" "SEGE" "SEGF" "SEGG" loc loc loc loc loc loc loc loc = = = = = = = = "p144"; "p143"; "p141"; "p140"; "p135"; "p139"; "p138"; "p137";

Display
net net net net net "DIS<0>" "DIS<1>" "DIS<2>" "DIS<3>" "DIS<4>" net "DIS<5>" loc loc loc loc loc loc = = = = = = "p97"; "p100"; "p101"; "p102"; "p132"; "p133";

Input Switches
net "IL<0>" net "IL<10>" net "IL<11>" loc = "p57"; loc = "p40"; loc = "p39";

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net net net net net net net net net net net net net "IL<12>" "IL<13>" "IL<14>" "IL<15>" "IL<1>" "IL<2>" "IL<3>" "IL<4>" "IL<5>" "IL<6>" "IL<7>" "IL<8>" "IL<9>" loc loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = = "p37"; "p36"; "p35"; "p34"; "p52"; "p51"; "p50"; "p48"; "p46"; "p45"; "p44"; "p43"; "p42";

Test LEDs
net net net net net net net net net net net net net net net net "OL<0>" "OL<1>" "OL<2>" "OL<3>" "OL<4>" "OL<5>" "OL<6>" "OL<7>" "OL<8>" "OL<9>" "OL<10>" "OL<11>" "OL<12>" "OL<13>" "OL<14>" "OL<15>" "IO<1>" "IO<2>" "IO<3>" "IO<4>" "IO<5>" "IO<6>" "IO<7>" "IO<8>" "IO<9>" "IO<10>" "IO<11>" "IO<12>" "IO<13>" "IO<14>" "IO<15>" "IO<16>" net "IO<17>" net "IO<18>" net "IO<19>" net "IO<20>" net "IO<21>" net "IO<22>" net "IO<23>" net "IO<24>" loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = "p68"; "p67"; "p65"; "p64"; "p63"; "p62"; "p61"; "p58"; "p80"; "p79"; "p78"; "p77"; "p76"; "p74"; "p72"; "p71"; "p184"; "p183"; "p187"; "p185"; "p190"; "p189"; "p194"; "p191"; "p197"; "p196"; "p199"; "p198"; "p203"; "p200"; "p205"; "p204"; loc = "p3"; loc = "p2"; loc = "p5"; loc = "p4"; loc = "p9"; loc = "p7"; loc = "p11"; loc = "p10";

IOs
net net net net net net net net net net net net net net net net

TRAFFIC LIGHT CONTROLLER


SIGNAL NAME net "TRC_LE" net "TRC_LN" net "TRC_LS" FPGA PIN NO. loc = "p107"; loc = "p125"; loc = "p150"; CONNECTOR J3 PINNO. #J3-20 #J3-9 #J3-25

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net net net net net net net net net net net net net net net net net net net net net net net net net "TRC_LW" "TRC_PEG" "TRC_PER" "TRC_PNG" "TRC_PNR" "TRC_PSG" "TRC_PSR" "TRC_PWG" "TRC_PWR" "TRC_RE" "TRC_REDE" "TRC_REDN" "TRC_REDS" "TRC_REDW" "TRC_RN" "TRC_RS" "TRC_RW" "TRC_SE" "TRC_SN" "TRC_SS" "TRC_SW" "TRC_YE" "TRC_YN" "TRC_YS" "TRC_YW" loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = = = = = = = = = = = = = = "p130"; "p116"; "p117"; "p128"; "p124"; "p12"; "p13"; "p148"; "p149"; "p114"; "p109"; "p120"; "p108"; "p126"; "p122"; "p111"; "p147"; "p115"; "p123"; "p152"; "p146"; "p106"; "p119"; "p113"; "p131"; #J3-6 #J3-16 #J3-15 #J3-7 #J3-10 #J3-28 #J3-27 #J3-2 #J3-1 #J3-18 #J3-22 #J3-13 #J3-21 #J3-8 #J3-12 #J3-23 #J3-3 #J3-17 #J3-11 #J3-26 #J3-4 #J3-19 #J3-14 #J3-24 #J3-5

#Abbreviations Used: #PS-G Pedestrian South Green #PS-R pedestrian South Red #RS Right South #LS Left South #SS Straight South #YS Yellow South #RED-S Red South #PW-R Pedestrian west red #PW-G Pedestrian west Green #LW Left West #SW South West #RW Right West #YW yellow West #RED-W Red West

#PN-R- Pedestrian North Red #PN-G Pedestrian North Green #RED-E Red East #YE Yellow East #SE Straight East #RE Right East #LE Left East #PE-G Pedestrian East green #PE-R Pedestrian East Red #RED-N Red North #YN - Yellow North #LN Left North #RN Right north #SN Straight North

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REAL TIME CLOCK


SIGNAL NAME net "RTC_DIS<0>" net "RTC_DIS<1>" net "RTC_DIS<2>" net "RTC_DIS<3>" net "RTC_DIS<4>" net "RTC_DIS<5>" net "RTC_SEGA" net "RTC_SEGB" net "RTC_SEGC" net "RTC_SEGD" net "RTC_SEGDP" net "RTC_SEGE" net "RTC_SEGF" net "RTC_SEGG" FPGA PIN NO. loc = "p16"; loc = "p15"; loc = "p19"; loc = "p18"; loc = "p21"; loc = "p22"; loc = "p24"; loc = "p20"; loc = "p27"; loc = "p26"; loc = "p31"; loc = "p29"; loc = "p28"; loc = "p33"; J6 CONNECTOR #J6-13 #J6-14 #J6-11 #J6-12 #J6-9 #J6-10 #J6-7 #J6-8 #J6-5 #J6-6 #J6-2 #J6-3 #J6-4 #J6-1

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APPENDIX B
Operating Instructions To Start A New Design
B.1 Starting The ISE Software:
Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE Project Navigator. DESIGN ENTRY SIMULATION SYNTHESIS IMPLEMENTATION DEVICE PROGRAMMING

B.2 Design Flow


Sample Design of Half Adder is used to explain the Design Flow.

B.3 Design Description

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B.4 Truth Table of Half adder: Inputs A 0 0 1 1 B 0 1 0 1 Sum 0 1 1 0

Output
Carry 0 0 0 1

B.5 VHDL Code for Half adder


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture Behavioral of half_adder is begin sum <= a xor b ; carry <= a and b; end Behavioral;

B.6 Steps to implement the Half adder in the FPGA using Xilinx ISE(8.1i)
Step 1 : Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE (8.1i).
SOURCE WINDOW WORK SPACE

TRANSCRIPT PROCESS WINDOW

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FPGA-01: SPARTAN - III Protoboard Step 2 Create a new project In the window go to FILE New project. Specify the project name and location and say NEXT

Select Device. Use the pull-down arrow to select the Value for each Property Name. Click in the field to access the pull-down list.

Say FINISH. Project summary is seen.

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FPGA-01: SPARTAN - III Protoboard Step 3: Creating a new VHD file Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the File name

VHDL MODULE

Then say NextDefine ports.In this case a and b are the input ports defined as in sum and carry are output ports defined as out after this say Next twice and then Finish Skeleton of the design is shown in the VHDL editor.

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Step 4:

Writing the Behavioural VHDL Code in VHDL Editor Sample code is given below for this experiment.

Step 5

Check Syntax Run the Check syntax Process window synthesizecheck syntax >, and remove errors if present.

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FPGA-01: SPARTAN - III Protoboard Step 6 Creating a test bench file Verify the operation of your design before you implement it as hardware. Simulation can be done using ISE simulator. For this click on the symbol of FPGA device and then right click Click on new source Test Bench Waveform and give the name Select entityFinish.

Select the desired parameters for simulating your design. In this case combinational circuit and Simulation time.

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FPGA-01: SPARTAN - III Protoboard Step 7: Simulate the code Simulation Tools ISE tool supports the following simulation tools: HDL Bencher is an automated test bench creation tool. It is fully integrated with Project Navigator. ModelSim from Model Technology, Inc., is integrated in Project Navigator to simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model Technology, Inc.s ModelSim application, can be installed from the MTI CD included in your ISE Tool In source Window from the Drop-down menu select Behavioural Simulation to view the created test Bench file.

FOR SIMULATION

Click on test bench file. Test bench file will open in main window. Assign all the signals and save File. From the source of process window. Click on Simulate Behavioral Model in Process window.

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Verify your design in wave window by seeing behaviour of output signal with respect to input signal. Close the ISE simulator window

SIMULATED OUTPUT

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Step 8:

Synthesize the design using XST. Translate your design into gates and optimize it for the target architecture. This is the synthesis phase. Again for synthesizing your design, from the source window select, synthesis/Implementation from the drop-down menu.

SYNTHESIS

Highlight file in the Sources in Project window. To run synthesis, right-click on Synthesize, and the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check 9will appear next to Synthesize when it is successfully completed. a red cross 8indicates an error was generated and a yellow exclamation ! mark indicates that a warning was generated, (warnings are OK). Check the synthesis report. If there are any errors correct it and rerun synthesis.

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SYNTHESIS COMPLETED SUCCESSFULLY

Step 9:

Create Constraints File(UCF) Click on the symbol of FPGA device and then right click Click on new source Implementation Constraints File and give the name Select entityFinish. Click on User Constraint and in that Double Click on Assign Package Pins option in Process window. Xilinx PACE window opens. Enter all the pin assignments in PACE., depending upon target device and number of input and outputs used in your design. (sample code is given below for given design.)

PIN ASSIGNMENT

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Step 10:

Implementing a Design Once synthesis is complete, you can place and route your design to fit into a Xilinx device, and you can also get some post place-and-route timing information about the design. The implementation stage consists of taking the synthesized netlist through translation, mapping, and place and route. To check your design as it is implemented, reports are available for each stage in the implementation process. Use the Xilinx Constraints Editor to add timing and location constraints for the implementation of your design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

IMPLEMENTATION DONE

Step 11:

Step 12

Generating Programming File Right-click on Generate Programming File, choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Downloading in Boundary Scan Mode. Note : Xilinx provides 2-tools for downloading purpose, viz. iMPACT - is a command line and GUI based tool PROM File Formatter

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BOUNDARY SCAN MODE

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Procedure for downloading using iMPACT 2. Boundary Scan Mode 1. Right click on Configure Device (iMPACT) -> and Say RUN or Double click on Configure Device (iMPACT). 2. Right click in workspace and say Initialize chain .The device is seen. 3. Right click on the device and say Program.

Step 13: Step 14:

If the device is programmed properly, it says Programming Succeeded or else. Programming Failed. The DONE Led glows green if programming succeeds. Note: Before downloading make sure that Protoboard is connected to PC's parallel port with the cable provided and power to the Protoboard is ON. Apply input through DIP Switches, output is displayed on LEDs Configuration through PROM: Generating PROM file: FPGA can also be configured in Master Serial Mode through PROM. For this you need to program the PROM through a .mcs file.

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FPGA-01: SPARTAN - III Protoboard Right click on Generate PROM,ACE or JTAG file -> and Say RUN or Double click on Generate PROM,ACE or JTAG file

Specify the PROM file name and location where it is to be generated.

Specify the desired parameters of the PROM on board and say ADD then FINISH

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Say Generate File from the Process Window.

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PROGRAMMING THE PROM


Note: Check the Jumper setting on the board. Refer the Chapter jumper Setting

Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on board are seen .Assign the generated mcs file and bit file as desired. Right click the PROM symbol and say PROGRAM.

Now, whenever the board is powered on in master serial mode, FPGA is configured through PROM automatically.

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APPENDIX C
SAMPLE CODES
Some experiments which can be implemented and verified using VLSI kit: FIFO memory. Configurable UART. Programmable timer. Functionality of keyboard with debounce logic. Functionality of 6821 where each port can act as input or output i.e. bit programmable ports. Programmable interrupt controller. Programmable Peripheral interface (8255). DMA controller Given below is a sample design for a Keyboard / Display Interface.

C.1 keyboard-display & I/O interface test code


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keydis is Port ( rst : in std_logic; Clock : in std_logic; -- keyboard return and scan lines ret_lin : in std_logic_vector(3 downto 0); scan_lin : out std_logic_vector(3 downto 0); -- display i/os segments and display selects segments : out std_logic_vector(7 downto 0); dis_sel : out std_logic_vector(3 downto 0); -- Input switches and output leds input_s : in std_logic_vector(15 downto 0); output_s : out std_logic_vector(15 downto 0) ); end keydis; -----------------------------------------------------------architecture Behavioral of keydis is -----------------------------------------------------------signal Divider : std_logic_vector(20 downto 0); signal SClock, DClock, ORed, Interrupt : std_logic; signal Scan, Decoded : std_logic_vector(1 downto 0); signal SL_S,D,Display_s : std_logic_vector(3 downto 0); ---------------------------------------begin ---------Clock Divider---------process(rst, Clock) begin if(rst = '1')then Divider <= (others=>'0'); elsif(Clock'event and Clock = '1')then Divider <= Divider + 1; end if;

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FPGA-01: SPARTAN - III Protoboard end process; -----------------Scan & Debounce clock-------------SClock <= Divider(14); DClock <= Divider(11); ------------------Scan Counter---------------------process(SClock, Rst) begin if(Rst = '1')then Scan <= (others=>'0'); elsif(SClock'event and SClock='1')then Scan <= Scan + 1; end if; end process; SL_S <= "0111" when Scan = "00" else "1011" when Scan = "01" else "1101" when Scan = "10" else "1110" ; scan_lin <= SL_S; ORed <= (not ret_lin(0)) or (not ret_lin(1)) or (not ret_lin(2)) or (not ret_lin(3)); process(Rst,DClock) begin if(Rst = '1')then D <=(others => '0'); elsif(DClock'event and DClock = '1')then D <= D(2 downto 0) & ORed; end if; end process; Interrupt <= '1' when(D = "1111")else '0'; Decoded <= 00" when (ret_lin = "0111") else "01" when (ret_lin = "1011") else "10" when (ret_lin = "1101") else "11"; process(Interrupt, Rst) begin if(Rst = '1')then Display_s <= (others=>'0'); elsif(Interrupt'event and Interrupt = '1')then Display_s <= Scan & Decoded; end if; end process; ------------------------------------------------------------- .a. -- f| |b -- .g. -- e| |c -- .d. -Segments dphgfedcba <= "01000000" when Display_s ="0000" else --0 "01111001" when Display_s ="0001" else --1 "00100100" when Display_s ="0010" else --2 "00110000" when Display_s ="0011" else --3 - 58 VLSI Training System

FPGA-01: SPARTAN - III Protoboard "00011001" when Display_s ="0100" else --4 "00010010" when Display_s ="0101" else --5 "00000010" when Display_s ="0110" else --6 "01111000" when Display_s ="0111" else --7 "00000000" when Display_s ="1000" else --8 "00010000" when Display_s ="1001" else --9 "00001000" when Display_s ="1010" else --A "00000011" when Display_s ="1011" else --B "01000110" when Display_s ="1100" else --C "00100001" when Display_s ="1101" else --D "00000110" when Display_s ="1110" else --E "00001110" when Display_s ="1111" else --F "01000000"; dis_sel <= (others=>'0'); -- test input switches and output leds output_s <= input_s; end Behavioral; For Pin Locking refer the pin out diagram of the specific adapter and the device used on that adapter.( Refer -APPENDIX.A ) UCF for above code Net "CLOCK" loc = p181; Net "RST" loc = p182; Net "ret_lin<0>" loc = p94; Net "ret_lin<1>" loc = p93; Net "ret_lin<2>" loc = p90; Net "ret_lin<3>" loc = p87; Net "scan_lin<0>" loc = p86; Net "scan_lin<1>" loc = p85 Net "scan_lin<2>" loc = p80; Net "scan_lin<3>" loc= p79; ; # DISPLAY SELECTION Net "dis_sel<0>" loc = p106; Net "dis_sel<1>" loc = p107;; Net "dis_sel<2>" loc = p108 Net "dis_sel<3>" loc = p109; Net "dis_sel<4>" loc = p137 Net "dis_sel<5>" loc = p138; Net "segments<0>" loc = p111; Net "segments<1>" loc = p113; Net "segments<2>" loc = p114; Net "segments<3>" loc = p115; Net "segments<4>" loc = p116; Net "segments<5>" loc = p117; Net segments<6>" loc = p119; Net "segments<7>" loc = p120;

Input switches Output LEDs Net "IL<0>" loc =p102; Net "OL<0>" loc = p65; Net "IL<1>" loc =p101; Net "OL<1>" loc = p64; Net "IL<2>" loc =p100; Net "OL<2>" loc = p63; Net "IL<3>" loc = p97; Net "OL<3>" loc = p62; Net "IL<4>" loc = p96; Net "OL<4>" loc = p61; Net "IL<5>" loc = p95; Net "OL<5>" loc = p58; Net "IL<6>" loc = p51; Net "OL<6>" loc = p57; Net "IL<7>" loc = p50; Net "OL<7>" loc = p52; Net "IL<8>" loc = p39; Net "OL<8>" loc = p78; Net "IL<9>" loc = p40; Net "OL<9>" loc = p77; Net "IL<10>" loc =p42; Net "OL<10>" loc = p76; Net "IL<11>" loc =p43; Net "OL<11>" loc = p74; Net "IL<12>" loc =p44; Net "OL<12>" loc = p72; Net "IL<13>" loc =p45; Net "OL<13>" loc = p71; Net "IL<14>" loc =p46; Net "OL<14>" loc = p68; Net "IL<15>" loc =p48; Net "OL<15>" loc = p67; After this go for Implementation Procedure. Downloading the Program into target Device.

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