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A 30-mA CMOS Low Dropout Regulator for WiMAX Analog Front Ends with 50 dB PSRR at 10 MHz
Joseph Sankman and Dongsheng Ma
Integrated System Design Laboratory Texas Analog Center of Excellence (TxACE) The University of Texas at Dallas, Richardson, TX 75080 Email:
Abstract While the application space for WiMAX has seen fast growth in recent years, on-chip digital circuits and high frequency switching converters have resulted in power supply noise with high frequency spectral content, which jeopardizes the reliability of sensitive WiMAX analog front ends. As a costeffective solution, this paper presents a low dropout (LDO) regulator design, which achieves high PSRR at 10 MHz. The LDO is implemented and verified in a CMOS 0.25-m process. With a 3-V input power supply, it provides a 2.8-V regulated output with a PSRR of 76 dB at 1 kHz and 50 dB at 10 MHz. The target maximum load current is 30 mA for this application.


Fig. 1. Block diagram of high PSRR LDO without multiple amplifiers or cascoded pass device.

The use of wireless devices has seen significant growth in recent years. As a popular example, the Worldwide Interoperability for Microwave Access (WiMAX) offers tremendous opportunities for broadband wireless applications, specifically consumer-premises equipment and portable devices [1]. In general, a WiMAX analog front end (AFE) contains many noise sensitive analog and RF elements, which must be well isolated from noisy digital circuit blocks and other disturbances on the power supply [2]. Commonly, a switching converter, working as a preregulator, is employed to convert a high input voltage of a battery or other power sources to a low on-chip DC voltage. Such a switching converter is desired to operate at high switching frequency to reduce the size of off-chip components, such as inductors and output filtering capacitors, which, however, results in supply noise high in the frequency spectrum. As a result, an LDO with the capability to reject high frequency noise is required for post-regulation so that clean and less noisy power can be delivered to the WiMAX AFE. Typically, the power supply rejection ratio (PSRR) of an LDO is determined by the gain and bandwidth of the LDO, the output capacitor, the equivalent series inductance (ESL) and the equivalent series resistance (ESR) of the output capacitor as well as the bond wire inductance [3]. At low frequencies, power supply noise can be rejected by the error amplifier itself. However, at high frequencies, the noise reaches beyond the error amplifier bandwidth.

The output capacitor shorts high frequency power supply noise to ground. However, in the mid-range frequency band, neither the error amplifier nor output capacitor can reject the supply noise well, which causes a significant drop on the PSRR of the LDO. Previous designs improve PSRR by using cascoded pass devices [4, 5] or multiple high bandwidth amplifiers for supply ripple feed forward paths [2, 6]. However, cascoded pass devices improve PSRR at the cost of a significant silicon area increase, a degraded transient performance, and the requirement of a second high voltage supply rail (if an NMOS cascaded power transistor is used). Once again, this second supply rail, usually generated by an on-chip charge pump, consumes more silicon area and potentially contributes more switching noise to the system. On the other hand, the supply ripple feed-forward approaches requires more amplifiers and large on-chip compensation capacitors. Hence, due to cost and complexity concerns, as shown in Fig. 1, a LDO with a single PMOS pass device and a single error amplifier would be highly desirable. To mitigate the aforementioned issues, this paper proposes a simple LDO that employs a low noise error amplifier and voltage-to-current and current-to-voltage converters to achieve high PSRR. The rest of the paper is organized as follows. Section II introduces the proposed design and simulation results are presented in Section II. Finally, the paper is concluded in Section IV.

978-1-4673-1000-0/12/$31.00 2012 IEEE


Fig. 2. Circuit schematic of the proposed LDO. Low VTH devices are indicated by blue stripes.

II. PROPOSED DESIGN A. LDO Design Overview To battle the drawbacks of the previously published concepts, an error amplifier followed by a voltage-to-current converter and current-to-voltage converter (labeled as V-to-I and I-to-V respectively in Fig, 2) to drive the pass device is proposed. Additionally, a novel high PSRR error amplifier with adaptive gain compensation is introduced to maintain stability at all loading conditions. In this approach, the PSRR performance is vastly improved across all frequencies. The complete schematic is shown in Fig. 2. The LDO operates on a 3-V supply and regulates the output at 2.8 V. The voltage-to-current converter is formed by transistors M6 and M6L in Fig. 2, and is controlled by the error amplifier, which is composed of transistors M1M5 and MB2MB3. The voltage-to-current converter has high output impedance, meaning that the current it sinks is insensitive to voltage ripples on its output (the drain of M6L). Only the error amplifier affects the current that the voltage-to-current converter sinks. The current-to-voltage converter is M8, with its source connected to the supply and its gate connected to the gate of the pass device, MP. The voltage-to-current converter sinks a supply independent current through M8 to maintain constant VGS. Thus, any fluctuations at the source of M8 are replicated on the gate of M8 to keep its VGS constant. Since the gates of M8 and MP are connected, supply ripples are replicated on the gate of MP, maintaining the VGS of MP at a constant value. The transistor M7 in Fig. 2 provides another supply noise path to the gate of MP to maintain the VGS of MP. The purpose of the level shifter, formed by M9 and RLVL, is to ensure that the VGS of M7 is not large, which would result in a large current dissipation through M7, thus reducing efficiency.

Fig. 3. Supply noise paths in a conventional two-stage amplifier.

B. Circuit Design & Implementation 1. Error Amplifier The design of the error amplifier requires careful consideration of how power supply noise enters the signal path. First, let us examine a conventional two-stage amplifier that consists of a differential-input, single-ended-output first stage and a common source second stage amplifier shown in Fig. 3. The first stage, composed of M1A,B and M2A,B, is relatively immune to power supply noise because at the output, the power supply noise is added with power supply noise that is shifted by 180o. However, the second stage, formed by M3 and MB3, does not have this feature because it is not differential. Assuming that MB3 is biased with a supply independent source, the supply noise at the output of the conventional two-stage amplifier is derived from the voltage divider of the output impedances of M3 and MB3. Assuming that the output impedances of the devices are approximately equal, the best case PSRR of a conventional two-stage amplifier in open-loop is 3 dB.


Fig. 4. Proposed error amplifier with enhanced supply noise rejection and adaptive gain compensation. Low VTH devices are indicated by blue stripes.

To overcome poor PSRR, [7] presents a single-stage, highgain, high-bandwidth amplifier to achieve high PSRR performance. However, this amplifier has a major drawback due to its limited output swing. The amplifier can swing up to VDD 2VOV, but is limited to a low swing of VT + 2VOV. This means that the amplifier has a very small region in which it operates in the small-signal domain. In light-load situations, the amplifier moves out of its desired operating region. Thus, to overcome the limitations of the conventional twostage amplifier and the swing limitations of the amplifier in [7], a novel two-stage amplifier with two differential-input stages is proposed. The proposed amplifier achieves a large swing along with excellent supply noise rejection. A detailed illustration of the amplifier with supply noise paths indicated is shown in Fig. 4. The first stage of the amplifier is a differential-input, differential-output topology, composed of transistors M1A,B, M3A,B, and M4A,B in Fig. 4. Thus, any supply noise that is conducted through the tail current source, MB2 and MB2L, appears at both outputs (drains of M1A and M1B) of the differential amplifier. The second stage of the amplifier is a differential-input, single-ended output topology, formed by M2A,B, and M5A,B in Fig. 4, which converts the differential output of the first stage in a single-ended output. Since the same noise is presented at both inputs, it is rejected as common-mode noise. The supply noise that is conducted from the tail current source of the second stage, MB3 and MB3L, is cancelled out due to the phase shift through half of the amplifier. Supply noise is amplified through the common-gate amplifier formed by M2B, but the same supply noise is amplified through the common gate amplifier M2A and the common source amplifier, M5B. As a result of the 180o phase shift from the common source amplifier, noise that is equal and opposite is summed with the noise through M2B, thus cancelling it. Ideally, very little supply noise is propagated through the amplifier.

Fig. 5. Gain plots at heavy and light load of (a) the proposed LDO without adaptive gain compensation and (b) the proposed LDO with adaptive gain compensation.

Frequency Compensation The compensation of the proposed LDO is more difficult that the compensation of a conventional LDO. In a conventional LDO, where the error amplifier directly drives the gate of the pass device, the dominant pole is determined by the load capacitance and load resistance, and the second pole is determined by the pass device gate capacitance and error amplifier output impedance. Thus, only the dominant pole should move significantly with changes in the load current. This makes compensation of the conventional LDO simpler since only one of the two poles moves in response to changes in the load current. However, in the proposed topology, the second pole location now is determined by the ratio of the transconductance of M8 and the gate capacitance of the pass device. At light load, the transconductance of M8 becomes very small, and since the gate capacitance of the pass device does not change, the second pole of the LDO is pushed to a significantly lower frequency. The movement of the dominant pole and the second pole is illustrated in Fig. 5(a). Normally, a zero created by the output capacitor and its ESR is used to cancel the second pole in a conventional LDO, but because the second pole changes position, the zero only cancels the pole at one loading condition. As shown in Fig.



5(a), the zero can be positioned to cancel the second pole at heavy load, but not at light load conditions. Because of the fixed position of the zero, despite changes in load current, the movement of the second pole threatens the stability of the system. Thus, a new method of compensation is paramount to ensure stable response at light and heavy loads. To overcome this stability problem, an adaptive gain compensation technique is employed to ensure stability over all load conditions. The transistors, M3A and M3B, illustrated in Fig. 4, are used to adaptively change the gain of the first stage in the error amplifier. M3A and M3B, also shown in Fig. 4, current starve transistors M4A and M4B depending on the output voltage of the amplifier, which in turn changes the output impedance seen by the first stage amplifier. For example, if the load current increases, the output voltage (the drain voltages of M2B and M5B in Fig. 4) of the error amplifier increases. In turn, this increases the current starving, which increases the output impedance of the first stage and increases its gain. At the same time, the second pole is pushed out and can be cancelled by the capacitor ESR zero. However, as the load current decreases, the error amplifier output voltage decreases, thus reducing the current starving effect. This reduces the gain sufficiently so that the second pole is beyond the unity gain bandwidth. This effect is shown in Fig. 5(b). If not for the reduction in gain, the second pole would degrade the phase margin of the LDO. The trade-off of using this approach is that the unity-gain bandwidth of the system is dramatically reduced at light loads since the DC gain of the error amplifier is reduced.

Phase (Degrees)

Loop-Gain (dB)

Fig. 7. Loop-gain and phase of the proposed LDO at 30-mA load.

35 30 Load Current (mA) Voltage (V) 25 20 15 10 5 0 2.799 2.799 2.798 2.797 2.796 2.795 2.794 2.793 0 50 100 150 Time (s) 200 250 300



Fig. 8. Load transient responses for 1% to 100% and 100% to 1% load current changes. Load steps occur in 30 ns.

Fig. 6. Plot of the PSRR of the proposed LDO at a 30-mA load.

The proposed design is verified based on fully transistorlevel simulations in a CMOS 0.25-m process. The LDO operates nominally with a 2.2-F output capacitor and up to 60 m of capacitor ESR. It consumes 92 A at a load of 300 A and consumes 205 A at a maximum load of 30 mA. The dropout voltage is 230 mV.

The PSRR performance of the proposed LDO against frequency is shown in Fig. 6. At low frequencies, the PSRR is 76 dB. The mid-range frequencies, where neither the error amplifier nor output capacitor rejects supply noise is slightly below 1 MHz. At 10 MHz, the PSRR is 50 dB. In addition, the LDO achieves the simulated PSRR performance with 2 nH of bond wire package inductance and 1.2 nH of capacitor ESL. From the Bode plot in Fig. 7, the phase margin of the LDO is 63o and the gain margin is 34 dB. These values indicate good stability of the LDO. The load transient response of the proposed LDO is shown in Fig. 8. Load steps are performed from 300 A to 30 mA and from 30 mA to 300 A. The step time for each load step is 30 ns. The observed undershoot is 1.7 mV and the observed overshoot is 1.2 mV.


Table 1. Performance comparison of the proposed design with prior art. Technology VIN (V) VOUT (V) Dropout (V) Max. Load (mA) IQ (A) PSRR (dB) [2] 0.13-m > 1.15 1 0.15 25 50 60 @ 100-kHz 67 @ 1MHz 56 @ 10MHz 4 30 0.4 0.048 26 15 (over) 1.2 (under) [5] 0.13-m >3 2.8 0.19 150 98 (noload) 57 @ 100-kHz 40 @ 1MHz -- @ 10MHz 1 10 3.5 (over) 15.8 (under) [7] 90-nm > 1.15 1 0.15 140 33 to 145 53 @ 100-kHz 62 @ 1MHz 56 @ 10-MHz 6 0.043 24 (over) 70 (under) [8] 0.35-m > 3.3 3 0.3 25 40.6 to 76.8 55* @ 100-kHz 47 @ 1MHz 66 @ 10-MHz 5 2 Proposed 0.25-m > 3.03 2.8 0.23 30 92 to 205 72 @ 100-kHz 60 @ 1MHz 50 @ 10MHz 2.2 60 1.2 0.073 1.2 1.2 (over) 1.7 (under) [6] [1]

S. Vaughan-Nichols, Mobile WiMax: The Next Wireless Battleground? IEEE Computer Society, Computer, vol. 41, no. 6, pp. 1618, Jun. 2008. M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. SanchezSinencio, High PSR low drop-out regulator with feed-forward ripple cancellation, IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 565577, Mar. 2010. V. Gupta, G. A. Rincn-Mora, and P. Raha, Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications, in Proceedings of the IEEE International System on Chip (SOC) Conference, pp. 311315, Santa Clara, California, 2004. V. Gupta and G. A. Rincn-Mora, A 5 mA 0.6 m CMOS Miller compensated LDO regulator with -27 dB worst-case power-supply rejection using 60 pF of on-chip capacitance, in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb. 2007, pp. 520521. K. Wong and D. Evans, A 150mA Low Noise, High PSRR LowDropout Linear Regulator in 0.13m Technology for RF SoC Applications, in Proceedings of the IEEE European Solid-State Circuits Conference ESSCIRC, Montreux, Switzerland, Sept. 2006, pp. 532535. C. Zheng and D. Ma, Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 686690, Sept. 2010. A. Amer and E. Sanchez-Sinencio, A 140mA 90nm CMOS lowdropout regulator with -56dB power supply rejection at 10MHz, in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sept. 2010, pp. 14. S. Yeung, L. Guo, and K.N. Leung, 25 mA LDO with -63 dB PSRR at 30 MHz for WiMAX, IET Electronic Letters, vol. 46, no. 15, pp. 10801081, July 2010.




Load Cap. (F) Cap. ESR (m) Cap. ESL (nH) Load Reg. (mV/mA) Line Reg. (mV/V) Load Transient (mV)



* - Interpolated from figures.

In comparison with prior art from Table 1, the proposed design achieves comparable PSRR performance with up to a factor of 2.7 times less output capacitance [7], tolerating up to 30 times as much capacitor ESR [8], and a factor of 3 times more capacitor ESL [2]. Additionally, the proposed design achieves excellent load and line regulation performance as well as minimal load transient overshoot and undershoot in comparison with other designs. IV. CONCLUSIONS


A high PSRR LDO has been proposed for WiMAX analog fronts ends, in which an error amplifier has been proposed in combination with a voltage-to-current and current-to-voltage converter to achieve high PSRR with a PMOS pass device. In comparison with the prior art, this design demonstrates better transient performance and demands less silicon real estate, since neither cascoded pass device nor multiple amplifiers are required. The proposed design achieves 50 dB PSRR at 10 MHz with significant parasitic output capacitor ESR and ESL.