A low noise, high PSR low-dropout regulator

for low-cost portable electronics

Karim EL KHADIRI and Hassan Qjidaa
Universit Sidi Mohamed Ben Abdellah
Facult des sciences Dhar El Mehraz
Laboratoire dElectronique Signaux Systmes et Informatique(LESSI)
Fes, Morocco
Karim_elkhadiri@yahoo.fr

Abstract This paper presents A low noise, high PSRR low-
dropout regulator for low-cost portable electronics. The
proposed LDO uses an Operational Transconductance Amplifier
(OTA) with Miller R-C compensation to ensure a stable phase
margin greater than 62. The active chip of the proposed
regulator is only 150680 um2. The design was simulated and
lyouted in Cadence using mixed-signal 90 nm 2P9M CMOS
process, the simulation results show that this LDO output voltage
can achieves line regulation of less than 0.10% and load
regulation of better than 0.25% and a low quiescent current of
only 90uA and ultra-low noise of only 65 nV/SqrtHz. Moreover,
it can achieve a PSRR of-52 dB and -64dB at 1and 10 kHz,
respectively. The input voltage is ranged from 2.70 to 5V for a
load current 100mA and an output voltage of 1.5V.
Keywords-component; LDO regulator, Low Voltage, High PSRR,
Low noise, Quiescent Current.
I. INTRODUCTION

The LDO (low-dropout) regulator is generally utilized to
translate a voltage level or provide a stable output voltage,
which has been considered as one of the most important
components for the power management of wireless
applications ,e.g., cellular phones, handheld computers [1].
Electronics systems, which need a large base-band
frequency to work (100 kHz bandwidth), like new wireless
receiver, are very sensitive to the noise present on power
supply. Consequently, they need large battery filters to reduce
the ripple on battery voltage. To reduce the cost and the area of
those battery filters, 100 kHz bandwidth high performance
PSRR regulators are required. Thus, low drop out regulators
are implemented in most sensitive circuit applications to
provide regulated power supply.
Furthermore, such regulators have to be designed in
standard low-cost CMOS process, which makes them difficult
to realize.
LDO voltage regulators result in a small voltage drop
across the power transistor and provide a well regulated low-
noise voltage. These are particularly suitable for portable
electronics portable applications, which require low noise [2,
3]. In portable devices, a crucial design consideration is
reducing quiescent current to maximize the lifespan of the
battery [4, 5, 6]. The damping frequency compensate on
technique provides high PSRR in [7], but the regulator is
unstable at low load current.
A low drop out regulator in standard CMOS process,
with new dynamic compensation, low-noise, high open-
loop gain, and high-PSRR is introduced in this article. This
regulator has a small silicon area because it uses a very
low 0.5pF internal compensation capacitor.
II. LDO CIRCUIT DESIGN
The block diagram of the proposed LDO is shown in Fig.1.
which is composed of a reference voltage bandgab, an input
stage, an output voltage trimming, a compensation network, a
low output-impedance buffer stage, a power transistor (MP), a
gain and offset control circuit.

A. Bandgap reference

To generate a stable voltage against process and temperature
variations, a bandgap reference circuit is adapted [8]. To
enhance the capability against the supply voltage variation and
the noise coupling from the substrate, a feedback loop with an
error amplier (EAB) is used as shown in Fig.2. Assuming the
gain of the EAB is very large, Vx and Vy are approximately
equal, where Vy and Vx are the voltages at the inverting and
non inverting input terminals of EAB, respectively.
Suppose that EAB is ideal and that the counterpart resistors are
equal, such that INP = INN, R
a1
= R
a2
and R
b1
= R
b2
; now, I
Ra1

= I
Ra2
. Therefore,
I
Ru2
= I
Rb2
+ I
R2
= I
Rb1
+ I
R2
(1)

Where I
Ra2
, I
Rb2
, I
R2
, and I
Rb1
are the currents through R
a2
, R
b2
,
R2 and Rb1, respectively. Differentiating Eq. (1) with respect
to temperature (T) yields
oI
Ru2
oI
=
oI
Rb2
oI
+
oI
R2
oI
(2)
If a temperature-independent current reference I
Ra2
is required,
I
Rc2
1
= u is set; thus,
I
Rb2
1
+
I
R2
1
= u (3)
where I
Rb2
is a negative-TC current because I
Rb2
= I
Rb1
=
v
BE1
R
b1

whereas I
R2
is a positive-TC current because I
R2
= (I
R2
=
(I
BL1
I
BL2
)R
2
=
vLB
R2
Combining the first differential
978-1-4799-0792-2/13/$31.00 2013 IEEE
item,
I
Rb2
1
, with the second differential item,
I
R2
1
, yields a
temperature-independent current I
Ra2
.
The voltage reference Vref associated with the bandgap
reference can be expressed as, Irc = I
LB3
+ I
R3
R
3
(4)
where V
EB3
is the emitter to base voltage of the BJT Q
3
and
I
R3
is the current through resistor R
3
which is a temperature-
independent current. Differentiating the above equation with
respect to temperature (T) yields
oI
c]
oI
= R
3

oI
R3
oI
+ I
R3

oR
3
oI
+
oI
BL
oI
(S)
A temperature-independent bandgap reference is obtained
by setting
v
rc]
1
u anu
I
R3
1
u Therefore,
I
R3

oR
3
oI
+
oI
BL
oI
= u (6)
Where R
3
is a positive-TC resistor, whereas V
EB3
is a negative-
TC voltage. Properly setting the value of R
3
yields a
temperature-independent voltage reference,
v
rc]
1
u .
Notably, R
3
not only compensates for the temperature variation
of V
EB3
, but also adjusts the output voltage as required.

B. Input Stage (OTA)

In order to reduce the noise from VIN, Operational
Transconductance Amplifier (OTA) architecture is
implemented in Fig. 1. The PMOS and NMOS devices is used
and optimized for differential pair and current mirrors in term
of noise, input offset and good matching. For low noise an
additional 5uA sink current (M11, M12, M13, M14) can be
used to increase the current in the differential pair, such as to
reduce its noise contribution.

C. Gain Control and Input-Offset

The first pole of the LDO is made by the output of the first
stage. We use a resistor (400kOhm) in series with M48 diode-
connected transistor (1/gm) to control the output impedance of
the first stage, and thus to control the gain of the first stage.
A positive feedback loop (gain=4/5) permits to reduce the input
offset voltage, by reducing the dc current which goes into the
output of the first stage so input offset voltage can be greatly
reduced, without reducing the stability of the open loop and
improves greatly the DC line, load and temperature regulation.

D. Low Output-Impedance Buffer Stage

The parasitic pole which is constituted by the input capacitance
of the power PMOS is made at higher frequency, by reducing
the impedance of the node common drain circuit and three
series diodes (M54, M55, M56) clamp the VGS of the power
PMOS during the startup of the LDO. In bypass mode, a small
current is sink into these three series diodes, such as to force a
VGS for the power PMOS, and have VOUT=VDD-Vdrop.

E. Stability and PSRR analysis

For stability analysis of the feedback loop, small signal
equivalent circuit of the proposed on-chip LDO is shown in
Fig. 3, where Gm is the transconductance of the input
differential pairs, R0, C0 are the resistor and capacitor at the
OTA output. C
out
is the on-chip output capacitor at the output
of the LDO.
The small signal loop gain at low frequency can be given as
bellow

A
Lu
= A
01A
A
P
= 0
m
R
0
g
mP
[
1
gdsP
(R
1
+ R
2
)
R
1
R
1
+R
2
(7)

Where A
OTA
and A
P
are the voltage gain of the OTA and pass
transistor respectively, g
mP
the transconductance of the pass
transistor.
The dominant and non-dominant poles of the feedback loop
can be given as

d
=
1
2n R
0
C
c
(8)

nd
=
1
2n _
1
gJsP
(R
1
+ R
2
)] C
out
(9)

The gain bandwidth product (GBW) of the feedback loop can
be obtained from equations (7) and (8)
0Bw = A
Lu

d
=
u
m
A
P
[
2nC
0
(10)
Since the operating state of the pass transistor is dramatically
changed with the load current, the small signal gain of the pass
transistor A
P
and the capacitor C
0
at the OTA output are
dramatically affected. Correspondingly, the non-dominant pole
f
nd
locating at the LDO voltage output will change with load
current, degrading the stability of the feedback loop.
To ensure the stability of the feedback loop and improve
the transient response, a Miller R-C compensation adopted for
the worst case frequency compensation. The non-dominant
pole f
nd
should be 2 times beyond the GBW given as bellow,
1
2n [
1
gdsP
(R
1
+R
2
)C
cut
> 2
u
m
A
P
[
2nC
0
(10)

The simulation demonstrates that the capacitor should be 0.5pF
and resistor 125K Ohm for a minimum load current of 100A.
The simulated frequency response of the feedback loop with
Miller compensation is given in Fig. 5,
The LDO voltage regulator with a high PSRR over a wide
frequency range shields noise-sensitive blocks from high
frequency ripples in the power supply [4]. However, several
paths between the input and output voltage of the LDO voltage
regulator cause finite PSR over a limited frequency range [9].
Considering the direct path through the transconductance gmP
and conductance gdsP of the pass transistor, The PSRR of the
proposed LDO voltage regulator can be approximately given as

PSRR =
1 + A
P
1 +
1
g
dsP
(R1 + R2)
+
1
sC
out
+
A
Lu
1 +
s
2nJ
,
(11)

To obtain a high PSRR over a wide frequency range, both high
loop gain and dominant pole of high frequency have to be
realized at the same time.





























































Fig.1. Architecture of the proposed low noise low dropout regulator




















Fig.2. The schematic of bandgap reference Fig. 3. Small signal equivalent circuit
EAB
VSS
VDD
Vy Vx
Rb3
R3
Q3
M6
M5
M4 M3
Q1
Rb2
Ra1
M1 M2
Ra2
R2 Rb1
Q2
Vref
Vout
-gmP
gnd
R2
Cout
R1
C0
R0
R3
VFB
Vin
Gm
Cout
Compensation Network
Power
Transistor
LowOutput-Impedance Buffer
Input Satge (OTA)
M31
M29
M21
M15
M55
MP
M46
M47
M48 M49
M44
M37 M43
M39
M40
M41
M42
M26
M20
M18
M13 M14
M11 M9 M10
M7
M8
M4
M3
M1 M2
M6
M5
M12 M17
M19 M25
M28
M27
NOISE_LOW
IBIAS
M38 M36
M50
M52
M51
M54
M56
OLIN
OLOUT
OUTPUT
VDD
M16
M24
M23
M22
VSS
M30
M32
MOSCAP
Gain and Offset Gain Control
Referance
Voltage
Bandgap
(1.2)
Il oad
III. SIMULATION RESULTS
The LDO regulator was designed using
technology. Figure 4 shows the layout of the proposed LDO
regulator, with an area of 0.1mm
2
, including feedback resistors.
The DC load and line regulation performance of the LDO
regulator are 0.10% and 0.25%, respectively.
the proposed LDO regulator performance is shown in
The input voltage ranges from 2.7 to 5V. The quiescent current
is only 90 uA. The power supply rejection ratio (PSRR) is less
than -52dB for frequencies up to1kHz. The
noise at100Hz is approximately 65 nV/SqrtHz.












Fig.4. Layout of the proposed LDO














Fig.5 Typical Curve Open-Loop transfert function















Fig.6 Typical Curve PSRR
IMULATION RESULTS
The LDO regulator was designed using 90nm CMOS
Figure 4 shows the layout of the proposed LDO
, including feedback resistors.
The DC load and line regulation performance of the LDO
respectively. A summary of
the proposed LDO regulator performance is shown in Table1.
The quiescent current
The power supply rejection ratio (PSRR) is less
equivalent output
nV/SqrtHz.
Loop transfert function
Typical Curve PSRR




















Fig.7 Typical Curve Output Noise












Fig.8 Typical Curve DC Line Regulation
















Fig.9 Typical Curve DC load Regulation

Typical Curve Output Noise




Typical Curve DC Line Regulation
Typical Curve DC load Regulation


















Fig.10 Typical Curve DC temperature regulation
IV. CONCLUSION

In this paper, a low noise, high PSRR low-
was presented. The proposed LDO is simulated using Cadence
Spectre simulator in a 90 nm 2P9M, CMOS
simulation results justify its low noise, low quiescent current,
ultra-low noise, high PSRR low dropout linear r
proposed LDO does not need large off-chip capacitor and is
thus suitable for portable electronics.

Table 1. Performance parameters

Parameters Simulation Result
VIN 2.7V to 5V
VOUT 1.5V
Quiescent current 90uA
Dropout voltage 100mV
Load regulation 0.25%
Line regulation 0.10%
Layout 0.1mm
2

















Typical Curve DC temperature regulation

-dropout regulator
imulated using Cadence
CMOS process. The
low quiescent current,
low noise, high PSRR low dropout linear regulator. The
chip capacitor and is
Result

ACKNOWLEDGMENT

This work was supported by: le Centre National de la
Recherche Scientifique et Technique (CNRST Maroc)
the TIC R&D program.
REFERENCES

[1]. R.J. Baker, H.W. Li, D.E. Boyce, CMOS circuit design, layout, and
simulation, in: Proceedings of the 15th International Conference on
Electronics, Circuits and Systems, August 2008, pp.1047
[2]. Huang, W.-J., & Liu, S.-I.(2011). A PSRR
regulator. IET Electronics Letters, 47(1),17
[3]. Wong, K., & Evans, D. (2006). A 150mA low noise, high PSRR low
dropout linear regulator in 0.13 lm technology for RF SoC applications.
In Proceedings IEEE European solid
(ESSCIRC), Sep 2006, pp. 532535.
[4]. Rincon- Mora, G.A.,& Allen, P.E. (1998). A low
current, low drop-out regulator. IEEE Journal of Solid
Circuits,33(1),3644.
[5]. Lin, C.-H., Chen, K.-H. , & Huang
regulators with adaptive reference
techniques for enhancing transient
Power Electronics, 24(4), 10161022.
[6]. Garimella, A., Rashid, M.W.,
miller compensation using current
Transactions on Circuits and Systems
250254.
[7]. Leung, K. N., & Mok, P. K. T.
dropout regulator with damping-
IEEE Journal of Solid-State Circuits,
[8]. S. Hui, W. Xiaobo, Y. Xiaolang, A precise bandga preference with high
PSRR, in: Proceedings of the Seventh IEEE International Conference on
Electron Devices and solid-State Circuits, December 2005, pp.267
[9]. Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari,
and E. Snchez-Sinencio, High PSR Low Drop
Feed-Forward Ripple Cancellation Technique, IEEE J. Solid
Circuits, vol. 45, NO.3, pp. 565577, Mar. 2010











ACKNOWLEDGMENT
d by: le Centre National de la
Recherche Scientifique et Technique (CNRST Maroc) under
EFERENCES
H.W. Li, D.E. Boyce, CMOS circuit design, layout, and
simulation, in: Proceedings of the 15th International Conference on
Electronics, Circuits and Systems, August 2008, pp.10471050.
I.(2011). A PSRR-enhanced low-dropout
IET Electronics Letters, 47(1),1718.
Evans, D. (2006). A 150mA low noise, high PSRR low-
dropout linear regulator in 0.13 lm technology for RF SoC applications.
In Proceedings IEEE European solid-state circuits conference
535.
Mora, G.A.,& Allen, P.E. (1998). A low-voltage, low quiescent
out regulator. IEEE Journal of Solid-State
& Huang, H.-W. (2009). Low-dropout
rence control and dynamic push-pull
transient performance. IEEE Transactions on
1022.
& Furth, P.M. (2010).Reverse nested
current buffers in a three-stage LDO. IEEE
Systems Part II: Express Briefs, 57(4),
T. (2003).A capacitor-free CMOS low-
-factor control frequency compensation.
Circuits, 38(10), 16911702.
S. Hui, W. Xiaobo, Y. Xiaolang, A precise bandga preference with high
PSRR, in: Proceedings of the Seventh IEEE International Conference on
State Circuits, December 2005, pp.267270.
Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari,
Sinencio, High PSR Low Drop-Out Regulator With
Forward Ripple Cancellation Technique, IEEE J. Solid-State
577, Mar. 2010