Code No: L0424

R07

Set No. 1

IV B.Tech. II Semester Regular Examinations, April, 2011

DSP PROCESSORS AND ARCHITECTURES

(Common to Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Bio-Medical Engineering) Time: 3 Hours Max Marks: 80

Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) Elaborate the sampling process used in Digital Signal Processing with relevant example. [8] (b) Give the representation of a linear time-invariant system and explain the terms, convolution, Z-Transform and The system function related to LTI System. [8] 2. (a) Define the terms Dynamic Range and Precision related to computational accuracy and give their significance for various number representations. [8] (b) Describe the A/D conversion errors for evaluating computational accuracy in DSP implementations. [8] 3. (a) Draw and explain the block diagram of a barrel shifter and present the implementation of a 4-bit shift-right barrel shifter. (b) Explain the basic architectural features for programmable DSP devices. 4. (a) Explain the interrupts activation during the process of execution control in DSP processors. (b) Illustrate the pipeline programming models with suitable examples. 5. With suitable example, explain the following relevant to TMS320C54XX Digital Signal Processors. (a) Instructions and Programming (b) (b) Pipeline operation

[8] [8]

[8] [8]

[16 ]

1 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 1

6. (a) What is meant by Q-notation? Explain the concept of multiplication of numbers represented using the Q-notation. (b) Write notes on decimation filters and give the digital decimation filter implementation with a decimation factor three and a low pass filter of length five.

[8]

[8]

7. (a) Draw a general DIT FFT butterfly in-place computation structure and explain its importance in DSP implementations. [8] (b) Draw an 8-point DIT FFT implementation structure based on a butterfly computation for TMS320C54xx Digital Signal Processors. [8] 8. (a) With neat sketch, explain how the Direct Memory Access is going to be interfaced to programmable DSP devices. (b) Explain a CODEC-DSP interface with suitable example.

[8] [8]

2 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 2

IV B.Tech. II Semester Regular Examinations, April, 2011

DSP PROCESSORS AND ARCHITECTURES

(Common to Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Bio-Medical Engineering) Time: 3 Hours Max Marks: 80

Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) Give the various discrete time sequences available in DSP for analysis with their definitions and MATLAB representations. (b) Define the term Fast Fourier Transform and explain its properties. 2. (a) Explain Double-Precision fixed-point format and Block floating-point format for signals and coefficients in DSP systems. (b) Describe the DSP computational errors for evaluating computational accuracy in DSP implementations. 3. (a) Describe the speed issues that are required for programmable DSP devices. (b) What is meant by on-chip memory? Explain the organization of the on-chip memory relevant to bus architecture and memory concept. 4. (a) Describe the concept of hardware looping related to execution control and pipelining in DSP processors. (b) Describe the concept of pipelining and its performance in DSP processors. 5. With an example, explain the following relevant to TMS320C54XX Digital Signal Processors. (a) Interrupts (b) Data addressing modes

[8] [8]

[8] [8]

[8] [8]

[8] [8]

[16]

1 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

6.

R07

Set No. 2

Implement a digital FIR low pass filter using the Parks-McClellan algorithm with the following specifications. (a) p = 0.2 Rp = 0.25 dB As = 50 Db (b) s = 0.3 Give the necessary MATLAB source code. [16] [8] [8]

7. (a) With an example, present FFT algorithm for efficient DFT computation. (b) Perform an 8-Point FFT implementation on the TMS320C54XX DSP processor. 8. (a) Describe the interfacing concept of parallel I/O to programmable DSP devices with neat sketch. (b) With suitable CODEC interface circuit, explain its programming concept.

[8] [8]

2 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 3

IV B.Tech. II Semester Regular Examinations, April, 2011

DSP PROCESSORS AND ARCHITECTURES

(Common to Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Bio-Medical Engineering) Time: 3 Hours Max Marks: 80

Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) With suitable example, explain the analysis and design tool for DSP systems using MATLAB. (b) Write notes on Digital Filters. 2. (a) Explain the fixed-point format and floating-point format for signals and coefficients in DSP systems. (b) Differentiate A/D and D/A conversion errors concerned to computational accuracy in DSP applications. 3. (a) With the aid of suitable structure, explain the basic DSP computational building block of 4X4 Braun multiplier. (b) Explain the concepts of hardware architecture and parallelism related to speed issues required for programmable DSP devices. 4. (a) Describe the concept of pipelining and its performance in DSP processors. (b) Explain the various interrupt effects that are occurred during the process of execution and pipelining in DSP processors. 5. With suitable example, explain the following relevant to TMS320C54XX Digital Signal Processors. (a) Interrupts (b) Data addressing modes

[8] [8]

[8] [8]

[8] [8] [8] [8]

[16]

1 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 3

6. Implement a digital IIR low pass filter using a Chebyshev-II prototype algorithm with the following specifications. (a) p = 0.2 Rp = 1 dB (b) s = 0.3 As = 15 dB Give the necessary MATLAB source code. [16] 7. (a) Describe the concept of overflow and scaling for the implementation of FFT algorithms with suitable examples. (b) Write a note on computation of the signal spectrum relevant to FFT algorithms. 8. (a) With the aid of suitable timing diagrams explain the memory interface signals for a read-read-write sequence of operations to programmable DSP devices. (b) Draw the block diagram of a multichannel buffered serial port of C54xx and explain its importance on the TMS320C5416 DSP.

[8] [8]

[8] [8]

2 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 4

IV B.Tech. II Semester Regular Examinations, April, 2011

DSP PROCESSORS AND ARCHITECTURES

(Common to Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Bio-Medical Engineering) Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) Explain the frequency domain representation of linear time-invariant systems. [8] (b) Draw and explain the block diagram of a digital signal processing system. [8] 2. (a) Describe the sources of error in DSP implementations for evaluating the computational accuracy. [8] (b) Discuss about A/D conversion errors for evaluating computational accuracy in DSP implementations. [8] 3. (a) Explain the various DSP computational building blocks, in brief. (b) Explain the basic architectural features of programmable DSP devices. 4. (a) Describe the importance of stacks during the process of execution control and pipelining in DSP processors. (b) Explain the various branching effects that are required to consider during the process of execution and pipelining in DSP processors. 5. With suitable example, explain the following relevant to TMS320C54XX Digital Signal Processors. (a) Interrupts (b) Memory space [8] [8] Time: 3 Hours

[8] [8]

[16]

1 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: L0424

R07

Set No. 4

6. Implement a digital IIR low pass filter using a Chebyshev-II prototype algorithm with the following specifications. (a) p = 0.2 Rp = 1 dB (b) s = 0.3 As = 15 dB Give the necessary MATLAB source code. [16] 7. (a) Discuss the various types of FFT algorithms for the efficient computation of the DFT. [8] (b) Perform an implementation for an 8-point DIT FFT algorithm which includes spectrum computation using the FFT result. [8] 8. (a) With neat sketch, explain how the Direct Memory Access is going to be interfaced to programmable DSP devices. (b) Explain the programming concept of a multichannel buffered serial port.

[8] [8]

2 of 2

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.