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Amplification is necessary in an analogue or digital circuit as the existing signal from the circuit is small to drive a load or overcome noise at particular stages in the circuit. Amplifiers have numerous practical applications such as amplification of sound from microphone to loud speaker, current amplifier to drive a motor in a robot, amplifiers in CD player, in microwave oven to amplify the beep, cameras, security system and many other applications hence it is very important in analogue circuit designs. There are numerous types of amplifiers based on the type of application. A fully differential amplifier is a high gain voltage amplifier with differential inputs and outputs, a fully differential amplifier is widely used in analogue integrated circuits as it can reject noise caused by the power supply and common mode. A fully differential amplifier also can amplify a small differential AC voltage so that it can be detectable and processed to its following stages in the circuit. The objective of this assignment is to design a Folded Cascoded Fully Differential CMOS Amplifier based on the given parameters and constrains. Throughout this report basic theory of relevant circuit are explain and the required circuit is designed with all the analysis, calculations and simulated in order to fulfil the constrains.


1. You are expected to design and simulate a folded cascode fully differential CMOS amplifier. AC input signal of 5 mV (Vpeak) is applied to the differential input for amplification. 2. Thorough analysis on differential amplifier including a. DC analysis. b. AC analysis. c. transient analysis d. Frequency response. e. Power supply noise analysis. f. The fully differential amplifier must achieve below specifications: a) Power supply = 1.8V b) Gain > 80 dB c) Cutoff frequency (fc) > 10 MHz d) Power supply rejection > -30dB at the frequency of 1MHz. e) Total current consumption < 2mA f) The differential output is able to drive a capacitive load of 0.1pF and resistive load of 1k

MOSFET Transistors
MOSFET (Metal Oxide Field Effect Transistor) is a voltage controlled device consisting of 3 terminals gate( connected to input) , drain and source , in other words the voltage at the gate terminal controls the current flow from the drain to source. The reason why it is used more commonly now instead of BJT is due to its high input resistance; it has low leakage current and can be used for high power amplification. Mosfets are of two types enhancement and depletion where enhancement consist of two types of transistor NMOS & PMOS. NMOS NMOS transistor in built with n-type source, drain and a p-type substrate. The below figure 1 shows the source and the drain regions made of n+-type diffusion which is connected by a metal to the external conductors. The depletion regions are mainly formed in the more lightly doped p-region. Thus, the source and the drain are separated from each other by two diodes. The region between the two diffused n+-type under the oxide layer is called the channel region which basically provides a path for the majority carriers to flow between the source and the drain. It is covered by a thin insulating layer of silicon dioxide (SiO2), the gate electrode is made of polycrystalline silicon (polysilicon ) stands over this oxide.

Figure 1 NMOS transistor structure

The below figure 2 shows the circuit diagram of NMOS transistor Vg Gate terminal connected to gate voltage Vd Voltage at the drain terminal Vb Buck terminal which is connected to the source terminal Vs Source terminal connected to ground in this case.
Figure 2 NMOS circuit symbol

PMOS PMOS transistors are built with p-type source, drain and n-type substrate which is donor doped silicon and it consists of holes for charge carriers. The source and the drain regions made of p+ type diffusion which is connected by a metal to the external conductors. The depletion regions are mainly formed in the more lightly doped n-region. Thus, the source and the drain are separated from each other by two diodes. The region between the two diffused p+-type under the oxide layer is called the channel region which basically provides a path for the holes to flow between the source and the drain. In PMOS transistor the terminals are the same but the voltage polarities and current direction is reversed. The below figure 3 shows the structure of PMOS transistor.

Figure 3 PMOS transistor structure

The below figure 4 shows the circuit diagram of PMOS transistor

The terminal G (gate) is connected to the positive voltage and the terminal D (drain) polarity is change to negative and the S (source) terminal polarity is changed to positive.

Figure 4 PMOS symbol

Transistor Operations
Switching of MOS transistors is characterised by the parameter threshold voltage (V TH) which is the minimum voltage that must be given between the gate and source in order to turn on or enable the transistor. Operations of transistors are categorised in the following regions below. Cut off Region: - In the Cut off region the gate voltage VGS is smaller than the threshold voltage VT the transistor is generally off , causing no current flow between the drain and source , in other words VDS is zero. Electrical field induced by the gate voltage goes down from the gate through the channel, where this field repels the majority carriers for the p-type substrate (positive holes) from the channel forming a depleted region of carriers and due to the lack of free carriers IDS=0 which is shown in the below figure5. This is basically called cut off region VGS < VT for NMOS and for PMOS VGS >-VT due to the polarity changes

Figure 5 Cut off region

Linear region: - In the linear region the presence of free electrons in the conducting channel causes the drain source voltage above 0 ( VDS >0 ) , hence the drain-source current (IDS )starts to flow. In the linear region the VDS is very small and the current ID is a function of source drain voltage. Increase in drain current slows down when the source drain voltage increases causing the channel depth at drain to decrease. The linear region of operation is basically illustrated by the formulae VGS > VT for NMOA VGS <-VT, the below figure 6 shows linear region.

Figure 6 Linear region

Saturation region: In saturation mode the depletion region adjacent to the drain is enlarged and there are no free electric carriers , hence the area acts as a dielectric. In the case of saturation region source-drain current ID is independent of VDS ( source drain voltage ). Electrons received to the channel from the source is injected to the depleted region of the channel and accelerated toward the drain by high electric field induced by the source drain voltage. Saturation region is the region where the transistor functions or operates fully and it has to satisfy by the equation it must be must be satisfied by the equation for NMOS transistors and for PMOS , if the equation is

satisfied the transistor tends to operated, the below figure 7 shows how saturation region looks like.

Figure 7 Saturation region

CMOS (Complementary Metal Oxide Semiconductor)

Combination of p-channel and n-channel of the MOSFET in the same substrate can give a very effective circuit called CMOS which is highly advantageous in computer logic designs. Advantages include high input impedance, fast switching speeds, reduces noise, lower operating power and less power consumption. It can be seen how CMOS is complementally arranged in the circuit which is to be designed in order to obtain the required outputs.

Figure 8 CMOS Cross-section

Transistor Configuration
Transistors are configured based on the requirement for the application in the circuit. In this assignment a common source and common drain configuration will be used for numerous purposes which will be explained detailed during circuit design. Common source configuration with current-source load This type of configuration is generally used to amplify the gain which is given by the formulae Av = -gm RD where RD is the load impedance. Common source gives a moderate output impedance but however as instead of resistor usage of PMOS transistor gives a high output impedance as the impedance at Rout is looked in to drain. The output signal is 180 degrees out of phase with respect to the input. It is also know from the equation that increasing of load impedance can increase the gain of the amplifier. Figure 9 shows the configuration of common source stage with resistor which gives the output impedance by the following equation

Now the gain in this configuration is Av = -gm Rout

Figure 9 CS with resistor

Figure 10 shows the configuration of common source stage with PMOS transistors which give the output impedance by the following equation

Now the gain in this configuration is Av = -gm Rout This configuration gives high output impedance resulting in a gain compared to the figure 9 configuration

Figure 10 CS with PMOS transistor

Source follower configuration It is often called as common drain; this configuration has very high input impedance and gives low output impedance. The gain of this configuration is almost closer to unity. As the gain is unity it is also called as buffer and its role is to drive the load with negligible power loss of the signal level and also to alter no noise in the circuit. The below figure shows a source follower with resistor connected to source.

Figure 11 Source follower

Basically the source follower senses the signal from the gate Vin which comes from the output of common source (high input impedance) at the gate terminal and drives the load at source. In source follower the drain current of M1 depends on the input dc level. For example if Vin changes from 1.5V to 2 V , ID may increase by a factor of 2 , hence which causes nonlinearity in the input output

characteristics to eliminate this issue the resistor can be replaced by NMOS transistor.

Circuit Design and Analysis

Folded Cascoded fully differential amplifier consist of four stages which are : 1. Fully Differential amplifier stage 2. Cascode amplifier stage 3. Common source amplifier stage 4. Buffer stage Fully Differential amplifier stage Fully differential amplifier is characterised in terms of self-bias capability, common mode rejection, voltage gain and reduced noise. A fully differential amplifier circuit is a special type of amplifier with two inputs and two outputs, this amplifier amplifies input signal on the two input terminals that are out of phase and rejects input signals that have a common phase such as induced noise. A differential signal is the one that is measured between two nodes that have equal and opposite signal around fixed potential, the centre potential in differential signal is common mode. The circuit designed for fully differential amplifier stage is shown in the figure below

Figure 12 Fully differential amplifier

M1 and M3 are input source coupled pair since they have the same drain current and same size. If V1 and V3 experience common mode disturbance or if the common mode is not well defined as the input common mode changes, bias current V1 and V3 changes varying in transconductance of the amplifier and output common mode level. Due to the variance in transconductance it leads to a small signal gain while the output at common model level from

its ideal value lowers the maximum allowable output swings. For instance if the common mode level is low the minimum values of V3 and V1 may turn off M1 and M3 leading to severe clipping at output , thus in order to resolve this the differential pair is connected to a tail NMOS transistor to make Id1 + Id3 is dependent on input common mode voltage.

When designing it is necessary to determine the size of transistors and it must be ensure they are in the saturation region for the transistor to operate.

NMOS Transistor M1 & M3 Assumptions made: VTH = 0.36V, VS = 0.3V, VG = 1.2 V, VD = 1.2V, IDS = 400 , L = 0.5 m,

must be satisfied in order to ensure that the transistor is in the saturation region for operation.

since it saturated now the width can be found V

( ) ( ) ( ) W VGS IDS L : - Width of transistor : - Gate-source voltage : - Drain current : - Length of transistor : - Transconductance of transistor : - Threshold Voltage : - Drain Voltage


Hence the width is

( ( ) ( ) )

The width of M1 and M3 is same because they are mirrored.

NMOS Transistor M2 Assumptions made: VTH = 0.36V, VS = 0V, VG = 0.5 V, VD = 0.3V, Ids = Ids1+Ids3= 800 m, L =
0.5 m,

must be satisfied in order to ensure that the transistor is in the saturation region for operation. Saturated, now the width can be found
( ( ) ( ) )

Channel length is neglected during the calculation of the size of transistors. The gain produce by the differential pair is relatively low and hence to increase the gain a cascaded differential pair had to be deisgned.

Cascode amplifier stage