2013 VLSI IEEE PROJECTS

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S.No
EIVL1 EIVL2 EIVL3 EIVL4 EIVL5 EIVL6 EIVL7 EIVL8 EIVL9

PROJECT TITLE
Novel Architecture for an Efficient Implementation of Image Compression Using 2DDWT(2012) Median filter on FPGAs(2012) Background subtraction algorithm for moving object detection (2012) Implementation of moving object tracking using EDK (2012) Real time hardware co-simulation of Edge Detection for video processing system(2012) Motion human detection based on background subtraction(2011) Hardware Implementation of DWT for Image Compression Using SPIHT Algorithm (2010) Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number(2010) Hardware Software co-simulation for Image Processing Applications(2012) HW HW HW HW HW HW HW HW HW HW HW HW HW

EIVL10 An FPGA Implementation of the Time Domain Deadbeat Algorithm (2010) EIVL11 A New Adaptive Weight Algorithm for Salt and Pepper Noise Removal (2011) EIVL12 An FPGA-based Architecture for Linear and Morphological Image Filtering (2012) EIVL13 VLSI Implementation of Image Segmentation with Resource Optimized Adaptive Median Filter (2011)

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2013 VLSI IEEE PROJECTS

Contact: +91-9014131492
EIVL14 FPGA Hardware of the LSB Steganography Method (2012) EIVL15 Four Bit CMOS Full adder in Submicron Technology with Low leakage and Ground bounce Noise Reduction(2012) EIVL16 Design of Sequential Elements for Low Power Clocking System(2011) EIVL17 Analysis of Power Gating designs in Low Power VLSI Circuits(2011) EIVL18 Area Optimized Low Power Arithmetic And Logic Unit(2011) EIVL19 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting(2010) EIVL20 Design of new full adder cell using hybrid-CMOS logic style(2010) EIVL21 Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications(2010) EIVL22 Design of A Low Power Flip-Flop Using CMOS Deep Submicron Technology(2010) EIVL23 Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design(2010) EIVL24 High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers(2012) EIVL25 Low-Power and Area-Efficient Carry Select Adder(2012) EIVL26 High speed and area efficient VEDIC multiplier(2012) EIVL27 Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits(2012)

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HW Backend Backend Backend Backend Backend Backend Backend Backend Backend Frontend Frontend Frontend Frontend

#11-13-916/52,Greenhills Colony, Rd.No.1. Saroornagar, Hyd-35. Cont: 04064609797.

2013 VLSI IEEE PROJECTS

Contact: +91-9014131492 info@eruditeinfo.com
Frontend Frontend Frontend Frontend Frontend Frontend Frontend Frontend Frontend Frontend Frontend Frontend EIVL28 High-Speed Low-Power Viterbi Decoder Design for TCM decoders(2012) EIVL29 Design and Verification of Four Port Router C(2011) EIVL30 An Efficient Implementation Of Floating Point Multiplier(2011) EIVL31 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm EIVL32 Low Complexity design of Ripple carry and Brent Kung Adder in QCA EIVL33 A Review on Power optimization of Linear Feedback Shift Register (LFSR) for Low Power Built In Self Test (BIST) EIVL34 CORDIC Designs for Fixed Angle of Rotation EIVL35 Design and Characterization of Parallel Prefix Adders (2011) EIVL36 Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing (2010) EIVL37 Performance Evaluation of DES and Blowfish Algorithms (2010) EIVL38 Finite State Machine based Vending Machine Controller with Auto-Billing Features (2012) EIVL39 Analysis of error masking and restoring properties of sequencial circuits (2011)

#11-13-916/52,Greenhills Colony, Rd.No.1. Saroornagar, Hyd-35. Cont: 04064609797.