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Unit 3

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UNIT 3

Register

OBJECTIVES

General Objective
Know and apply the fundamental concepts of the register .

Specific Objectives
At the end of this unit, you should be able to:

draw a basic shift register circuit using JK flip-flop and D flip-flop describe the basic function of the register identify the basic forms of data movement in shift registers list the types of shift register describe the operation of serial in/serial out(SISO), serial in/parallel out(SIPO), parallel in/serial out(PISO), and parallel in/parallel out(PIPO) shift registers state the applications of shift register in arithmetic operations; division and multiplication. construct a ring counter from a shift register state the application of shift register IC

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INPUT INPUT

3.0 INTRODUCTION
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously. A typical example of a shift register at work is found within a calculator. As you enter each digit on the keyboard, the numbers shift to the left on the display. In other words, to enter the number 156 you must do the following. First, you press and release the 1 on the keyboard; a 1 appears at the extreme right on the display. Next, you press and release the 5 on the keyboard causing the 1 to shift one place to the left allowing for 5 to appear on the extreme right; 15 appears on the display. Finally, you press and release the 6 on the keyboard; 156 appears on the display. This example shows two important characteristics of shift registers: (i) It is a temporary memory and thus holds the numbers on the display (even if you release the keyboard number) and (ii) it shifts the numbers to the left on the display each time you press a new digit on the keyboard. These memory and shifting characteristics make the shift register extremely valuable in most digital electronic systems. In this unit, we are going to learn the basic types of shift registers, such as Serial In - Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In Parallel Out, and bidirectional shift registers. A special form of counter - the shift register counter, is also introduced.

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3.1 Basic Shift Register Circuit

A register is a digital circuit with two basic functions: data storage and data movement. The storage capability of a register makes it an important type of memory device. Figure 3.1 illustrates the concept of storing a 1 or a 0 in a D flipflop. A 1 is applied to the data input as shown, and a clock pulse is applied that stores the 1 by setting the flip-flop. When the 1 on the input is removed, the flipflop remains in the SET state, thereby storing the 1. The same procedure applies to the storage of a 0, as also illustrated in Figure 3.1.

" 1 " is s to r e d "1 " C LK

Q Q

" 0 " is s t o r e d "0 " C LK

Q Q

Figure 3.1: The flip-flop as a storage element

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The storage capacity of a register is the number of bits (1s and 0s) of digital data it can retain. Each flip-flop in a shift register represents one bit of storage capacity; therefore, the number of flip-flops in a register determines its total storage capacity. For example, if 2 bit shift register to be built, 2 flip-flops are needed, as illustrated in Figure 3.2.

D a ta in p u t
D
C LK

D a ta o u t
Q Q
0

Q Q

Figure 3.2: A 2-bit shift register

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3.2

Shift Register Using Flip-Flops

The flip-flops used to construct registers are usually either JK or D types.

So, lets begin by summarizing the operation of a D flip-flop.

3.2.1 Shift Register Using D Flip-Flop

A basic four-bit shift register can be constructed using four D flip-flops, as shown in Figure 3.3. The operation of the circuit is as follows.

Figure 3.3: A 4-bit shift register

On the leading edge of the first clock pulse, the signal on the DATA input is latched in the first flip-flop. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-flop, and the signal which is present at the DATA input is stored in the first flip-flop, etc. Because the data is entered one bit at a time, it is called a serial-in shift register. Since there is only one output, and data leaves the shift register one bit at a time, then it is also a serial out shift register. (Shift registers are named by their method of input and output; either serial or parallel). Parallel input can be provided through the use of the preset and clear inputs to the flip-flop. The parallel loading of the flip-flop can be synchronous ( i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.

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3.2.2 Shift Register Using JK Flip-Flop

For a JK flip-flop, the data bit to be shifted into the flip-flop must be present at the J and K inputs when the clock transitions (low or high). Since the data bit is either a 1 or a 0, there are two cases: iiiTo shift a 0 into the flip-flop, J = 0 and K = 1. To shift a 1 into the flip-flop, J = 1 and K = 0.

The important point to note is that the J and K inputs must be controlled to provide the correct input data. The J and K logic levels may be changing while the clock is high (or low), but they must be steady from just before until just after the clock transition. For our discussion, we shall use JK master-slave flip-flops having clock inputs that are sensitive to negative clock transitions. Incidentally, this negative transition of the clock is frequently referred to as a shift pulse. The waveforms in Figure 3.4 illustrate these ideas. At time A, Q is reset low (a 0 is shifted into the flip-flop). At time B, Q does not change since the flipflop had a 0 in it and another 0 is shifted in. At time C, the flip-flop is set (a 1 is shifted into it). At time D, another 0 is shifted into the flip-flop. In essence, we have shifted 4 data bits into this flip-flop in a time sequence: a 0 at time A, another 0 at time B, a 1 at time C, and a 0 at time D.

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Input data Clock (shift)

J K

SET

Q Q

CLR

Figure 3.4: Shift register using JK flip-flop

Figure 3.5: Timing diagram of the shift register

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3.3 Types Of Register

The bits in a binary number (lets call them the data) can be moved from one place to another in either of two ways. The first method involves shifting the data 1 bit at a time in a serial fashion, beginning with either the most significant bit (MSB) or the least significant bit (LSB). The technique is referred to as serial shifting. The second method involves shifting all the data bits simultaneously and is referred to as parallel shifting. There are two ways to shift data into a register (serial or parallel) and similarly two ways to shift the data out of the register. This leads to the construction of four basic register types as shown in Figure 3.6: serial in/serial out (SISO), serial in/parallel out (SIPO), parallel in/serial out (PISO), and parallel in/parallel out (PIPO). All of these configurations are commercially available as TTL MSI/LSI circuit.
Parallel data input MSB Serial data input Serial data output LSB

SISO

PISO

Serial data output

Parallel data input Serial data input MSB LSB

SIPO

PIPO
MSB LSB Parallel data output MSB LSB

Parallel data output Figure 3.6: Shift Register types

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3.3.1 Serial In/ Serial Out Shift Register

The serial in/serial out shift register accepts data serially, that is, one bit at a time on a single line. It produces the stored information on its output also in serial form. Lets first look at the serial entry of data into a typical shift register. Figure 3.7 shows a 4-bit device implemented with D flip-flops. With four stages, this register can store up to four bits of data; its storage capacity is four bits.
FF0 FF1 FF2 FF3

s e r ia l d a ta in p u t

Q Q

Q Q

Q Q

Q Q

s e r ia l d a ta o u tp u t

C LK Figure 3.7: Serial in/serial out register

Figure 3.8 illustrates entry of the four bits 1010 into the register, beginning with the right-most bit. The register is initially clear. The 0 is put into the data input line, making D = 0 for FF0. When the first clock pulse is applied, FF0 is RESET, thus storing the 0. Next the second bit, which is a 1, is applied to the data input, making D = 1 for FF0 and D = 0 for FF1 because the D input of FF1 is connected to the Q 0 output. When the second clock pulse occurs, the 1 on the data input is shifted into FF0 because FF0 sets, and the 0 that was in FF0 is shifted into FF1. The third bit, a 0, is now put onto the data-input line, and a clock pulse is applied. The 0 is entered into FF0, the 1 stored in FF0 is shifted into FF1, and the 0 stored in FF1 is shifted into FF2.

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The last bit, a 1, is now applied to the data input, and a clock pulse is applied. This time the 1 is entered into FF0, the 0 stored in FF0 is shifted into FF1, the 1 stored in FF1 is shifted into FF2, and the 0 stored in FF2 is shifted into FF3. This completes the serial entry of the four bits into the shift register, where they can be stored for any length of time as long as the flip-flops have DC power.

FF0 D a ta in p u t
D
SET

FF1
Q Q
0

FF2
Q Q
0

FF3
Q Q
0

SET

SET

SET

Q Q

CLR

C LR

CLR

CLR

R e g is t e r in it ia lly C LEAR

C LK

1 s t d a t a b it = 0

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

A fte r C L K 1

CLR

C LR

CLR

CLR

C LK1

2 n d d a t a b it = 1

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

A fte r C L K 2

CLR

C LR

C LR

C LR

C LK2
0

3 rd d a t a b it = 0

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

A fte r C L K 3

CLR

C LR

C LR

C LR

C LK3

4 th d a t a b it = 1

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

A fte r C L K 4

CLR

C LR

C LR

C LR

C LK4

t h e 4 - b it n u m b e r i s c o m p le t e ly s t o r e d in r e g i s t e r

Figure 3.8: Four bits (1010) being entered serially into the register

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If you want to get the data out of the register, the bits must be shifted out serially and taken off the Q3 output, as Figure 3.9 illustrates. After CLK4 in the data entry operation just described, the right-most bit, 0, appears on the Q 3 output. When clock pulse CLK5 is applied, the second bit appears on the Q 3 output. Clock pulse CLK6 shifts the third bit to the output, and CLK7 shifts the fourth bit to the output. Notice that while the original four bits are being shifted out, more bits can be shifted in. As shown in Figure 3.9, all zeros are being shifted in.

FF0 0
D
SET

FF1
Q Q
1

FF2
Q Q
0

FF3
Q Q
1

SET

SET

SET

Q Q

Q 3 1 st d a ta b it
A fte r C L K 4 , re g i ste r c o n ta in s 1 0 1 0

C LR

C LR

C LR

C LR

C LK

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

Q 3 2 n d d a ta b it A fte r C L K 5

C LR

C LR

C LR

C LR

C LK 5

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

Q 3 3 rd d a ta b it A fte r C L K 6

C LR

C LR

C LR

CLR

C LK6
0

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

4 th d a ta b it
C LR C LR C LR CLR

A fte r C L K 7

C LK7

SET

Q Q

SET

Q Q

SET

Q Q

SET

Q Q

3 A fte r C L K 8 , re g is te r is C L E A R

C LR

C LR

C LR

CLR

C LK8

t h e 4 - b it n u m b e r is c o m p le t e ly s t o r e d in r e g is t e r

Figure 3.9: Four bits (1010) being serially shifted out of the register and replaced by all zeros.

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Example 3.1 Draw the waveforms to shift the number 0100 into the shift register shown in the figure below.
s e r ia l d a ta in p u t Q
0

Q Q

Q Q

Q Q

Q Q

d a ta o u t

C LK

Solution to Example 3.1

C LK

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3.3.2 Serial In/ Parallel Out Shift Register

The second type of register mentioned in section 3.3 is one in which data is shifted in serial, but shifted out in parallel. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously, rather than on a bit by bit basis as with the serial output. Figure 3.10 shows a 4bit serial in/parallel out shift register and its logic block symbol.
FF0 d a ta in p u t FF1 FF2 FF3

Q Q

Q Q

Q Q

Q Q

C LK Q Q Q Q

(a)

(b)

d a ta in p u t C LK

SRG 4

Figure 3.10: (a) Serial in/Parallel out shift register (b) Symbol Logic

Suppose that the data input is to be loaded in this 4-bit register is 0110. Since the 4-bit data is fed serially, the 4 clock pulses are needed to shift the data into the register. The data may now be read from the four Q outputs of the flipflops.

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3.3.3 Parallel In/ Serial Out Shift Register

For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on parallel lines rather than on a bit-by-bit basis on one line as with serial data inputs. The serial output is the same as described in section 3.3.1, once the data are completely stored in the register. Figure 3.11 illustrates a 4-bit parallel in/serial out shift register.

Notice that there are four data-input lines, D 0, D1, D2, and D3, and a
SHIFT/ LOAD

input, which allows four bits of data to be loaded in parallel into

SHIFT/LOAD

the register. When

is LOW, gates G1 through G3 are enabled,

allowing each data bit to be applied to the D input of its respective flip-flop. When a clock pulse is applied, the flip-flops with D = 1 will SET and those with D = 0 will RESET, thereby storing all four bits simultaneously. When is HIGH, gate G1 through G3 are disabled and gates

SHIFT/ LOAD

G4 through G6 are enabled, allowing the data bits to shift right from one flip-flop to the next. The OR gates allow either the normal shifting operation or the parallel data-entry operation, depending on which AND gates are enabled by the level on the
SHIFT/ LOAD

input.

Example 3.2

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Show the data-output waveform for a 4-bit register with the parallel input data and the clock and
SHIFT/ LOAD

waveforms given in figure below, if the parallel

data are D0 D1 D2 D3 = 1010.

D0 1 D1 D2 0 1 D 0
3

S H IF T / L O A D CLK

SRG 4 D a ta o u t (Q 3)

Solution to Example 3.2

CLK

S H IF T / L O A D

D a ta o u t (Q 3)

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3.3.4 Parallel In/ Parallel Out Shift Register

For parallel in/parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The following circuit in Figure 3.12 is a four-bit parallel in/parallel out shift register constructed by D flip-flops.

Figure 3.12: A 4-bit parallel in/parallel out shift register

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.

3.3.5 Bidirectional Register

A bidirectional shift register is one in which the data can be shifted either left or right. It can be implemented by using gating logic that enables the transfer of a data bit from one flip-flop to the next flip-flop to the right or to the left, depending on the level of a control line. A 4-bit bidirectional shift register is shown in Figure 3.13. A HIGH on the RIGHT/LEFT control input allows data bits inside the register to be shifted to the right, and a LOW enables data bits inside the register to be shifted to the left. An examination of the gating logic will make the operation apparent. When the RIGHT/LEFT control input is HIGH, gates G1 through G4 are enabled, and the state of the Q output of each flip-flop is passed through to the D input of the

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following flip-flop. When a clock pulse occurs, the data bits are shifted one place to the right. When the RIGHT/LEFT control input is LOW, gates G 5 through G8 are enabled, and the Q output of each flip-flop is passed through to the D input of the preceding flip-flop. When a clock pulse occurs, the data bits are then shifted one place to the left.

Figure 3.13: A 4-bit bidirectional shift register

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Example 3.3 Determine the state of the shift register of Figure 3.13 after each clock pulse for the given
RIGHT/ LEFT

control input waveform in figure below. Assume

that Q0 = 1, Q1 = 1, Q2 = 0, and Q3 = 1 and the serial data-input line is LOW. Solution to Example 3.3

R I G H T /LEFT LEFT RIGHT/

( rig h t )

( le ft )

( rig h t )

( le ft )

CLK

Q 0

Q 1

Q 2

Q 3

The key to everything is patience. You get the chicken by The key to everything is patience. You get the chicken by hatching the egg, not by smashing it. hatching the egg, not by smashing it. - Arnold H. Glasow - Arnold H. Glasow

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Activity 3A

LETS TRY TO ANSWER THE QUESTIONS BELOW..! 3.1 A stage in a shift register consists of (a) a latch (c) a byte of storage 3.2 (b) a flip-flop (d) four bits of storage

To serially shift a byte of data into a shift register, there must be (a) one clock pulse (c) eight clock pulses (b) one load pulse (d) one clock pulse for each 1 in the data

3.3

To parallel load a byte of data into a shift register, there must be (a) one clock pulse (c) eight clock pulses (b) one clock pulse for each 1 in the data (d) one clock pulse for each 0 in the data

3.4

The group of bits 10110101 is serially shifted (right-most bit first) into an 8bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains

(a) 01011110 (c) 01111001

(b) 10110101 (d) 00101101

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3.5 3.6

Why are shift registers considered basic memory devices? Draw the waveforms you would expect if the 4-bit binary number 1010 were shifted into the shift register in figure below, in serial. The register initially contains all 0s.
FF0 d a ta in p u t FF1 FF2 FF3

Q Q

Q Q

Q Q

Q Q

C LK Q Q Q Q

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Feedback To Activity 3A

3.1 3.2 3.3 3.4 3.5 3.6

(b) (c) (a) (c) Shift registers store binary data.

C L K D Q Q Q Q
0

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INPUT INPUT

3.4 Shift Register Applications

Shift registers can be found in many applications. Here are some applications of shift registers in microcomputer circuits.

3.4.1 Serial-to-Parallel Data Converter

A computer or microprocessor-based system commonly requires incoming data to be in a parallel format. But frequently, these systems must communicate with external devices that send or receive serial data. So, serial-to-parallel conversion is required. As shown in Figure 3.14, a serial-to-parallel data converter can be achieved. To illustrate the operation of this serial-to-parallel converter, the serial data format shown in Figure 3.14 is used. It consists of eleven bits. The first bit (start bit) is always 0 and always begins with a HIGH-to-LOW transition. The next eight bits (D7 through D0) are the data bits (one of the bits can be parity), and the last two bits (stop bits) are always 1s. When no data are being sent, there is a continuous 1 on the serial data line. The HIGH-to-LOW transition of the start bit SETS the control flip-flop, which enables the clock generator. After a fixed delay time, the clock generator begins producing a pulse waveform, which is applied to the data-input register and to the divide-by-8 counter. The clock has a frequency precisely equal to that

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of the incoming serial data, and the first clock pulse after the start bit occurs simultaneously with the first data bit.

Parallel data out

Figure 3.14: Simplified logic diagram of a serial-to-parallel converter

Figure 3.15: Serial data format

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By reversing the process, parallel-to-serial conversion can be accomplished. However, additional requirements must be taken into consideration in order to design the parallel-to-serial data converter. Figure 3.16 illustrates this concept.

Data bits

Figure 3.16: An 8-bit parallel-to-serial data converter

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3.4.2 Shift Register As Arithmetic Circuits

One of the common applications of the shift register is as a divider or a multiplier circuit. These arithmetic operations can be achieved using the Right/ Left shift register. For example, a right shift register as in Figure 3.17 can be implemented as a divide-by-2 circuit as shown in the following example. Operation 1st shift 2nd shift Data ( binary ) 0100 0010 0001 Data ( decimal ) 4 2 1

From the above table, we noticed that the most significant bit (MSB) is shifted one place to the right. As a result, the least significant bit (LSB) is shifted to the place of MSB.

Figure 3.17: A 4-bit Right shift register

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Meanwhile, for a left shift register as in Figure 3.18, it can be implemented as a multiply-by-2 circuit as shown in the following example. Operation 1st shift 2nd shift Data ( binary ) 0010 0100 1000 Data ( decimal ) 2 4 8

From the table above, the least significant bit (LSB) is shifted one place to the left. As a result, the most significant bit (MSB) is shifted to the place of LSB.

Figure 3.18: A 4-bit left shift register

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3.4.3 Shift Register Counter

A shift register counter is basically a shift register with the serial output connected back to the serial input to produce special sequences. These devices are often classified as counters because they exhibit a specified sequence of states. One of them is a ring counter. The ring counter utilizes one flip-flop for each state in its sequence. It has the advantage that decoding gates are not required for decimal conversion, because there is an output for each decimal number. The following circuit as in Figure 3.19 is a 4-bit ring counter constructed from D flip-flops. The output of each stage is shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is preset to 1 instead. The sequence for this ring counter is given in Table 3.1

Figure 3.19: A 4-bit ring counter

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Clock pulse

Q0 1 0 0 0

Q1 0 1 0 0

Q2 0 0 1 0

Q3 0 0 0 1

0 1 2 3

Table 3.1: Four-bit ring counter sequence

Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state usage.

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3.5 Applications Of IC Shift Register

Of course, there are many single-chip integrated circuits which perform all the shift register functions. One of the more common ones is the 74LS164 shift register. Pin1 (labeled "A" here) is the enable input for the serial input, Pin 2 ( B ). The serial information presented at B is shifted through the internal 8 stages whose outputs are Q0 through Q7 on each positive clock edge (Pin 8). There is also a convenient overall reset (pin 9, MR ), which will clear the outputs of all the stages to zero. This counter has 8 binary outputs (8 stages), but if you need more you may cascade two of these together by connecting the MSB output (Q7) to the serial input of another 74LS164.

Figure 3.20: The logic diagram of 74LS164

Figure 3.21: The logic symbol of 74LS164

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The logic diagram of the 74LS164 is shown in Figure 3.20, and a typical logic block symbol is shown in Figure 3.21. A sample timing diagram for this IC is illustrated in Figure 3.22. Notice that the serial input data on input A are shifted into and through the register after input B goes HIGH.

Figure 3.22: Timing diagram of IC 74LS164

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Example 3.4 How long will it take to shift an 8 bit binary number into the 74LS164 in Figure 3.20 if the clock is: a) 1 MHz b) 5 MHz Solution to Example 3.4 a) b) T=1/f = 1/1MHz = 1x10-6 s 8 bit x 1 x 10-6 = 8 s T = 1/5MHz = 0.2 x 10-6 s 8 bit x 0.2 x 10-6 = 1.6 s

If you dont make mistake, you arent really trying. If you dont make mistake, you arent really trying. - Coleman Hamking - Coleman Hamking

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Activity 3B

3.7

A divide-by-10 ring counter requires a minimum of (a) ten flip-flops (c) four flip-flops (b) five flip-flops (d) twelve flip-flops

3.8 Draw a timing diagram of a 4-bit ring counter if the first register stores a 0100 data. 3.9 Assume that the initial contents of the 74LS164 register in figure below are 00000000. Determine sequence of states as clock pulses are applied.

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Feedback to Activity 3B

3.7 3.8

(a)

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3.9 Input pulse number 0 1 2 3 4 5 6 7 8 Q0 0 1 1 1 1 1 1 1 1 Q1 0 0 1 1 1 1 1 1 1 Q2 0 0 0 1 1 1 1 1 1 Q3 0 0 0 0 1 1 1 1 1 Q4 0 0 0 0 0 1 1 1 1 Q5 0 0 0 0 0 0 1 1 1 Q6 0 0 0 0 0 0 0 1 1 Q7 0 0 0 0 0 0 0 0 1

Recycles

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KEY FACTS

1.

The basic types of registers classified by input and output, are serial in/ serial out (SISO), serial in/ parallel out (SIPO), parallel in/ serial out (PISO), and parallel in/ parallel out (PIPO).

2. 3. 4. 5.

The basic types of data movement in a register are shift right and shift left. Shift register counters are shift registers with feedback that exhibit special sequences. Example is the ring counter. The ring counter has n states in its sequence. One of the shift register applications is in arithmetic operations.

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SELF-ASSESSMENT 3

Question 3-1

a.

Determine the number of flip-flops needed to construct a shift register capable of storing: i. 6 bit binary number ii. decimal numbers up to 32 iii. hexadecimal numbers up to F

Question 3-2 a. Name the four basic types of shift registers, and draw a block diagram for each. b. Draw the waveforms to shift the binary number 1001 into the register in figure below.

Serial data input

A
D
SET

B
Q Q D
SET

C
Q Q D
SET

D
Q Q D
SET

Q Q

CLR

CLR

CLR

CLR

CLK

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c.

For the data input and clock in figure below, determine the states of each flip-flop in the shift register of figure in (Question 3-2b) and draw the Q waveforms. Assume that the register contains all 1s initially.

C L K

D a ta in p u t

Question 3-3 a. Sketch the Q0 through Q7 outputs for a 74LS164 shift register with the input waveforms shown in figure below.

C L K

CLR

Be curious always! For knowledge will not acquire you, you must acquire it. Be curious always! For knowledge will not acquire you, you must acquire it. - Sudie Bach - Sudie Bach

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Feedback To Self-Assessment 3

Answer for Question 3-1 a. i) 6 flip-flops ii) 6 flip-flops iii) 4 flip-flops Answer for Question 3-2 a. Serial In/Serial Out (SISO), Serial In/Parallel Out(SIPO), Parallel In/Serial Out(PISO), and Parallel In/Parallel Out(PIPO).
Serial data input SIPO

Serial data input

SISO

Serial data output

Parallel data output Parallel data input Parallel data input Serial data output

PISO

PIPO

Parallel data output

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b.

A C L K

c.

C L K

D a ta in Q 0

Q 1

Q 2

Q 3

Answer for Question 3-3 a.

C L K

C L R

Q 0

Q 1

Q 2