C3PU: A 16-BIT SOFT-CORE PROCESSOR

Simon
(1) Cossart ,

Filip

(2) Keri ,

Luka

(3) Kova

and Ivan

(4) Sovi

(1) Lyce Toulouse-Lautrec, Toulouse, France (2) XV. gimnazija, Zagreb, Croatia (3) III. gimnazija, Osijek, Croatia (4) Ruer Bokovi Institute/Centre for Informatics and Computing, Zagreb, Croatia

Introduction
A processor is a small chip that can be found in electronic devices whose job is to receive input and provide the appropriate output. The main goal of this project was to design and implement a 16-bit soft-core CPU using FPGA board and VHDL language. We designed all the components of our CPU, and checked if they work separately. We also defined our assembly language and implemented two assemblers that translate our assembly code to the CPUs machine code.

C3PU how it works?

Results
We made a code for our processor to make a Fibonacci sequence. It was ran through the assembly, and then we put the machine code in the memory of our C3PU.

assembly

FPGA board
Spartan 3-AN model
Power

Memory
( program+data )

Our simulation results showed us the expected sequence, so we can say that our processor works.

CPUs finite state machine (pipeline)

Chip
RESET FETCH
Puts the zero value in all the registers

Conclusion
We reached our goal in designing a soft-core CPU. The simulation results proved that our processor works. In the future we want to include I/O components to our design, so our C3PU is more practical.

Connection with the computer

DECODE
Retrieves commands from RAM on the address from PC register

EXECUTE
Checks the opcode of retrieved command Performs the instruction

Example of an output

Acknowledgements
Authors would like to thank the Society for Out-of-Frame Education, as well as the organizers and participants of the Summer School of Science 2013 in Poega for endorsing and supporting this project.

Example of an input

Sample command: 00011_00000_001_010

FPGAs are logic devices that contain configurable logic blocks( CLBs ) and connections between them. CLBs can perform any logic operation we want we have to define which one( unlike hard-core CPU, which isnt so reconfigurable ). Since we have many empty CLBs, we are able to make a complex logic design such as CPU.

ALU operations AND

opcode

Shifter operations SHL SHR

opcode

c = a and b 01001

OR
NOT XOR ADD SUB INC DEC ZERO

c = a or b
c = not a c = a xor b c=a+b c=ab c=a+1 c=a1 c=0

01010
01100 01011 01101 01110 00111 01100 01111

Shift 1 bit to 10000 the left Shift 1 bit to 10001 the right

Control operations NOP LOAD MOV LOADI JMPI JMPCI END 00000 00001 00011 00100 00101 00110 10110

ROTR Rotate 1 bit 10010 to the right ROTL Rotate 1 bit 10011 to the left