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Chapter 2 Programming Model, Addressing Modes and Instruction Set

An assembly language programmer should at least be familiar with the following features of the processor: Register set Instruction set Addressing modes Memory organization

CPU Registers
An MPUs programming model shows only those internal registers that the programmer can directly control via the MPUs instruction set.

Programming Model of the 68HC11 Accumulators A,B and D: - There are two 8-bit accumulators (ACCA and ACCB) - Each may be a source or destination operand for 8-bit instructions. - ACCD is the concatenation of A and B and instructions that modify ACCD actually modify ACCA and ACCB. e.g. LSLA

b7 .....................b0 ACCA


b7 .....................b0 ACCA

b7 .....................b0 ACCB


Index registers X and Y: The two 16-bit index registers are used primarily for indexed addressing (will be studied in addressing modes). There are also some arithmetic instructions involving the index registers. e.g. INX (increments the contents of index register X, i.e., (IX) (IX)+$0001) Stack pointer (SP): The 16-bit stack pointer maintains a program stack (will be studied later in detail) in RAM and must be initialized to point to RAM area before use. Program counter (PC): Although it is shown in the programming model, the programmer does not have direct control over it like the other registers. It is usually given to show the amount of memory that can be directly addressed by the processor (the number of bits in the PC indicate the address range). Condition code register (CCR): The 8-bit condition code register consists of individual bits, called flags, with different meanings. Each flag is used to indicate the status of a particular MPU condition and the logic value of the flags can be examined under program control to determine what sequence of instruction to follow. The flags in CCR are carry, overflow, zero, negative, interrup mask, half-carry, X-interrupt mask and stop disable. e.g. Zero flag indicates whether the result of the previous operation is zero or not CLRA instructions clears ACCA and sets the zero (Z) flag.

Instruction Set
An MPU instruction usually has two parts, the opcode and the operand. the opcode tells the CPU what operation to perform the operand tells the CPU what data to operate on e.g. opcode 86 5A (LDAA #$5A in assembly language) operand

In 8-bit microprocessors, the instructions usually have one-byte opcodes but in 68HC11 there are also two byte opcodes (called the prebyte system) for increasing the number of possible instructions (because of having an additional 16-bit IY register). e.g., instruction increment X increment Y mnemonic INX INY machine code $08 $18 $08 operation (IX) (IX)+$0001 (IY) (IY)+$0001

Addressing Modes
An addressing mode specifies how to find/locate the data. The addressing modes available for the 68HC11 are; inherent, immediate, direct, extended, indexed and relative modes. Inherent addressing mode: used by instructions that do not need to access memory or I/O addresses (since all data for the instruction is within the CPU). The operand is obvious from the instruction mnemonic (assembly language representation). e.g., instruction clear ACCA mnemonic CLRA machine code $4F operation (A) $00


increment X set carry flag add B to A transfer A to B


$08 $0D $1B $16

(IX) (IX)+$0001 C1 (A) (A)+(B) (B) (A)

Immediate addressing mode: actual data follows the opcode. - used to initialize the registers with constants known at the time the program is written - requires a # prefix in the assembly language - can have both 8 or 16-bit operands e.g., instruction load Acc.A with 64 load Acc.A with $64 add Acc.B $02 load X with #$01FF mnemonic LDAA #64 LDAA #$64 ADDB #$02 LDX #$01FF machine code $86 $40 $86 $64 $CB $02 $CE $01 $FF operation (A) $40 (decimal 64) (A) $64 (hexadecimal 64) (B) (B)+$02 (IXHIGH) $01, (IXLOW) $FF

Direct addressing mode (also known as base-page addressing mode): single-byte data following the opcode is not the actual data but the address of the operand. - 2 byte instructions (one byte opcode + one byte address) enables one to address only the first 256 locations between $00 and $FF (base-page) e.g., memory location $E000 $E001 : $0064 machine code $96 $64 $C5 mnemonic LDAA $64 operation (A) ($64)

When executed ACCA contains $C5 The above instruction is executed as follows: PC contains the $E000 (the address of the location where the opcode is stored). The opcode $96 is fetched from memory first. The instruction is then decoded as a direct mode one and another byte is read from the memory loc. $E001 as the address of the operand. When the address information $64 is read from the memory, full address information $0064 is formed in the memory address register. Another memory read operation is performed from the address location $0064. The contents of the corresponding location, i.e, $C5, is then stored in ACCA.

Extended addressing mode: similar to direct addressing but uses two bytes as the address of the operand - 3 byte instructions (one byte opcode + two bytes address) enables one to address the entire 64Kbyte (216 = 65,536 = 64K) address space between $0000 and $FFFF. e.g., memory location $E000 $E001 $E002 : $6400 machine code $B6 $64 $00 $F5 mnemonic LDAA $6400 operation (A) ($6400)

When executed ACCA contains $F5.



memory location $0000 $0003

machine code ($) FC 12 34 FF 12 34

mnemonic operation LDD $1234 ACCD ($1234:$1235) { ACCA ($1234), ACCB ($1235) } STX $1234 ($1234:$1235) IX { ($1234) IXHIGH, ($1235) IXLOW) }

: $1234 $1235

$F5 $00

When executed with ACCA=$FF, ACCB=$FF and IX=$2345, the register and memory contents will change as follows ACCA=$F5, ACCB=$00, IX=$2345, ($1234)=$23, ($1235)=$45 Indexed addressing mode: makes it easy to handle tables and blocks of data in memory. - an indexed instruction format is as follows: Operation Offset, Index_register (e.g. LDAA $05,X)

where Offset is an unsigned 8-bit value and Index_register is either X or Y. the effective address of the operand in indexed mode is calculated by the CPU as the sum of the offset and the contents of the IX or IY register. i.e., operand address = (IX) + offset e.g., machine code ($) A6 05 offset or operand address = (IY) + offset comment effective address = (IX) + $05

mnemonic LDAA $05,X


if (IX) = $C500 then the effective address (address of the operand) is $C505 and A ($C505) Contents of memory location $C505 is loaded into ACCA Examples:


Relative addressing mode: is used for branch instructions. - Branch instructions often do not jump very far from the current location. - M68HC11 branch instructions use relative addressing while jump instructions use extended addressing. - a relative addressing mode instruction adds the offset to PC to find the address of the next instruction to execute. e.g., (extended mode jump instruction) address

0100 0101 0102 0103 0104

0200 0201

ADDA $50 JMP $02 $00 . . . LDAB $40

After this instruction is executed, PC is updated to have $0200, which is the address of the next instruction to be executed.


(relative mode branch instruction) (forward jump) address opcode offset

0100 0101 0102 0103 0104

ADDA $50 BRA $03 . . . STAA $20

PC points to $0104 after the fetch cycle and also the operand fetch. Following the execution, $03 is added to the PC and the next instruction to be executed becomes the one located at address $0107. jump forwards


Since it is designed to branch in either direction, the 8-bit address byte (offset) is interpreted as a signed 7-bit value (in 2s complement). Hence the branching range is; (PC + 2) 128 Destination (PC + 2) +127 PC 126 Destination PC+129 Location of the current instruction Location of the instruction to jump


Effectively, one can branch to locations between 126 bytes backwards and 129 byte forwards relative to the address of the branch instruction. e.g., (relative mode branch instruction) (backward jump) address

0100 0101 0102 0103 0104

ADDA $50 BRA $FC . . . STAA $20

jump backwards PC points to $0104 after the fetch cycle and the operand fetch. Following the execution, PC is updated and $FC (-4) is added to the low byte of PC and the next instruction to be executed becomes the one located at address $0100.


Instruction Set
68HC11 has 329 instructions but counting only the different operations there are 153 instructions, which can further be categorized into 14 different sets. Learning a new instruction set is easier if one first learns the categories of instructions and then learns what instructions are in each category. 1) Load registers (10 instructions) e.g., LDAA LDAB LDX STAA STAB STY TBA TAB TSX XGDY DEC DECA INX CLR CLRA BSET ABA ABX SUBA (A) (M) (B) (M) (IX) (M:M+1) (M) (A) (M) (B) (M:M+1) (IY) (A) (B) (B) (A) (IX) (SP) (D) (IY) (M) (M) - 1 (A) (A) - 1 (IX) (IX) + 1 (M) 0 (A) 0 set bits (M) (A) (A) + (B) (IX) (IX) + (B) (A) (A) - (M)

2) Store registers (10 instructions)


3) Transfer registers (8 instructions)


4) Decrement/Incremen t (12 instructions)


5) Clear/Set (5 instructions)


6) Arithmetic (21 instructions)




(D) (A) * (B) (A) 2s complement of (A) (A) (A) AND (M) (B) (B) XOR (M) (B) 1s complement of (B) rotate right A logic shift right (M) test if (A) = 0 (A) (M) (X) (M:M+1) branch if minus branch if equal to zero branch if carry clear unconditional jump unconditional branch (short jump) jump to subroutine (C) 0 (V) 0 (CCR) (A) (A) (CCR) (I) 0 (I) 1 return from interrupt software interrupt wait for interrupt no operation stop clocks special test mode

8) Rotates/Shifts (21 instructions) 9) Data test (11 instructions)



10) Conditional branch (16 instructions) 11) Jump and branch (9 instructions)



12) Condition code (6 instructions)


13) Interrupts (5 instructions)


14) Misc. (3 instructions)


Load register instructions


Note that it is possible to use the same instruction in different addressing modes. e.g., use of LDAA instruction in different addressing modes Code 86 40 96 40 B6 40 00 A6 40 18 A6 40 Mnemonic LDAA #$40 LDAA $40 LDAA $4000 LDAA $40,X LDAA $40,Y Addressing Mode immediate direct extended indexed indexed Operation (A) $40 (A) ($40) (A) ($4000) (A) ((IX) + $40) (A) ((IY) + $40)

Note that these instructions affect the Z and N flags according to the value that is loaded, reset the V flag and do not effect the C flag in the condition code register (CCR). Note: At this stage it is helpful to study the full instruction set of the 68HC11 (Appendix A)