System Design and Modeling With Simulink

1
System Design & Modeling System Design & Modeling

with with MATlab MATlab / / Simulink Simulink
Project Results and Solutions within Project Results and Solutions within
Research and Education Research and Education
- A VLSI- System - Prototyping Test-bed -
Real-time Analysis & Visualization
Dr. Alfred Blaickner
Email: a.blaickner@cti.ac.at
6/8/2002 Dr.A.Blaickner, email: a.blaickner@cti.ac.at 2
Overview
System Design Cycle & DSP/FPGA-test-bed
Project & Research Activities
Communication Systems
Signal Processing Systems & Education
MATlab Solutions
VLSI - Emulation / Prototyping-test-bed
Conclusion
2
Motivation
System - Design
Necessary due to non-linear behavior of many
subsystems and reduced word-length effects
System design - important step prior to VHDL -
coding, synthesis and VLSI - implementation
System - Design with MATlab
Floating point models - most efficient & fastest
solution for early analysis & performance results
Bit-true and cycle accurate modeling techniques
have been developed for the presented projects
Define concept, a mathematical model, get suitable numeric algorithms
Design of a floating point model at system level
MATlab, System-C, Co-Centric, Cossap, SPW
Map floating point model to a constrained equivalent bit-true and cycle
accurate version - minimize data path processing / shared-architecture
Verify and optimize until functionality full-filled
Map the design manually to a hardware description
language VHDL / HDL (today) ...System-C (future ?)
Synthesize, place and route - HW / SW- Co-design cycles
get test-vectors, back-annotate, optimize and verify
System Design Cycle - Overview
3
System - Design Level (ML, SysC)
Idea and concept
Mathematical model
Numerical algorithm
Numerical simulation model;
Bit-true & cycle accurate model
Mapping to architecture - manually
Behavioral- / RTL- Level (HDL, SysC)
Behavioral architecture description
RTL architecture description
E.g: Data bus, MUX, ADD, MUL, REG -
pipeline;
Implementation (Route & Place)
ASIC, FPGA, DSP, Embedded - Systems
System Simulation (ML, Msim, SysC)
Simulation and back annotation to prev.
D
S
R
DSP
ASIC
MATlab based modeling and VHDL-generation
Libraries and toolbox for VHDL/HDL generation
Easy usage for automatic generation of various VHDL/HDL
designs of filters & arithmetic functions (MUL, CORDIC, .. ;)
E.g. half-band filters, arbitrary filter chains
Bit-true and bus accurate
modeling techniques
Most important prior to
architecture mapping
Get first accurate hardware results
Bit - True
Remove zero Values
Matlab Filter
Design Tool
Coefficint Array
ReadCoeffRam.m
RunHalfBandDez.m
MakePackage.m
HB_Filter_Pkg.vhd
- Create Input data vector
- Write test patter in data file
- Filter data
- Write result file
4
Hardware / Software - Co-design
Device under Test is directly embedded
in design- & test- environment
Shortened design cycles and rapid
prototyping
DSP- PC_ board
ALTERA- FPGA
1.5 mil. gates)
I/O Interfaces
Testvectors
System Architecture Integration & Synthesis
Architectural mapping and synthesis
T VHDL / C++ / System-C; Cooperation with CAE-Vendors
System Implementation
T Target is currently a modular DSP/FPGA VLSI-emulator - RT-test-bed
HW/SW-co-design and co-verification
T Real-time analysis and control with MATlab / MEXfile- Interface plus
pattern generator / high-speed-digital-IO
T In future with both SystemC and MATlab
Embedded Parallel Processing DSP/FPGA
Scaleable multi-processing architecture
T Modular DSP(Sharc)- and FPGA(Apex)-based system
C++ based system control
T Real-time test vector and verification environment
T Seamless integration to industry standard compact PCI-bus system
5
Wideband
RF frontend
Wideband
RF frontend
Display
CTRL
CCD-
Interface
SYSTEM CONTROL
cPCI-Bus
CLK-Ref
JTAG-Bus
PPORT
Prog./Analyze
BITSI
LVDS
LVDS
ParPort
ParPort
SerPort
SerPort
SerPort
SerPort
ParPort
ParPort
ParPort
ParPort
ParPort
ParPort
BITSI
BITSI
BITSI
DSP-array / QUADsharc 21160
FloatPnt-processing / Baseband processing /
Adaptive filtering / Source- / Channel coding /
Signal processing
FPGA-array
Integer- / Channel processing / Filtering
Signal processing / VLSI emulation
A/D - modules
Analog to digital
conversion
Frontend / Backend
Up-/down-conversion
Specific analog
electronics
NT-Workstation-B
System - Design
VHDL - Synthesis
HW/SW-Co-design
NT-Workstation-A
System - Control
Realtime - Test
Visualization
Vector-Gen
Fast-IO
MV-IF (Prog.)
MV-Analyzer
JTAG-IF (ICE)
QuadSHARC 21160
Fast-ADC (2 Chan)
Fast-DAC (2 Chan)
PCI-BUS-Bridge (NI)
PCI-Bus PCI-Bus
PASS Programable Array System Simulator, design by Dr. A. Blaickner
FPGAmodule
APEX
400/600/1000
FPGAmodule
APEX
400/600/1000
FPGAmodule
APEX
400/600/1000
FPGAmodule
APEX
400/600/1000
DSP
SHARC
21160
DSP
SHARC
21160
DSP
SHARC
21160
DSP
SHARC
21160
ADC
ADC
DAC
DAC
Author: Dr. A. Blaickner
DSP/FPGA-based - VLSI-emulator
FPGAs
2 x 1.5mil.
Gates
System-Clk:
50-100 Msps
DSPs
4x21161 ADI-
Sharc
~1.2 Mflops
IO-Bandwidth
~320 Mbyte/s
Communications & Signal Processing
T Software Definable Radio Transceiver Design (GSM / UMTS)
T System Level Design MATlab & System-C
T System Architecture Integration and Synthesis
T Embedded Parallel Processing Systems DSP/FPGA based
Projects done with MATlab / COSSAP (1991-1999)
T FFTs, CORDICs, f-Synth., f/t/p-Synchronizers, TDMA burst modem
T Trained / blind equalization subsystem for broadband channels
T FSK/M-QAM-modems, Wireless networking / MC - modem (OFDM)
T Viterbi codec (radix - 4(2) ) // RS-codes, GF-arithmetic
T DVB- Receiver and FFT/IFFT - modeling, optimization, implement.
T Pipe-lined- FFT, multi-rate filters, half-band- / Avg.- / CIC-filters
T Bit-true modeling and DSP/FPGA- implementation, VLSI-emulation
6
Recent Projects on Software Definable Transceivers
Digital Channel Processing
T Programmable pulse-shaping and multi-rate filters
T Polynomial based re-sampling interpolation filters (Farrow / Poly-phase)
T Digital frequency synthesis, frequency translation, pipelined- CORDICs
Digital Baseband Processing
T Pulse-shaping, equalization, correlation, FFT-processing, modulation
detection, synchronization, phase looked & control loops, system ctrl;
System Level Design with SystemC & MATlab
Floating point system model
T System simulation and verification Matlab / System-C
Bit-true system model architectural mapping
T Bit-true simulation and co-verification CoCentric / SystemC / Matlab
Behavioral- / RTL- HW-description and synthesis
T Mapping to a real-time DSP/FPGA - VLSI emulator (test-bed)
Communication Systems - Status
Telecommunication systems - a current status
Multiple standards - fixed system solutions
Various dedicated VLSI - implementations
Next generation system architectures - 3G/4G
UMTS / HIPERLAN
T Air-interface: WCDMA / TD-CDMA, 384 Kbit/s ... 2 Mbit/s, (QPSK,FDD,TDD)
T 54Mbit: OFDM, QAM
WLAN - IEEE802.11a/b, HIPERLAN, Home-RF
T 2Mbit: DSSS, FHSS
T 11Mbit: DSSS (CCK), OFDM, QAM
Digital Broadcasting - DVB, MMDS
T Air-interface: OFDM, QAM
Coding: Viterbi, Trellis, Turbo, Reed-Solomon or concatenated
7
Software Radio - Motivation
Software radio and base-station concepts
Ideal digital software radio receiver
Realistic software receiver architecture
Single system provides various air-interfaces - modulation / coding
Suitable technology: FPGAs, 2 mil. logic gates - e.g. Apex, Virtex
T Sufficient system performance and logic capacity for channel processing
T Re-configurable and scaleable over LVDS, Remote re-programming service
T In contrast to DSP-solutions no limits for parallel structures (e.g decoding)
T A system per chip solutions, designed to exact requirements, no overhead
T Cost is comparable to dedicated VLSI-products e.g. band-pass processing
T Limitations: power budget - small terminals, but combine VLSI & FPGA area
Library of scaleable communication sub-modules
T Modulator units, channel-processing, frequency-synthesis, mixer, NCO, data-filter,
interpolator, equalizer, FEC, FFT, adaptive filter, CORDICs, parallel- / bit-serial
versions;
Software Radio - Motivation
Conventional coherent digital receiver architecture
Generic software radio receiver architectures
Wideband
RF frontend
Digital IF
channel
selection
Digital IF
channel
selection
Baseband
processing
Baseband
processing
System control unit
ADC
Data
stream 1
Data
stream 2
.
.
stream M
I/Q
I/Q
8
Software Radio - Architecture
A more detailed software radio architecture
Source Coding / Channel Coding / Multiplexer
Inner Transceiver
Channel Processing
Analog Backend / Frontend
DataInp
DataOut
Generic Digital Re-configurable Software Radio Transceiver
Coding/Decoding
SystemControl Unit
Symbol/Frame Processing Inner Transceiver Channel Processing
Scrambler
FEC (VIT,RS)
Puncturing
Host-Processor / Test-Interface System Control Interface
Descrambler
FEC(VIT,RS)
Depuncturing
Symbol-
mapping
DifCod
Symbol-
demapping
DifDecod
M
u
lt
ip
le
x
i
n
g
, R
a
t
e
-
c
o
n
v
e
r
s
io
n
M
u
lt
ip
le
x
i
n
g
, R
a
t
e
-
c
o
n
v
e
r
s
io
n
Data
Inter-
leaving
Data
Deinter-
leaving
Pilot-
Frame-
assembly
Channel-
equalizat.
Synchron.
Mux/
Demux
Cyclic-
Extension
Guard-
interval-
removal
FFT-/IFFT-
processing
Puls-
shaping
Symbol-/
Freq-/Phase-
Synchronization
Channel-
Equalization
Timing-/
Author: Dr. A. Blaickner, J2000
Configur-
able
Digital
to
Analog
Processing
Complex-
Mixer
Frequency-
synthesis
(DDS, NCO)
Digital
AGC
Channel-
filtering
Resampling
Analog
Up-/Down-
Conversion
ISM-band-
RF-TX/RX
Antenna
Processing
Signal-
detection
Analog RF - Processing
A
n
a
lo
g
G
a
in
C
o
n
t
r
o
l -
A
G
C
Clock-Control / State-Machine
Data-/Ctrl-BUS
Complex Pipeline Radix- 4 FFT- / IFFT- Processor
Delay
(12)
Delay
(8)
Delay
(4)
C
O
M
M
U
T
A
T
O
R
Delay
(12)
Delay
(8)
Delay
(4)
B
U
T
T
E
R
F
L
Y
R
a
d
ix
- 4
Delay
(3)
Delay
(2)
Delay
(1)
C
O
M
M
U
T
A
T
O
R
Delay
(3)
Delay
(2)
Delay
(1)
B
U
T
T
E
R
F
L
Y
R
a
d
ix
- 4
OutA
OutB
OutC
OutD
D
A
T
A
P
A
T
H
M
U
L
T
IP
L
E
X
E
R
TXout
RXout
RXclk
TXclk
DAclk
B
U
T
T
E
R
F
L
Y
R
a
d
ix
- 4
TX-Din
D
a
ta
S
c
h
e
d
u
e
r
S
y
s
te
m
C
o
n
tr
o
l
InA
InB
InC
InD
RX-Din
DAclk
RXclk
TXclk
Init
CTRLbus CTRLbus
A. Blaickner
Wideband
RF frontend
Digital IF
channel
selection
Digital IF
channel
selection
Baseband
processing
Baseband
processing
System control unit
ADC
tunable
Data
stream 1
Data
stream 2
.
.
stream M
I/Q
I/Q
Subsystems - Overview
SOFTWARE - Radio
OFDM
CORDICs
FILTERs
FFT/IFFT
CICx - Interpolation Filter Architecture (CIC-4)
DATAin
A. Blai ckner
REG REG REG
REG
REG REG
Delay z-n
REG REG
Delay z-n
REG REG
Delay z-n
REG REG
Delay z-n
REG REG
REG
DATAout
CLKo
Int
INT INT INT
CMB CMB CMB CMB
DEC
CLKi
Switch - Matrix
A. Blaickner
Prog-FIR
Decimate,
interpolate,
resample
Base-
band-
PORT
IO,
Buffers
Ctrl,
Mod.
System - control - interface
Unit ctrl, mode-ctrl, sync, clk-gen, sytem-test
CTRL-Data
CIC/FIR
Decimate,
interpolate,
resample
Data IO-Par
IO-Ser
CTRL-Data
Mux/Switch Mux/Switch Mux/Switch
Binary
Data-
Source
Frequency
Synthesis
(DDS)
Digital OFDM - Transceiver
FEC
Coding
(1/2, 3/4, 9/16)
Scrambler
Interleaver
QAM-
Mapping
FRAME-
Assembly
Pilot-Ins.
Binary
Data-
Sink
FEC
Decoding
(1/2, 3/4, 9/16)
De-
scrambler
De-
Interleaver
QAM-
Decisions
Channel
Equalization
Post-AFC
IFFT-TX
64-points
Radix-(2)(4)
Add
Cyclic
Extension
FFT- RX
64-points
Radix-(2)(4)
Remove
Cyclic
Extension
Timing-
Frequency-
Correction
Windowing
RX-Data
TX-Data
A. Blaickner
ADC
RF-TX
Up-
converter
DAC
RF-TX
Up-
converter
CORDIC - Unit (Rotation-mode - Mixer, vector-mode - Sin/Cos-Gen)
Xin
A. Blaickner
Xout
CLK
ADD
SUB
REG Dly z-i
REG REG
ADD
SUB
REG
Dly z-i
REG REG
ANGLE-
Rotation
Stage - i
SGN
ADD
SUB
REG atan(2-i)
z-Path
ADD
SUB
REG Dly z-i
REG REG
ADD
SUB
REG
Dly z-i
REG REG
ANGLE-
Rotation
Stage - i
SGN
ADD
SUB
REG atan(2-i)
z-Path
ADD
SUB
REG Dly z-i
REG REG
ADD
SUB
REG
Dly z-i
REG REG
ANGLE-
Rotation
Stage - i
SGN
ADD
SUB
REG atan(2-i)
z-Path
Zout
Yin
Zin
Yout
9

Downconverter / Decimation FIR - Filter A. Blaickner '2000
8 - Tap FIR (c00,c08, ... ,cN-7)
8 - Tap FIR (c07,c15, ... ,cN-0)
8 - Tap FIR (c02,c10, ... ,cN-5)
8 - Tap FIR (c03,c11, ... ,cN-4)
8 - Tap FIR (c04,c12, ... ,cN-3)
8 - Tap FIR (c05,c13, ... ,cN-2)
8 - Tap FIR (c06,c14, ... ,cN-1)
8 - Tap FIR (c01,c08, ... ,cN-6)
Xin - 80MHz
Clk - 80MHz
Clk-
Ctrl
Real (I)
Imag (Q)

Data-Filter
RRCF / GAF
Matched Filter
64-Taps, I-Path
Delay z-n
(.)*
Rx-Data
Cplx - MULT Data-Filter
RRCF / GAF
Matched Filter
64-Taps, Q-Path
Carrier-Frequency
Direct Digital
Synthesi s
(DDS)
Decision
Devi ce
(Slicer)
Data
Symbold Timi ng
Estimator
Digital DMPSK - Demodulator A. Blaickner ' 2000
I
Q
Abs(.)
-2 0 2 -2
-1
0
1
2
Real
Im
ag
4
Z-plane
0 1 2 3 4 5 6 7 -4
-2
0
2
4
Frequency
M
agnitude
I
Q Mag
-2 0 2 -2
-1
0
1
2
Real
Im
ag
15
Z-plane
0 1 2 3 4 5 6 7 -2
-1
0
1
2
Frequency
M
agnitude
I
Q
Mag
-2 0 2 -2
-1
0
1
2
Real
Im
ag
9
Z-plane
0 1 2 3 4 5 6 7 -1
-0.5
0
0.5
1
Frequency
M
agnitude
I
Q
Mag
I
Q
I
-50 -40 -30 -20 -10 0 10 20 30 40 50 -0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
f
Results of Systems - Overview
M U X 4: 1
M U X 4:1
M U X 4:1
MU X 4:1
M U X 4:1
M U X 4: 1
M UX 4: 1
M UX 4:1
M U X 4: 1
MU X 4:1
M U X 4:1
MU X 4:1
M U X 4: 1
MU X 4:1
M U X 4:1
MU X 4:1
S00
S04
p00
p01
p02
p03
S08
S12
S01
S05
S09
S13
S02
S06
S10
S14
S03
S07
S11
S15
d00
d01
d02
d03
0 2 4 6 8 10 1 2 10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
10 -1
10 0
r(n)
y(n)
e(n)
a
0 500 1000 1500 2000 2500 10-5
10-4
10-3
10-2
10-1
100
Residuum
0 0.02 0.04 0.06
0
0.02
0.04
0.06
I
Q
Coefficients - e(n)
e(n),e(n+1)
0 0.01 0.02 0.03 0.04
0
0.01
0.02
0.03
I
Q
Coefficients - e(n)
e(n),e(n+1)
0 0.05 0.1
0
0.02
0.04
0.06
0.08
I
Q
Coefficients - e(n)
e(n),e(n+1)
0 0.1 0.2 0.3 0.4
0.7
0.8
0.9
1
1.1
I
Q
Coefficients - e(n)
e(n),e(n+1)
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Qam-sym
-1.5 -1 -0.5 0 0.5 1 1.5
-1.5
-1
-0.5
0
0.5
1
1.5
IFFT Tx
Rx FFT
Map Prc
Data
Sync
Sync
Par/Ser
Ser/Par
RAM-1 RAM-2
IOa IOb
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
10
-4
10-3
10-2
10
-1
10
0
Normalized frequency
R
elative pow
er density [dB
]
Equalizer
FFT/IFFT
POLY-
PHASE-FILTER
OFDM-Tx/Rx
Digital-Rx
Radix-2/4
Viterbi Codec
BMU
Modulation
Symbols
Decoded
Signal
Branch
Selector
Best State
Selector
Soft-
Decisions
ACSU
OPSU
BSSU
RXCH
0 2 4 6 8 10 12
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
BMU2
BMU2
Metric
nx5bit
BMU4
Soft-
Decisions
Soft-
Decisions
l 0000
l 0100
l 1000
l 1100
l 0001
l 0101
l 1001
l 1101
l 0010
l 0110
l 1010
l 1110
l 0011
l 0111
l 1011
l 1111
l m00 l m01 l m10 l m11
l n00
l n01
l n10
l n11
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
n n+1 n+2
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
n n+2
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4: 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4: 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4: 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4 : 1
M
U
X
4 : 1
S00
S04
p00
p01
p02
p03
S08
S12
S01
S05
S09
S13
S02
S06
S10
S14
S03
S07
S11
S15
d00
d01
d02
d03
10
Radix-2/4
Viterbi Codec
Branch and
path metric
calculation
Arbitrary
coding
schemes
Electromagnetic Field
Visualization
-10 -5 0 5 10
-10
-5
0
5
10
X-axis
-10 -5 0 5 10
-10
-5
0
5
10
X-axis
Y
- axi s
-10 -5 0 5 10
-10
-5
0
5
10
X-axis
Y
- axi s
Iso-Surface / Intensity - f(x,y)
11
Digital Signal Processing
Z-domain - IIR-band-pass filter
Impulse response
Magnitude spectra
z-plane
-4 -2 0 2 4
-4
-3
-2
-1
0
1
2
3
4
Real Part
Im
a
g
ina
ry
P
art
-4 -2 0 2 4
-4
-3
-2
-1
0
1
2
3
4
Real Part
Im
a
g
ina
ry
P
art
-150 -100 -50 0 50 100 150
-0. 5
0
0. 5
1
-150 -100 -50 0 50 100 150
-4
-2
0
2
4
-150 -100 -50 0 50 100 150
-4
-2
0
2
4
0 50 100 150 200 250 300
0
0. 5
1
Tsig
G
a
in
Time
0 50 100 150 200 250 300
-0. 5
0
0. 5
1 1.2 1.4 1. 6 1. 8 2 2.2 2.4 2. 6 2. 8 3
-0. 5
0
0. 5
1 1.2 1.4 1. 6 1. 8 2 2.2 2.4 2. 6 2. 8 3
-2
-1
0
1
Z-domain
IIR-band-pass
3-dim plot
12
0 50 100 150 200 250 300
0
0.5
1
Tsi g
G
ain
Time
0 50 100 150 200 250 300
-0.5
0
0.5
1
1 2 3 4 5 6 7 8 9
-2
-1
0
1
1 2 3 4 5 6 7 8 9
-1
0
1
Z-domain - FIR- Averaging Filter
Impulse response
Magnitude spectra
z-plane
-150 -100 -50 0 50 100 150
-10
0
10
-150 -100 -50 0 50 100 150
-5
0
5
-150 -100 -50 0 50 100 150
-10
0
10
-4 -2 0 2 4
-4
-2
0
2
4
Real Part
Im
a
g
in
a
r
y

P
a
r
t
7
-4 -2 0 2 4
-4
-2
0
2
4
Real Part
Im
a
g
in
a
r
y

P
a
r
t
7
Z-domain
3-dim plot
13
Base-band QAM-
Modulator
4..256 QAM
Eye- / Scatter-Plot
QAM-Phasor - Plot
Some MATlab Solutions
MatLab Script Programming
Vector- / Matrix - multiplexer function (switch)
RESULTab=[((SELseq==0).*DATAa + (SELseq>0).*DATAb);
Vector- / Matrix - comparator function
T re=(mod(hi,128)-128*(hi>127)); im=(mod(lo,128)-128*(lo>127));
Compact FSK-modulator & up-converter function
T Fnyq=0.5/Ssym;Wcar=Eta*(2*pi*Fnyq);Nco=cumsum(real(DatFil)); DatMod=exp(j*Wcar*Nco);
Structure based parameter lists - e.g. complex plot function
T TX.For=struct('Typ',{'Time'},'Sty',{'Stem','ReIm','ReIm','Cplx'});
TX.Dat=struct('Dat',{BinSrc,DatMap,DatFil},'Lab',{'Bsrc','Dmap,'Dfil'}); CplxPlot(TX);
Decimation Filter Core
T CoefRAM_ptr=COFidx+[1:1:COlen]; %Calc final index pointer vector Cram
PRODvec=DataDLYLIN.*CoefRAM(CoefRAM_ptr);%Multiply DlyLine Cvec, do for p0..pn
SUMpart=sum(PRODvec,2); SUMsca=SUMpart; %Accumulate all partial products p0..pn
DatInt(Ridx)=SUMsca; Ridx=Ridx+1; %Copy to filter result vector
Adaptive Filter Core
T for k=1:LOPlen; FilRes(k)=PolyIntp(DatInp(k:k+15).',
LPcof(PPcof(1+NCOmu(k),:))); end;
14
Some MATlab Solutions
Real-time Hardware Interface
MEX - file programming
// ------- MEX gateway function ------------------------------------------------------
void mexFunction( int nlhs, mxArray *plhs[], int nrhs, const mxArray *prhs[])
{
double Sps; //Samples per second from Patgen
double SplsRd; //Samples to read ...
if(nrhs!=3) mexErrMsgTxt("usage: DataOut=PATio.... ");
if(!mxIsNumeric(prhs[0])||!mxIsDouble(prhs[0])||... !=1) {mexErrMsgTxt("Input..");}
Sps = mxGetScalar(prhs[0]); /* get the scalar input x */
SplsRd = mxGetScalar(prhs[1]); /* get the scalar input x */
DataInp = mxGetPr(prhs[2]); /* create a pointer to the input matrix y */
NoCol = mxGetN(prhs[2]); /* get the dimensions of the matrix input y */
plhs[0] = mxCreateDoubleMatrix(1, (int)SplsRd, mxREAL); /* set the output pointer */
DataOut = mxGetPr(plhs[0]); /* create a C pointer to copy of output matrix */
PATio...(Sps,SplsRd,DataInp,NoCol,DataOut); /* call the C subroutine */
mxSetPr(plhs[0], DataOut); /* Load the new matrix data into plhs[0]. */
}
Conclusion
MATlab based Design of Digital Systems for Applications in the
Communications and Signal Processing Area
E.g. Channel coding, Synchronization units, Equalization
T High speed data transmission, typical system rate 50 ..100 Msps
T M-QAM, OFDM, FHSS, DSSS, ;
Typical application in 3G/4G Systems
T WLAN, UMTS, HIPERLAN, SET-TOP-BOX, xDSL, HFC, HOME-NETworks
HW/SW- co-design and prototyping of complex data path arithmetic
Re-programmability and re-use of standardized hardware proofed
Programmable array system simulator - P.A.S.S.
Digital modem / frequency synthesis / signal processing in general
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