Chapter 3: Implementation Technology: 2009 Spring CS211 Digital Systems & Lab

2009 Spring CS211 Digital Systems & Lab
CHAPTER 3: IMPLEMENTATION TECHNOLOGY
What will we learn in this chapter?

2
How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics of electronic circuits (partially covered) d)
Representation of Logic values by voltage levels

3
Threshold voltage Positive logic Negative logic Noise Margin
Voltage V DD Logic value 1 V 1,min Undefined V 0,max Logic value 0 V SS (Gnd) (G d)
Noise Margin
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Consider the following circuit

x f
N1

N2
Electronic circuits are constantly subjected to random noise It can alter the output voltage levels produced by the gate N1 It should not cause the gate N2 to misinterpret a low logic value as a high one one, or vice versa
Noise Margin
A measure of the extent to which a logic circuit can tolerate noise or unwanted spurious signals
Noise Margin
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the high state noise margin is defined as VNH = VOH(min) - VIH(min) the e low ow s state a e noise o se margin a g is s VNL = VIL(max) - VOL(max)
CMOS(5V) : 4.9V CMOS(2.5V) : 2.0V CMOS(5V) : 3.85V (1.05V) CMOS(2.5V) : 1.7V (0.3V) CMOS(5V) : 0.1V 0 1V CMOS(2.5V) : 0.4V CMOS(5V) : 1.35V (1.34V) CMOS(2.5V) : 0.7V (0.3V) 2009 Spring CS211 Digital Systems & Lab
Transistor Switches
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Logic circuits are built with transistors
Full treatment is beyond the scope of this class Metal oxide semiconductor field effect transistor (MOSFET) n-channel or nMOS p-channel or pMOS
Most popular type
Two types of MOSFET

NMOS transistor as a switch

7
Transistors: Voltage controlled switches

x = "low" x = "high"
(a) A simple switch controlled by the input x Gate Source Drain Substrate (Body) (b) NMOS transistor VG VS VD
(c) Simplified symbol for an NMOS transistor

NMOS transistors in logic circuits

VD VD =0V VD
VG
VS=0V Closed switch when V G = V DD Open switch when VG =0V
NMOS transistor
PMOS transistor as a switch

9
x = "high" "hi h"
x = "low" "l "
(a) A switch with the opposite behavior of Figure 3.2 Gate
Drain VDD Substrate ( (Body) y) (b) PMOS transistor VG VS
Source
VD
(c) Simplified symbol for a PMOS transistor

PMOS transistors in logic circuits

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V S = V DD
V DD
V DD
VG
VD
VD Open switch when V G = V DD
V D = V DD Closed switch when V G = 0 V
PMOS transistor
NMOS Logic Gates

11
A NOT gate built using NMOS technology

VDD R R Vf Vx Vx Vf
5V
+ -
(a) Circuit diagram
(b) Simplified circuit diagram
(c) Graphical symbols

NMOS realization of a NAND gate

12
VDD
x1 Vf Vx
1
x2
x1 x2 Vx
2
f 1 1 1 0
0 0 1 1 (a) Circuit
0 1 0 1
x1 x2 (c) Graphical symbols
(b) Truth table
NMOS realization
13
VDD
VDD
VDD
Vf
Vf Vx 1 Vx
2
x1 x2 0 0 1 1 0 1 0 1
f 1 0 0 0
A Vx1 x1 x2 Vx2 0 0 1 1 (a) Circuit 0 1 0 1 f 0 0 0 1
( ) Ci (a) Circuit it
(b) Truth table
(b) Truth table
x1 x2
x1 x2
x1 x2
x1 x2

Structure of an NMOS circuit

14
V DD
Vf Vx Vx
1
Pull-down Pull down network (PDN)

n
What is the PDN?

What will we learn in this chapter?

15
How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics of electronic circuits (partially covered) d)
CMOS realization
16
VDD
V DD
T1 Vx T2 Vf
Vx
1
T1
T2 Vf T3 x1 x2 0 0 1 1 0 1 0 1 T1 T2 T3 T4 on on off off on off off on off ff on on off ff off off on on f 1 1 1 0
Vx
T4
(a) Circuit x 0 1 T1 T2 on off off on f 1 0

( ) Ci (a) Circuit i
(b) T Truth h table bl and d transistor i states
(b) Truth table and transistor states

CMOS circuits
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DD
DD
S
D
T1 turn off
VGS=-5V<VT 0v
S
D
T1 V 1 T
turn on
5v
D
0v
T2 turn on
5v
D
T2
S
turn off
VGS=5V>VT VT1V
(a) Circuit
(a) Circuit
CMOS realization
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VDD
V DD
V DD
Vx
T1
Vx
V f
T2 Vf T3 T4 x1 x2 0 0 1 1 0 1 0 1 T1 T2 T3 T4 on on off off on off off on off on on off off off on on f 1 0 0 0
V x
V x
(a) Circuit
(b) Truth table and transistor
f=?
Circuit for Example 3.1

19
V DD
f= x1 + x2x3 f= x1(x2+x3)
Vf Vx
1
Vx Vx
Structure of a CMOS circuit

20
Why do we use CMOS circuits?

no power consumption under steady state conditions still have leakage current dynamic power consumption
V DD
What is the PDN? Why do we use NMOS in the PDN? What is the PUN? Why do we use PMOS in the PUN?
Pull-up network (PUN)
duals
Vf Vx Vx
1
Pull-down network (PDN)

n
Passing 1s and 0s through the transistor switches

21
NMOS can only partially pass a NM high voltage signal VDD VDD VGS VT
D
PMOS can only partially pass a low voltage signal VDD VGS -VT
S
D
VA=VDD-VT
For the typical value VT =0.2VDD
VA=VDD-0.1mV
A VDD
D
VA=0.1~0.2 mV
D
A V =V A T
A poor implementation (buffer)

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DD D
1.5VT S
DD D S
T1 turn on
T1
S
turn off VOL=1.5VT =1.5V turn on
5V
T2
D
VOH=VDD-1.5VT =3 5V =3.5V turn off
0V
T2
-1.5VT
Reversed connection
Reversed connection
Body effect: The substrate bias voltage increases the threshold voltage in the TR VT by a factor of about 1.5 or higher
Reversed connection
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Vf Vx1 VDD
Logic value x1 x2 0 0 1 1 0 1 0 1
Voltage Vf 1.5 V 1.5 V 15V 1.5 3.5 V
Logic value f 0 0 0 1
Vx2
( ) An (a) A AND gate t circuit i it
(b) Truth T th table t bl and d voltage lt levels l l
A Poor implementation p of a CMOS AND g gate

Positive and Negative logic

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VDD
x 1x 2 f 0 0 1 0 1 1 1 0 1 1 1 0
Vf Vx
1
x1 x2
Vx Vx
1
Vf H H H L
Vx
L L H H
L H L H
(a) Positive logic truth table and gate symbol

x 1x 2 f 1 1 0 1 0 0 0 1 0 0 0 1 x 1 x 2 f
(a) Circuit
(b) Voltage le
(b) Negative logic truth table and gate symbol
Why dont we use the mixed logic system? H How can we t treat t active ti low l signals? i l ?
A transmission gate
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Bidirectional Switch

NMOS passes 0 well and 1 poorly PMOS passes 1 well and 0 poorly
s x s ( ) Ci (a) Circuit i s=0 x x s=1 f=Z x f=x f s 0 1 f Z x
(b) Truth T th table t bl s f
(c) Equivalent circuit
s (d) Graphical symbol
A2 2-to-1 to 1 multiplexer
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Exclusive-OR Exclusive OR gate

27
x1 x2 0 0 1 1 0 1 0 1
f = x1 x2 0 1 1 0 x1 x2
f = x1 x2 (b) Graphical symbol
(a) Truth table
x1 x2 f = x1 x2
(c) Sum-of-products implementation

CMOS Exclusive Exclusive-OR OR gate

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x1 x2
f = x1 x2
(d) CMOS implementation
Standard chips: 7400 7400-series series

29
An approach in the mid-80s Various types

TTL CMOS
(a) Dual-inline package
Small Scale Integration (SSI) Other technologies

V DD Gnd
MSI : 10-100 gates VLSI : more than millions of transistors
(b) Structure of 7404 chip
Implementation of f = x1x2 + x2x3

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VDD
7404
7408
7432
x 2 x 3 x
Buffers
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To improve performance
to drive a large capacitive load

Non-inverting buffer Inverting buffer

Vx
V DD
Vf
+ + L L
(a) Small transistor (b) Larger transistor
W1
W2
(a) Implementation of a buffer
x
(b) Graphical symbol
Tri-state Tri state buffers

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e= 0 e x f x x f
e= 1 f
(a) A tri-state buffer

e x 0 0 1 1 0 1 0 1 f Z Z 0 1
(b) Equivalent circuit
e x f
( ) Truth table (c)
(d) Implementation
Four types of tri tri-state state buffers

33
x
(a)
x
(b)
x
(c)
x
(d)
An application of tri tri-state state buffers

34
x1 s x2
35
Pin 1 P Pin 2 P Pin 4 P Pin 6 P Pin 8 P Pin 12 2 Pin 14 4 Pin 16 6 Pin 18 8 Pin 19 9 Pin 3 P Pin 5 P Pin 7 P Pin 9 P Pin 11 Pin 13 3 Pin 15 5 Pin 17 7
74244 tri tri-state state buffer chip

Chapter 3: Implementation Technology: 2009 Spring CS211 Digital Systems & Lab

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2009 Spring CS211 Digital Systems & Lab