Basic HDL Coding Tech

Basic HDL Coding Techniques
Objectives
After completing this module, you will be able to:

Specify Xilinx resources that may need to be instantiated Identify some basic design guidelines that successful FPGA designers follow Select a proper HDL coding style for fast, efficient circuits, including:

Combinatorial functions Register functions State machines
Note: The guidelines in this module are not specific to any particular synthesis tool or Xilinx FPGA family
Basic HDL Coding Techniques - A - 2
2008 Xilinx, Inc. All Rights Reserved
Outline

Achieving Breakthrough Performance Basic Design Guidelines Coding for Combinatorial Logic Register Inference Finite State Machine Design Pipelining Summary
Breakthrough Performance
Three steps to achieve breakthrough performance

1. Utilize embedded (dedicated) resources

Dedicated resources are faster than a LUT/flip-flop implementation and consume less power Typically built with the CORE Generator tool and instantiated DSP48, FIFO, block RAM, ISERDES, OSERDES, PowerPC processor, EMAC, and MGT, for example Use synchronous design methodology Ensure the code is written optimally for critical paths Pipeline Try different optimization techniques Add critical timing constraints in synthesis Preserve hierarchy Apply full and correct constraints Use High effort
Virtex -5 FPGA Virtex Virtex-5 FPGA

Performance Meter
2. Write code for performance

3. Drive your synthesis tool

Use Embedded Blocks
Embedded block timing is correct by construction
Not dependent on programmable routing

XtremeDSP Solution Slice
Offers as much as 3x the performance of soft implementations Uses less power Examples

FIFO at 500 MHz DSP slices at 500 MHz PowerPC processor at 702 DMIPS
Smart RAM FIFO PowerPC Processor
Timing Closure
Outline

Instantiation versus Inference
Instantiate a component when you must dictate exactly which resource is needed

The synthesis tool is unable to infer the resource The synthesis tool fails to infer the resource Inference makes your code more portable
Xilinx recommends inference whenever possible
Xilinx recommends using the CORE Generator software to create functions such as Arithmetic Logic Units (ALUs), fast multipliers, and Finite Impulse Response (FIR) filters for instantiation Xilinx recommends using the Architecture Wizard utility to create DCM, PLL, and BUFG instantiations
FPGA Resources
Can be inferred by all synthesis tools
Can be inferred by some synthesis tools

Shift register LUT (SRL16/ SRLC16) F5, F6, F7, and F8 multiplexers Carry logic MULT_AND Multipliers and counters using the DSP48 Global clock buffers (BUFG) SelectIO (single-ended) interface I/O registers (single data rate) Input DDR registers
Memories Global clock buffers (BUFGCE, BUFGMUX, BUFGDLL) Some complex DSP functions
Cannot be inferred by any synthesis tools

SelectIO (differential) interface Output DDR registers DCM / PLL Local clock buffers (BUFIO, BUFR)
Suggested Instantiation
Xilinx recommends that you instantiate the following elements
Memory resources
Block RAMs specifically (use the CORE Generator software to build large memories)
SelectIO interface resources Clocking resources

DCM, PMCD (use the Architecture Wizard) IBUFG, BUFGMUX, BUFGCE BUFIO, BUFR
Suggested Instantiation
Why does Xilinx suggest this?
START UP
Xilinx wrapper top_xlnx

OBUF _GTL DCM BUFG
Easier to port your HDL to other and newer technologies Fewer synthesis constraints and attributes to pass on
IBUFG
IBUF _SSTL2_I
Top-Level Top-Level Block Block
OBUF _GTL
OBUF _GTL
Keeping most of the attributes and constraints in the Xilinx User Constraints File (UCF) keeps it simpleone file contains critical information
Create a separate hierarchical block for instantiating these resources
Above the top-level block, create a Xilinx wrapper with instantiations specific to Xilinx
Hierarchy Management

Synplify, Precision, and XST software The basic settings are
Flatten the design: Allows total combinatorial optimization across all boundaries Maintain hierarchy: Preserves hierarchy without allowing optimization of combinatorial logic across boundaries
If you have followed the synchronous design guidelines, use the setting -maintain hierarchy If you have not followed the synchronous design guidelines, use the setting -flatten the design Your synthesis tool may have additional settings
Refer to your synthesis documentation for details on these settings

Hierarchy Preservation Benefits

Easily locate problems in the code based on the hierarchical instance names contained within static timing analysis reports Enables floorplanning and incremental design flow The primary advantage of flattening is to optimize combinatorial logic across hierarchical boundaries
If the outputs of leaf-level blocks are registered, there is generally no need to flatten
Outline

Multiplexers
Multiplexers are generated from IF and CASE statements

IF/THEN statements generate priority encoders Use a CASE statement to generate complex encoding Delay and size
There are several issues to consider with a multiplexer
Affected by the number of inputs and number of nested clauses to an IF/THEN or CASE statement Generated when IF/THEN or CASE statements do not cover all conditions Review your synthesis tool warnings Check by looking at the component with a schematic viewer
Unintended latches or clock enables

IF/THEN Statement Answer
Priority Encoder

Most critical input listed first Lease critical input listed last
do_e 0 do_c 1 IF (crit_sig) THEN oput <= do_d ; ELSIF cond_a THEN oput <= do_a; ELSIF cond_b THEN oput <= do_b; ELSIF cond_c THEN oput <= do_c; ELSE oput <= do_e; END IF;
0
do_b
do_a
oput
cond_c
do_d
cond_b
cond_a
crit_sig
Avoid Nested IF and IF/ELSE Statements

Nested IF or IF/THEN/ELSE statements form priority encoders CASE statements do not have priority If nested IF statements are necessary, put critical input signals on the first IF statement
The critical signal ends up in the last logic stage
CASE Statements
CASE statements in a combinatorial process (VHDL) or always statement (Verilog)

Latches are inferred if outputs are not defined in all branches Use default assignments before the CASE statement to prevent latches
CASE statements in a sequential process (VHDL) or always statement (Verilog)

Clock enables are inferred if outputs are not defined in all branches This is not wrong, but might generate a long clock enable equation Use default assignments before CASE statement to prevent clock enables
CASE Statements
Register the select inputs if possible (pipelining)
Can reduce the number of logic levels between flip-flops Eliminating the select decoding can improve performance
Consider using one-hot select inputs
Determine how your synthesis tool synthesizes the order of the select lines
If there is a critical select input, this input should be included last in the logic for fastest performance
CASE Statement
This Verilog code describes a 6:1 multiplexer with binary-encoded select inputs
module case_binary (clock, sel, data_out, in_a, in_b, in_d, in_c, in_e, in_f) ; input clock ; input [2:0] sel ; input in_a, in_b, in_c, in_d, in_e, in_f ; output data_out ; reg data_out; always @(posedge clock) begin case (sel) 3'b000 : data_out <= in_a; 3'b001 : data_out <= in_b; 3'b010 : data_out <= in_c; 3'b011 : data_out <= in_d; 3'b100 : data_out <= in_e; 3'b101 : data_out <= in_f; default : data_out <= 1'bx; endcase end endmodule
This synthesized to 3 LUTs and 2 F5 muxes Longest path = 1 LUT + 2 F5
The advantage of using the dont care for the default, is that the synthesizer will have more flexibility to create a smaller, faster circuit How could the code be changed to use one-hot select inputs?
10
CASE Statement
module case_onehot (clock, sel, data_out, in_a, in_b, in_d, in_c, in_e, in_f) ;
This is the same code with one-hot select inputs
This synthesized to 8 LUTs and 1 F5 mux Longest path = 2 LUTs + 1 F5 This yields no benefit for 6-1 mux, but when you get larger the benefit is significant
input clock ; input [5:0] sel ; input in_a, in_b, in_c, in_d, in_e, in_f ; output data_out ; reg data_out; always @(posedge clock) begin case (sel) 6'b000001 : data_out <= in_a; 6'b000010 : data_out <= in_b; 6'b000100 : data_out <= in_c; 6'b0010 00: data_out <= in_d; 6'b010000 : data_out <= in_e; 6'b100000 : data_out <= in_f; default : data_out = 1'bx; endcase end endmodule
Other Basic Performance Tips
Avoid high-level loop constructs
Synthesis tools may not produce optimal results A <= B + C + D + E; should be: A <= (B + C) + (D + E) Better system control
Order and group arithmetic and logical functions and operators
Use synchronous reset
11
Synchronous Design Rewards
Always make your design synchronous
Recommended for all FPGAs Waste device resources
Failure to use synchronous design can potentially
Not using a synchronous element will not save silicon and it wastes money Reduces capability of end products; higher speed grades cost more Difficult timing specifications and tool-effort levels Probability, race conditions, temperature, and process effects
Waste performance
Lead to difficult design process
Cause long-term reliability issues
Synchronous designs have

Few clocks Synchronous resets No gated clocks; instead, clock enables
Ken Chapman (Xilinx UK) 2003
Outline

12
Inferred Register Examples

Ex 1 D Flip-Flop always @(posedge CLOCK) Q = D_IN; Ex 2. D Flip-Flop with Asynch Preset always @(posedge CLOCK or posedge PRESET) if (PRESET) Q = 1; else Q = D_IN; Ex 4. D Flip-Flop with Synch Reset always @(posedge CLOCK) if (RESET) Q = 0; else Q = D_IN;
Ex 3. D Flip-Flop with Asynch Reset always @(posedge CLOCK or posedge RESET) if (RESET) Q = 0; else Q = D_IN;
Clock Enables
Coding style will determine if clock enables are used

VHDL
FF_AR_CE: process(ENABLE,CLK) begin if (CLKevent and CLK = 1) then if (ENABLE = 1) then Q <= D_IN; end if; end if; end process
Verilog
always @(posedge CLOCK) if (ENABLE) Q = D_IN;
13
Outline

State Machine Design
Put the next-state logic in one CASE statement
Inputs to FSM S2 S1 State Machine Module S3
The state register can also be included here or in a separate process block or always block
Put the state machine outputs in a separate process or always block
S5
S4 HDL Code
Prevents resource sharing, which can hurt performance
Next-state logic State register State machine outputs
14
The Perfect State Machine
The perfect state machine has

Inputs: Input signals and state jumps Outputs: Output states and control and enable signals to the rest of the design NO arithmetic logic, datapaths, or combinatorial functions inside the state machine
Current State Feedback to Drive State Jumps
State Register
Input Signals
State Jumps Only!
Next State
Output State and Enables
State Machine Encoding
Use enumerated types to define state vectors (VHDL)
Most synthesis tools have commands to extract and re-encode state machines described in this way Uses more registers, but simplifies next-state logic Examine trade-offs: Gray and Johnson encoding styles can also improve performance Refer to the documentation of your synthesis tool to determine how your synthesis tool chooses the default encoding scheme
Use one-hot encoding for high-performance state machines

Register state machine outputs for higher performance
15
Benefits of FSM Encoding
Binary

Smallest (fewest registers) Complex FSM tends to build multiple levels of logic (slow) Synthesis tools usually map to this encoding when FSM has eight or fewer states Largest (more registers), but simplifies next-state logic (fast) Synthesis tools usually map this when FSM has between 8 and 16 states Always evaluate undefined states (you may need to cover your undefined states) Efficient size and can have good speed Depends on the number of states, inputs to the FSM, complexity of transitions Build your FSM and then synthesize it for each encoding and compare size and speed
One-hot

Gray and Johnson
Which is best?
How do you determine which is best?
State Machine Example (Verilog)

module STATE(signal_a, signal_b, clock, reset, usually_one, usually_zero); input output reg [4:0] parameter signal_a, signal_b, clock, reset; usually_one, usually_zero; current_state, next_state; s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;
always @(posedge clock or posedge reset) begin if (reset) begin current_state <= s0; end else current_state <= next state; end
16
State Machine Example (Verilog)

always @ (current_state or signal_a or signal_b) begin case (current_state) s0: if (signal_a) next_state = s0; else next_state = s1; s1: if (signal_a && ~signal_b) next_state = s4; else next_state = s2; s2: next_state = s4; s3: next_state = s3; s4: next_state = s0; default: next_state = bx; endcase end end endmodule
Binary Encoding (Verilog)

reg [3:0] current_state, next_state; parameter state1 = 2b00, state2 = 2b01, state3 = 2b10, state4 = 2b11; always @ (current_state) case (current_state) state1 : next_state = state2; state2 : next_state = state3; state3 : next_state = state4; state4 : next_state = state1; endcase always @ (posedge clock) current_state = next_state;
17
One-Hot Encoding (Verilog)

reg [4:0] current_state,next_state; parameter state1 = 4b0001, state2 = 4b0010, state3 = 4b0100, state4 = 4b1000; always @ (current_state) case (current_state) state1 : next_state = state2; state2 : next_state = state3; state3 : next_state = state4; state4 : next_state = state1; endcase always @ (posedge clock) current_state = next_state;
State Machine Example (VHDL)

library IEEE; use IEEE.std_logic_1164.all; entity STATE is port ( signal a, signal b: in STD_LOGIC; clock, reset: in STD_LOGIC; usually_zero, usually_one: out STD_LOGIC ); end STATE; architecture STATE_arch of STATE is type STATE_TYPE is (s0,s1, s2, s3); signal current_state, next_state: STATE_TYPE; signal usually_zero_comb, usually_one_comb : STD_LOGIC; begin
18

COMB_STATE_MACHINE: process(current_state, signal a, signal b) begin next_state <= s0; usually_zero_comb <= '0'; usually_one_comb <= '1'; -- set default to one and reset to zero when necessary case current_state is when s0 => next_state <= s1; if signal a = '1' then next_state <= s0; end if; when s1 => next_state <= s2; if signal a='1' AND signal b = '0' then next_state <= s3; usually_zero_comb <= '1'; end if; when s2 => next_state <= s3; when s3 => usually_one_comb <= '0'; next_state <= s3; when others => next_state <= s0; end case; end process;

SYNCH_STATE_MACHINE: process(clock, reset) begin if (reset = '1') then current_state <= s0; usually_zero <= '0'; usually_one <= '1'; elsif (clock'event and clock = '1') then current_state <= next_state; usually_zero <= usually_zero_comb; usually_one <= usually_one_comb; end if; end process; end STATE_arch;
19
Unspecified Encoding (VHDL)

entity EXAMPLE is port( A,B,C,D,E, CLOCK: in std_logic; X,Y,Z: out std_logic); end EXAMPLE; architecture XILINX of EXAMPLE is type STATE_LIST is (S1, S2, S3, S4, S5, S6, S7); signal STATE: STATE_LIST; begin P1: process( CLOCK ) begin if( CLOCKevent and CLOCK = 1) then case STATE is when S1 => X <= 0; Y <= 1; Z <= 1; if( A = 1 ) then STATE <= S2; else STATE <= S1;
One-Hot Encoding (VHDL)

architecture one-hot_arch of one-hot is subtype state_type is std_logic_vector(5 downto 0); signal current_state, next_state: state_type; constant s0 : state_type := "000001"; constant s0_bit : integer := 0; constant s1_bit : integer := 1; constant s2_bit : integer := 2; constant s3_bit : integer := 3; constant s4a_bit : integer := 4; constant s4b_bit : integer := 5; signal usually_zero_comb, usually_one_comb : std_logic; begin comb_state_machine: process(current_state, signal a, signal b, signal c, signal d) begin next_state <= state_type'(others => '0'); if current_state(s0_bit) = '1' then if signal a = '1' then next_state(s0_bit) <= '1'; else next_state(s1_bit) <= '1'; end if; end if; if current_state(s1_bit) = '1' then next_state(s4a_bit) <= '1'; end if; end; end;
20
Outline

Pipelining Concept
fMAX = n MHz
D Q
two logic levels
fMAX 2n MHz
one level
one level
21
Pipelining
Three situations in which to pipeline
Register the outputs of each lower leaf-level output

Typically done after timing analysis Can easily be done for purely combinatorial components Usually done by the designer from the beginning
Register I/O
Register high-fanout secondary control signals (Set, Reset, CEs)
Performance by Design
D Q
Switch High fanout
Code A
Two levels of logic (connections dominate) May require higher speed grade, adding cost Switch
D Q
Enable data_in
CE D Q
reg_data
Code B
One level of logic Maximum time for routing of high fanout net Flip-flop adds nothing to the cost
D Q
reg_enable High fanout
D Q
Enable data_in
CE D Q
reg_data
Tip: Remember that the LUT output feeds the D input to the flip-flop
Ken Chapman (Xilinx UK) 2003
22
Performance by Design (Verilog)
These two pieces of code are not functionally identical
The code on the right forms a pipeline stage for the circuit and improves its speed
Code B always @(posedge clk) begin if (set_in && enable_in) reg_enable <= 1'b1; else reg_enable <= 1'b0; if (reg_enable) reg_data <= data_in; end
Code A always @(posedge clk) begin if (switch && enable) reg_data <= data_in; end
In each case

reg_data and data_in are 16-bit buses switch and enable are outputs from flip-flops
Performance by Design (VHDL)
These two pieces of code are not functionally identical
Code A capture: process (clk) begin if clk'event and clk='1' then if switch='1 and enable=1 then reg_data <= data_in; end if; end if; end process;
Code B capture: process (clk) begin if clk'event and clk='1' then if switch ='1 and enable=1 then reg_enable <= 1; else reg_enable <= 0; end if; if reg_enable='1 then reg_data <= data_in; In each case end if; reg_data and data_in are 16-bit buses end if; switch and enable are outputs from flip-flops end process;
The code on the right forms a pipeline stage for the circuit and improves its speed
23
Outline

Apply Your Knowledge
What is the approach presented here for obtaining breakthrough performance? Compare CASE and IF/THEN statements when creating multiplexers What problem occurs with nested CASE and IF/THEN statements?
24
Answers
What is the approach presented here for obtaining breakthrough performance?
Three steps to achieve breakthrough performance
1. Utilize embedded (dedicated) resources Performance by construction DSP48, FIFO, block RAM, ISERDES, OSERDES, PowerPC processor, EMAC, and MGT, for example 2. Write code for performance Pipeline Xilinx FPGAs have abundant registers: one register per LUT 3. Drive your synthesis tool Apply full and correct constraints Utilize optional settings Use High effort
Answers
Compare CASE and IF/THEN statements when creating multiplexers

Both types of statements produce multiplexers CASE statements produce smaller/faster circuits in general IF/THEN statements are more flexible but create a priority encoder IF/THEN statements may be faster for late arriving signals Nested CASE and IF/THEN statements can generate long delays due to cascaded functions
What problem occurs with nested CASE and IF/THEN statements?
25
Summary
Use as much of the dedicated hardware resources as possible to ensure optimum speed and device utilization Plan on instantiating clocking and memory resources Try to use the Core Generator tool to create optimized components that target dedicated FPGA resources (BRAM, DSP48, and FIFO) Maintain your design hierarchy to make debugging, simulation, and report generation easier CASE and IF/THEN statements produce different types of multiplexers
CASE statements tend to build logic in parallel while IF/THEN statements tend to build priority encoders
Avoid nested CASE and IF/THEN statements
Summary

You should always build a synchronous design for your FPGA Inferring many types of flip-flops from HDL code is possible
Synchronous sets/resets are preferred
When coding a state machine, separate the next-state logic from state machine output equations Evaluate whether you need to use binary, one-hot, or Gray encoding style for your FSM
This will yield a smaller and/or faster FSM
Pipeline data paths to improve speed
26
Where Can I Learn More?
Synthesis & Simulation Design Guide
www.xilinx.com/support Documentation Search for Synthesis & Simulation Design Guide www.xilinx.com/support Documentation Search for User Guides www.xilinx.com/support Documentation Search for XST This guide has example inferences of many architectural resources Start Xilinx ISE 10.1i Documentation Software Manuals
User guides
XST User Guide

ISE online help
27

Basic HDL Coding Tech

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Basic HDL Coding Tech

Загружено:

Авторское право:

Доступные форматы

Basic HDL Coding Techniques

Combinatorial functions Register functions State machines

Basic HDL Coding Techniques - A - 2

2008 Xilinx, Inc. All Rights Reserved

Basic HDL Coding Techniques - A - 3

2008 Xilinx, Inc. All Rights Reserved

Three steps to achieve breakthrough performance

Virtex -5 FPGA Virtex Virtex-5 FPGA

2. Write code for performance

3. Drive your synthesis tool

Basic HDL Coding Techniques - A - 4

Use Embedded Blocks

Embedded block timing is correct by construction

Not dependent on programmable routing

Smart RAM FIFO PowerPC Processor

Basic HDL Coding Techniques - A - 5

2008 Xilinx, Inc. All Rights Reserved

Basic HDL Coding Techniques - A - 6

2008 Xilinx, Inc. All Rights Reserved

Basic HDL Coding Techniques - A - 7

2008 Xilinx, Inc. All Rights Reserved

Instantiation versus Inference

Xilinx recommends inference whenever possible

Basic HDL Coding Techniques - A - 8

2008 Xilinx, Inc. All Rights Reserved

Can be inferred by all synthesis tools

Can be inferred by some synthesis tools

Cannot be inferred by any synthesis tools

Basic HDL Coding Techniques - A - 9

2008 Xilinx, Inc. All Rights Reserved

Xilinx recommends that you instantiate the following elements

SelectIO interface resources Clocking resources

Basic HDL Coding Techniques - A - 10

2008 Xilinx, Inc. All Rights Reserved

Why does Xilinx suggest this?

Xilinx wrapper top_xlnx

Top-Level Top-Level Block Block

Create a separate hierarchical block for instantiating these resources

Basic HDL Coding Techniques - A - 11

Synplify, Precision, and XST software The basic settings are

Refer to your synthesis documentation for details on these settings

Basic HDL Coding Techniques - A - 12

Hierarchy Preservation Benefits

Basic HDL Coding Techniques - A - 13

2008 Xilinx, Inc. All Rights Reserved

Basic HDL Coding Techniques - A - 14

2008 Xilinx, Inc. All Rights Reserved

Multiplexers are generated from IF and CASE statements

There are several issues to consider with a multiplexer

Unintended latches or clock enables

Basic HDL Coding Techniques - A - 15

2008 Xilinx, Inc. All Rights Reserved

IF/THEN Statement Answer

Basic HDL Coding Techniques - A - 16

2008 Xilinx, Inc. All Rights Reserved

Avoid Nested IF and IF/ELSE Statements

The critical signal ends up in the last logic stage

Basic HDL Coding Techniques - A - 17

2008 Xilinx, Inc. All Rights Reserved

CASE statements in a combinatorial process (VHDL) or always statement (Verilog)

CASE statements in a sequential process (VHDL) or always statement (Verilog)

Basic HDL Coding Techniques - A - 18

2008 Xilinx, Inc. All Rights Reserved

Register the select inputs if possible (pipelining)