Outline

s VHDL s VHDL s VHDL

Background/History Design Example Model Components

Entity Declarations Architecture Descriptions

s Basic

Syntax and Lexicographical Conventions

Reasons for Using VHDL

s VHDL

Is an International IEEE Standard Specification Language (IEEE 1076-1993) for Describing Digital Hardware Used by Industry Worldwide
VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

Reasons for Using VHDL

s VHDL

enables hardware modeling from the gate to system level provides a mechanism for digital design and reusable design documentation Provides a Common Communications Medium

s VHDL

s VHDL

A Brief History of VHDL

s Very

High Speed Integrated Circuit (VHSIC) Program

Launched in 1980 Object was to achieve significant gains in VLSI technology by shortening the time from concept to implementation (18 months to 6 months) Need for common descriptive language

A Brief History of VHDL

s Woods

Hole Workshop

Held in June 1981 in Massachusetts Discussion of VHSIC goals Comprised of members of industry, government, and academia

A Brief History of VHDL

sJuly

1983: contract awarded to develop VHDL

Intermetrics IBM Texas Instruments

sAugust

1985: VHDL Version 7.2 released

A Brief History of VHDL

s December

1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard s September 1993: VHDL was restandardized to clarify and enhance the language s VHDL has been accepted as a Draft International Standard by the IEC

Gajski and Kuhns Y Chart

Architectural Behavioral Algorithmic Processor Systems Algorithms Register Transfer Logic Transfer Functions Functional Block Logic Circuit Hardware Modules ALUs, ALUs, Registers Gates, FFs Transistors Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions Structural

Copyright 1995, 1996 RASSP E&F

Physical/Geometry

VHDL Model
Package Generic Entity Ports

Behavioral Architecture

Functional Architecture

Dataflow Architecture

Structural Architecture

VHDL Combinational Template

Every VHDL model is composed of an entity and at least one architecture . Entity describes the interface to the model (inputs, outputs) Architecture describes the behavior of the model Can have multiple architectures for one entity (we will only use one in this class).

A VHDL Template for Combinational Logic

entity model_name is port ( list of inputs and outputs ); end model_name; architecture arch_name of model_name is begin concurrent statement 1 concurrent statement 2 ... concurrent statement N; end arch_name ; All of the text not in italics are VHDL keywords. VHDL is NOT case sensitive. (ENTITY is same as entity is same as EnTiTy).

Order of these statements is not important

VHDL Design Example

s

Problem: Design a single bit half adder with carry and enable Specifications Inputs and outputs are each one bit When enable is high, result gets x plus y When enable is high, carry gets any carry of x plus y Outputs are zero when enable input is low
x y enable Half Adder carry result

Copyright 1995, 1996 RASSP E&F

VHDL Design Example

Entity Declaration
s As

a first step, the entity declaration describes the interface of the component
input and output ports are declared

ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END half_adder;

We will, at least at first, use capitals and colors to denote VHDL language components
Copyright 1995, 1996 RASSP E&F

x y enable

Half Adder

carry result

VHDL Design Example

Functional Specification
sA

high level description can be used to describe the function of the adder
ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = 1 THEN result <= x XOR y; carry <= x AND y; ELSE carry <= 0; result <= 0; END IF; END PROCESS; END half_adder_a;

s The

Copyright 1995, 1996 RASSP E&F

model can then be simulated to verify correct functionality of the component

VHDL Design Example

Behavioral Specification
sA

high level description can be used to describe the function of the adder
ARCHITECTURE half_adder_b OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = 1 THEN result <= x XOR y after 10ns; carry <= x AND y after 12 ns; ELSE carry <= 0 after 10ns; result <= 0 after 12ns; END IF; END PROCESS; END half_adder_b;

timing

s The

model can then be simulated to verify correct timing of the entity

Copyright 1995, 1996 RASSP E&F

VHDL Design Example

Data Flow Specification
sA

Third Method Is to Use Logic Equations to Develop a Data Flow Description

ARCHITECTURE half_adder_c OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_c; q

Again, the model can be simulated at this level to confirm the logic equations

Copyright 1995, 1996 RASSP E&F

VHDL Design Example

Structural Specification
s As

a Fourth Method, a Structural Description Can Be Created From Previously Described Components s These gates can be taken from a library of parts
x y enable carry result

Copyright 1995, 1996 RASSP E&F

VHDL Design Example

Copyright 1995, 1996 RASSP E&F

Structural Specification (Cont.)

ARCHITECTURE half_adder_d OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); -- description is continued on next slide

VHDL Design Example

Structural Specification (Cont.)
-- continuing half_adder_d description SIGNAL xor_res : BIT; -- internal signal -- Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_d;

Copyright 1995, 1996 RASSP E&F

VHDL Model Components

sA

Complete VHDL Component Description Requires a VHDL Entity and a VHDL Architecture
The entity defines a components interface The architecture defines a components function

s Several

Alternative Architectures May Be Developed for Use With the Same Entity

VHDL Model Components

s Three

Areas of Description for a VHDL Component:

Structural descriptions Functional descriptions Timing and delay descriptions (Behavioral)

Majority Gate Example

The following is an example of a three input XOR gate (majority gate) implemented in VHDL
library ieee; use ieee.std_logic_1164.all; entity majority is port ( A, B, C : in std_logic; -- two dashes is a COMMENT in VHDL Y: out std_logic ); end majority; -- this is the architecture declaration, uses only one concurrent statement. ARCHITECTURE concurrent of majority is begin Y <= (A and B) or (A and C) or (B and C); end concurrent;

This is a style of one big expression

Majority Gate with Temporary Signals

The following version of the majority gate uses some temporary signals (entity has been left out, is same).
-- the architecture now uses 4 concurrent statements ARCHITECTURE newconc of majority is signal t1, t2, t3 : std_logic ; begin t1 <= A and B; t2 <= A and C; t3 <= B and C; Y <= t1 or t2 or t3; end newconc;

Majority gate: Variant 2

Explain why this style is often more convenient to use

Note that temporary signals are declared between architecture statement and begin statement.
Concurrent statement, no process

Majority Gate with when-else statement

The following version of the majority gate uses a 'when-else' statement: -- the architecture now uses a when-else statement. ARCHITECTURE whenelse of majority is

begin Y <= '1' when ( (A and B) or (A and C) or (B and C)) else '0'; end whenelse; Concurrent statement, no process You will find that there are many different ways to accomplish the same result in VHDL. There is usually no best way; just use one that you feel most comfortable with.

Majority gate: Variant 3

Concurrent Versus Sequential Statements

The statements we have looked at so far are called concurrent statements.
Each concurrent statement will synthesize to a block of logic.

Another class of VHDL statements are called sequential statements.

Sequential statements can ONLY appear inside of a process block. A process block is considered to be a single concurrent statement. Can have multiple process blocks in an architecture. Usually use process blocks to describe complex combinational or sequential logic.

Process
s Fundamental

Unit for Component Behavior Description Is the Process

Processes may be explicitly or implicitly defined They are packaged in architectures

VHDL Model Components

s Primary

Communication Mechanism Is the Signal (distinct from a variable)

Process executions result in new values being assigned to signals which are then accessible to other processes Similarly, a signal may be accessed by a process in another architecture by connecting the signal to ports in the the entities associated with the two architectures Note symbol
Output Output <= <= My_id My_id + + 10; 10;

used for signals

VHDL Entity
s The

Primary Purpose of an Entity Is to Declare the Input and Output Signals Which Communicate With It.
Interface signals are listed in the PORT clause which has 3 parts: Name Mode Data type

VHDL Entity Example

ENTITY OR3 IS PORT ( A, B, C D : IN : OUT BIT; BIT );

END OR3;

Entity Declarations
sThe

Primary Purpose of the Entity Is to Declare the Signals in the Components Interface
The interface signals are listed in the PORT clause
In this respect, the entity is akin to the schematic symbol for the component

Copyright 1995, 1996 RASSP E&F

Entity versus Schematic Symbol

Entity Example
x y enable Half Adder carry result

ENTITY half_adder IS GENERIC(prop_delay : TIME := 10 ns); PORT( x, y, enable : IN BIT; carry, result : OUT BIT); END half_adder;

Entity Declarations
Port Clause
s

PORT clause declares the interface signals of the object to the outside world Three parts of the PORT clause
Name Mode Data type
signal_name PORT ); signal_name : mode data_type data_type PORT ( ( : mode );

Note port signals (i.e. ports) of the same mode and type or subtype may be declared on the same line
name mode Data type

PORT PORT ( ( input input : : IN IN BIT_VECTOR(3 BIT_VECTOR(3 DOWNTO DOWNTO 0); 0); ready, ready, output output : : OUT OUT BIT BIT ); );
Copyright 1995, 1996 RASSP E&F

Entity Declarations
Port Clause (Cont.)
s The

Port Mode of the Interface Describes the Direction in Which Data Travels With Respect to the Component s Five Port Modes
1. IN: data comes in this port and can only be read 2. OUT: data travels out this port

Entity Declarations
Port Clause (Cont.)
3. BUFFER: bidirectional data, but only one signal driver may be enabled at any one time 4. INOUT: bidirectional data with any number of active drivers allowed but requires a Bus Resolution Function 5. LINKAGE: direction of data is unknown

Entity Declarations
Generic Clause
s Generics

May Be Used for:

Readability, Maintenance, Configuration.

s Generic

Clause Syntax :

generic_name GENERIC ]); generic_name : type [:= default_value GENERIC ( ( : type [:= default_value ]);

If optional default_value is missing in generic clause declaration, it must be present when component is to be used (i.e. instantiated)
Copyright 1995, 1996 RASSP E&F

Behavioral Descriptions
s VHDL

Provides Two Styles of Describing Component Behavior

Data Flow: concurrent signal assignment statements Behavioral: processes used to describe complex behavior by means of high-level language constructs
variables, loops, if-then-else statements, etc.

Copyright 1995, 1996 RASSP E&F

Majority Gate using process block and if statement

The entity declaration has been left out (same as before).
ARCHITECTURE ifstate of majority is begin main: process (A, B, C) begin Y <= '0'; -- default output assignment. if ((A = '1') and (B = '1')) then Y <= '1'; end if; if ((A = '1') and (C = '1') ) then Y <= '1'; end if; if ((B = '1') and (C = '1') ) then Y <= '1'; end if; end process main; end ifstate;

name of a process

Majority gate: Variant 4

name of a process
process

Comments on process block model

The first line in the process "main: process (A, B, C)" has the name of the process (main) and the sensitivity list of the process.
The process name is user defined, can also be left out (unnamed process). The sensitivity list should contain any signals that appear on the right hand side of an assignment (inputs) or in any boolean for a sequential control statement.

The if statement condition must return a boolean value (TRUE or FALSE) so that is why the conditional is written as: ( (A='1') and (B= '1') ) Cannot write it as: ( A and B) because this will return a 'std_logic' type (more on types later).

ARCHITECTURE ifelse of majority is begin process (A, B, C) begin

Use of if-else
Comments: Process is anonymous (no name) Used an 'else' clause to specify what the output should be if the if condition test was not true. CAREFUL! use parenthesis to define precedence order

if (((A = '1') and (B = '1')) or ((A = '1') and (C = '1')) or ((B = '1') and (C = '1')) ) then Y <= '1'; else Y <= '0'; end if; end process; end ifelse;

Majority gate: Variant 5

process

Generic Clause
s

Generic Clause Example :

GENERIC GENERIC (My_ID (My_ID : : INTEGER INTEGER := := 37); 37);

The generic My_ID, with a default value of 37, can be referenced by any architecture of the entity with this generic clause The default can be overridden at component instantiation
GENERIC can be time, current, voltage, signal..

Architecture Bodies
sDescribes

the Operation of the Component, Not Just Its Interface

sMore

Than One Architecture Can (and Usually Is) Associated With Each Entity

Architecture Bodies
s Architecture

Body consists of Two Parts:

1. Declarative part -- includes necessary declarations, e.g. :

type declarations signal declarations component declarations subprogram declarations

Architecture Bodies
2. Statement part -- includes statements that describe organization and/or functional operation of component, e.g. : concurrent signal assignment statements process statements component instantiation statements

Architecture Body Example

ARCHITECTURE half_adder_d OF half_adder IS -- architecture declarative part SIGNAL xor_res : BIT ; -- architecture statement part BEGIN carry <= enable AND (x AND y) ; result <= enable AND xor_res ; xor_res <= x XOR y ; END half_adder_d ;

Lexical Elements of VHDL

s Comments

two dashes to end of line is a comment, e.g.,

--this is a comment

Copyright 1997, KJH

Lexical Elements of VHDL

s Basic

Identifiers

Can Only Use

alphabetic letters ( A-Z, a-z ), or Decimal digits ( 0-9 ), or Underline character ( _ )

Must Start With Alphabetic Letter ( MyVal )

Copyright 1997, KJH

Lexical Elements of VHDL

s

Basic Identifiers
Not case sensitive ( LastValue = = lAsTvALue) May NOT end with underline ( MyVal_ ) May NOT contain sequential underlines (My__Val)

Not case sensitive, but recommended to use always the same way. It is also recommended to use capitals for language components
Copyright 1997, KJH

Lexical Elements of VHDL

s

Extended Identifiers
Any character(s) enclosed by \ \ Case IS significant in Extended Identifiers Extended identifiers are distinct from basic identifiers If \ is needed in extended identifier, use \\

Copyright 1997, KJH

Lexical Elements of VHDL

s Reserved s Special

Words

Do not use as identifiers

Symbols

Single characters

& ( ) * + , - . / : ; < = > |

Double characters (no intervening space)

=>

**

:=

/=

>=

<=

<>

Lexical Elements of VHDL

s Numbers

Underlines are NOT significant ( 10#8_192 ) Exponential notation allowed ( 46e5 , 98.6E+12 ) Integer Literals ( 12 )
Only positive numbers; negative numbers are preceded by unary negation operator No radix point
Copyright 1997, KJH

Lexical Elements of VHDL

Real Literals ( 23.1 )
Always include decimal point Radix point must be preceded and followed by at least one digit.

Radix ( radix # number expressed in radix)

Any radix from binary ( 2 ) to hexadecimal ( 16 ) Numbers in radices > 10 use letters a-f for 10-15.

Lexical Elements of VHDL

s Characters

Any printable character including space enclosed in single quotes ( x )

s Bit

Strings

B for binary ( b0100_1001 ) O for Octal ( o76443 ) X for hexadecimal ( xFFFE_F138 )

Characters, bits strings and strings are not the same thing!

VHDL Syntax
s Extended

Backus-Naur Form (EBNF)

Language divided into syntactic categories Each category has a rule describing how to build a rule of that category

Syntactic category <= pattern

<= is read as ...is defined to be...

Copyright 1997, KJH

VHDL Syntax
e.g.,

variable_assignment <= target :=

expression; Above, a clause of the category variable_assignment is defined to be a clause from the category target followed by the symbol := followed by a clause from the expression category followed by a terminating ;

VHDL Syntax
A preceding lexical element can be repeated an arbitrary number of times if ellipses are present, e.g.,
case-statement <= CASE expression IS case_statement_alternative { . . . } END CASE ;

repeated

Copyright 1997, KJH

VHDL Syntax
s OR

operator, | , in a list of alternatives,

e.g.,
mode <= IN | OUT | INOUT
s When

grouping is ambiguous, parenthesis are used, e.g.,

term <= factor { ( * | / | MOD | REM ) FACTOR }

Do not bother to remember operator precedence rules, just use parentheses

Copyright 1997, KJH

NEW EXAMPLE: 4-to-1 mux with 8 bit Datapaths

library ieee; use ieee.std_logic_1164.all; entity mux4to1_8 is port ( a,b,c,d : in std_logic_vector(7 downto 0); sel: in std_logic_vector (1 downto 0); a b dout: out std_logic_vector(7 downto 0) 8 ); end mux4to1_8; sel architecture whenelse of mux4to1_8 is begin dout <= b when (sel = "01") else 2 8 c when (sel = "10") else d when (sel = "11") else a; -- default We do not use with end process; end whenelse;

dout

Comments on Mux example

This is one way to write a mux, but is not the best way. The when-else structure here is actually a priority structure. A mux has no priority between inputs, just a simple selection. The synthesis tool has to work harder than necessary to understand that all possible choices for sel are specified and that no priority is necessary. Just want a simple selection mechanism. library ieee; use ieee.std_logic_1164.all; entity mux4to1_8 is port ( a,b,c,d : in std_logic_vector(7 downto 0); sel: in std_logic_vector (1 downto 0); dout: out std_logic_vector(7 downto 0) ); end mux4to1_8; architecture whenelse of mux4to1_8 is begin dout <= b when (sel = "01") else c when (sel = "10") else d when (sel = "11") else a; -- default end process; end whenelse;

repeated

A better way uses with

4-to-1 Mux using Select Concurrent Statement

architecture select_statement of mux4to1_8 is begin with sel select dout <= b when "01", c when "10", d when "11", a when others; end select_statement; Some synthesis tools will automatically recognize this structure (using with) as a mux They will find a more efficient implementation than using a when-else or if statement structure Remember in general that when-else and if structures define priority structures for compilation.

4-to-1 Mux using Select Concurrent Statement

architecture select_statement of mux4to1_8 is begin with sel select dout <= b when "01", c when "10", d when "11", a when others; continued end select_statement;

The others case must be specified. This is a concurrent statement, no process. The sequential version of the select statement is the case statement.

4-to-1 Mux using Case Sequential Statement

architecture select_statement of mux4to1_8 is begin process (a, b, c, d, sel) begin case sel is when "01" => dout <= b ; when "10" => dout <= c; when "11" => dout <= d; when others => dout <= a; end case; end process; end select_statement;

There can be multiple statements for each case; only one statement is needed for each case in this example. Uses process, it is sequential Concurrent => use select Sequential => use case

Pay attention to this arrow, how it is directed

Logical Shift Left by 1

library ieee; use ieee.std_logic_1164.all; entity lshift is port ( din : in std_logic_vector(7 downto 0); shift_en: in std_logic; dout: out std_logic_vector(7 downto 0) ); end lshift; architecture brute_force of lshift is begin process (din, shift_en) begin dout <= din; -- default case if (shift_en = '1') then dout(0) <= '0'; -- shift a zero into LSB dout (1) <= din(0); dout (2) <= din(1); dout (3) <= din(2); dout (4) <= din(3); dout (5) <= din(4); dout (6) <= din(5); dout (7) <= din(6); end if; end process; end brute_force; end lshift;

Din(7:0) Dout(7:0) 7 6 5 4 3 2 1 0

This is one way to do it; surely there is a better way?

Logical Shift Left by 1 (better way)

architecture better of lshift is begin process (din, shift_en) begin dout <= din; -- default case if (shift_en = '1') then dout(0) <= '0'; -- shift a zero into LSB dout (7 downto 1) <= din(6 downto 0); end if; end process; end better; end lshift;

This illustrates the assignment of a segment of one bus to another bus segment. The bus ranges on each side of the assignment statement must be the name number of bits (each 6 bits in this case).

4 Bit Ripple Carry Adder

A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0) Cout C(4) A
Co S B Ci

C(3)

A Co S

B Ci

C(2)

A Co S

B Ci

C(1)

A Co S

B Ci

C(0)

Cin

Sum(3)

Sum(2)

Sum(1)

Sum(0)

Want to write a VHDL model for a 4 bit ripple carry adder. Logic equation for each full adder is: sum <= a xor b xor ci; co <= (a and b) or (ci and (a or b));

4 Bit Ripple Carry Model

library ieee; use ieee.std_logic_1164.all; entity adder4bit is port ( a,b: in std_logic_vector(3 downto 0); cin : in std_logic; cout: out std_logic; sum: out std_logic_vector(3 downto 0) ); end adder4bit; architecture bruteforce of adder4bit is -- temporary signals for internal carries signal c : std_logic_vector(4 downto 0); . begin process (a, b, cin, c) begin c(0) <= cin; -- full adder 0 sum(0) <= a(0) xor b(0) xor c(0); c(1) <= (a(0) and b(0)) or (c(0) and (a(0) or b(0))); -- full adder 1 sum(1) <= a(1) xor b(1) xor c(1); c(2) <= (a(1) and b(1)) or (c(1) and (a(1) or b(1))); -- full adder 2 sum(2) <= a(2) xor b(2) xor c(2); c(3) <= (a(2) and b(2)) or (c(2) and (a(2) or b(2))); -- full adder 3 sum(3) <= a(3) xor b(3) xor c(3); c(4) <= (a(3) and b(3)) or (c(3) and (a(3) or b(3))); cout <= c(4); end process; end bruteforce;

Straight forward implementation. Nothing wrong with this. However, is there an easier way?
Not very elegant for long words, not scalable

4 Bit Ripple Carry Model using For Statement

architecture forloop of adder4bit is signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries. begin process (a, b, cin, c) Index i is not a signal , not a begin variable. c(0) <= cin; for i in 0 to 3 loop -- all four full adders sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); end process; end forloop;

Comments on for-loop statement

To visualize what logic is created, 'unroll' the loop by writing down each loop iteration with loop indices replaced hard numbers.
architecture forloop of adder4bit is signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries. begin The for-loop can be used to repeat blocks of logic process (a, b, cin, c) begin The loop variable i is implicity declared for this loop; does not have to c(0) <= cin; be declared anywhere else. for i in 0 to 3 loop -- all four full adders sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); end process; end forloop;

VHDL-II Structural Modeling

Variables
s Variables

Exist Only Within an Architecture

Values of variables cannot be passed to other entities except through signals

s Variables

Change Value When They Are Evaluated.

Signals change at a later time

Signals
s

Entities are Interconnected by Signals

Process executions result in new values being assigned to signals which are then accessible to other processes A signal may be accessed by a process in another architecture by connecting the signal to ports in the entities associated with the two architectures

Signals
Signals Can Be Declared Internal to an Architecture to Connect Internal Entities s Variables Are Not Appropriate Since They Do Not Have the Temporal Characteristics of Hardware s Signals Declared Within an Entity Are Not Available to Other Entities Unless Specified in the Port Clause of the Entity Declaration.
s

Entity Syntax
ENTITY identifier IS [ PORT ( port_interface_list ); ] { entity_declarative_item } END [ ENTITY ] [ identifier ] ;

Entity Syntax
port_interface_list <= ( identifier { , . . . } : [ mode ] subtype_indication [ := expression ] ) { ; . . . } mode <= IN | OUT | INOUT

Entity Example
ENTITY NiCadCharger IS
mode

PORT ( Voltage, Current : IN AC : IN REAL := 0.0 ; BIT := 1 ; );

Charged, Recharge: OUT BIT END ENTITY NiCadCharger ;

Architecture Syntax
ARCHITECTURE identifier OF entity_name IS { block_declarative_item } BEGIN { concurrent_statement } END [ARCHITECTURE][ identifier ];

Structural Model
sA

Representation of a System in Terms of the Interconnections of a Set of Defined Components.

Components can be described either structurally or behaviorally Smallest components are behavioral entities Components usually stored in libraries

Structural Models
s Components

Can Be Instantiated As Concurrent Statements in Architectures

If architecture not specified in statement
Must be specified later, or Most recently analyzed architecture used

Ports can be specified two ways

Positional association Named association

Internal Signals in a Structural Model

s Entity

Ports Which are Declared within an Architecture Body Are Local Signals
These signals are not available outside the architecture unless connected to one of the architectures ports

Odd Parity Generator Example

ENTITY Odd_Parity IS PORT( Out_1

Parity Entity

IN_1, IN_2, IN_3 : IN BIT ; : OUT BIT ); END ENTITY Odd_Parity ;

Odd Parity Behavior Architecture

ARCHITECTURE Odd_Parity_B OF Odd_Parity IS BEGIN Out_1 <= ( IN_1 AND NOT IN_2 AND IN_3 ) OR ( NOT IN_1 AND NOT IN_2 AND NOT IN_3 ) OR ( NOT IN_1 AND IN_2 AND IN_3 ) OR ( IN_1 AND IN_2 AND NOT IN_3 ) END ARCHITECTURE Odd_Parity_B ;

fodd ( A, B, C) = AB C + AB C + AB C + AB C

INVERTER Entity and Architecture

ENTITY INV IS PORT( In_1 : IN BIT ; In_1_Bar : OUT BIT ); END ENTITY INV ; ARCHITECTURE INV_B OF INV IS BEGIN In_1_Bar <= NOT IN_1 ; END ARCHITECTURE INV_B ;

AND_3 Entity/Architecture
ENTITY AND_3 IS PORT( IN_1, IN_2, IN_3 : IN BIT ; Out_1 : OUT BIT ); END ENTITY AND_3 ; ARCHITECTURE AND_3_B OF AND_3 IS BEGIN Out_1 <= IN_1 AND IN_2 AND IN_3 ; END ARCHITECTURE AND_3_B ;

OR_4 Entity/Architecture
ENTITY OR_4 IS PORT( IN_1, IN_2, IN_3, IN_4 : IN BIT ; Out_1 : OUT BIT ); END ENTITY OR_4 ; ARCHITECTURE OR_4_B OF OR_4 IS BEGIN Out_1 <= IN_1 OR IN_2 OR IN_3 OR IN_4 ; END ARCHITECTURE OR_4_B ;

Odd Parity Structural Architecture

ARCHITECTURE Odd_Parity_S OF Odd_Parity IS --block_declarative_items --components COMPONENT INV IS PORT( In_1 : IN BIT ; In_1_Bar : OUT BIT ); END COMPONENT INV ;

Odd Parity Structural Architecture

COMPONENT AND_3 IS PORT( IN_1, IN_2, IN_3 : IN BIT ; Out_1 : OUT BIT ); END COMPONENT AND_3 ; COMPONENT OR_4 IS PORT( IN_1, IN_2, IN_3, IN_4 : IN BIT ; Out_1 : OUT BIT ); END COMPONENT OR_4 ;

Structural Mapping
For single-output gates the name of the signal is the same as the name of the gate

MT_5 in_1 in_2 in_3 inv_1 inv_2 MT_3 inv_3 MT_6 MT_0

These names are necessary to connect components

Out_1

Odd Parity Structural Architecture

--block_declarative_items --internal signals SIGNAL MT_0, MT_3, MT_5, MT_6 : BIT ; SIGNAL INV_1, INV_2, INV_3 : BIT ; BEGIN --parity structural architecture --connect gates G1: INV PORT MAP ( In_1, INV_1 ); G2: INV PORT MAP ( In_2, INV_2 ); G3: INV PORT MAP ( In_3, INV_3 );

Odd Parity Structural Architecture

G4: AND_3 PORT MAP ( IN_1, INV_2, IN_3, MT_5 ); G5: AND_3 PORT MAP ( INV_1, INV_2, INV_3, MT_0 ); G6: AND_3 PORT MAP ( INV_1, IN_2, IN_3, MT_3 ); G7: AND_3 PORT MAP ( IN_1, IN_2, INV_3, MT_6 );

Odd Parity Structural Architecture

G8: OR_4 PORT MAP ( MT_0, MT_3, MT_5, MT_6, Out_1 ); END ARCHITECTURE Odd_Parity_S ;