CMOS Technology Overview

1
Overview of CMOS Technology
1.1 I ntroduction
Complementary metal-oxide-semiconductor (CMOS) technology has been the most important driving force for the evolution of almost all kinds of technology in the last five decades [1, 2]. It has revolutionized the way we live and has expanded our productivities and capabilities. For example, computers and the Internet, mobile phones and PDAs, video game and multimedia players, and digital and video cameras, using CMOS chips as the core components, have become indispensable devices for our daily lives and improve the productivities of many disciplines. The CMOS technology has now evolved into two extremes: the gigascale in terms of integration level and the nanoscale in terms of device feature sizes. The history of this technology development has followed a simple but amazing patternscaling, which involves downsizing in device size and upscaling in chip densityand has achieved the legend of smaller-larger-faster-cheaper in the exponential rate, or Moores law, for over five decades. This legend will continue for at least another decade, though we are now facing a lot of critical challenges [2]. The density of the microprocessor chip has been quadrupled every three years while the minimum transistor feature was reduced to some thousandth in the past five decades. This exponential trend was first predicted by Gordon Moore in 1965 and is now known as Moores law [3]. Figure1.1 depicts the integration density of different generations of Intel microprocessors [4]. It follows closely with the trend as predicted by Moore. Intel fabricated in 1971 its first 4-bit 750 kHz MOS transistor-based single-chip microprocessor (MPU), Intel 4004, and thus started the microprocessor revolution and the MOS technology evolution. At that time, the typical MOS transistor channel length was about 10 m and the number of transistors or chip density was 2250. Seven years later, the density of an 8-bit 8086 microprocessor reached 29,000. In the next four years, the chip density was further raised by more than four times, to 120,000, in the 16-bit 80286 microprocessor, which was used as the core of the widely used personal microcomputer at that time. The downsizing of the MOS transistor led to the decrease in capacitance and power consumption and to the increase in the circuit operating speed. Meanwhile, the 1
Nano-CMOS Gate Dielectric Engineering
1010 109 108 Number of Transistors 107 106 386 105 8086 104 8080 286
Itanium Poulson Itanium 2 Dual Xeon Quad Itanium 2 P IV Pentium Pro Pentium 486 P II P III Multi-core i7 Quad
Core 2 Dual
4004 103 1970 1975
1980
1985
1990
1995
2000
2005
2010
2015
Year FIGURE 1.1 Upscaling of integration density in Intel microprocessor chips. (Data taken from http://www. intel.com/technology/timeline.pdf and R. J. Riedlinger, R. Bhatia, L. Biro, B. Bowhill, E. Fetzer, P. Gronowski, and T. Grutkowski, A 32 nm 3.1 billion transistor 12-wide-issue itanium processor for mission critical servers, Technical Digest of 2011 IEEE International Solid-State Circuits Conference, San Francisco, Feb. 2011 IEEE.)
transistor size was reduced so that the same area could accommodate more components and thus more functions. With the parallel operation capability, the computation speed was enhanced further. This has been the major development of MPU in the last decade. The latest version of Intel Itanium series processor has 3.1 billion transistors squeezed onto a single chip with a size of 18.2 29.9 mm2 and the transistor gate length is now reduced to 32 nm [5], a factor of 0.0032 of those used in the first MPU. There is no doubt that the downsizing of the MOS transistor is approaching its ultimate device or technology limits [1]. When the transistor is being scaled into the nanoscale range, there are a lot of serve challenges in the device physics, material selections, and fabrication processes [1, 2]. New device structures, new materials, and new technologies are required for further downscaling the device to the limits. Table1.1 lists the major device geometric parameters for some future technology nodes, which are calculated based on the good technology rules [6, 7]. Particularly for the gate dielectric film, the thickness is now in the atomic scale. For example, we require a
TABLE1.1 Key Geometric Parameters for Some Future Technology Nodes Estimated Using the Good Technology Rule
Gate Length (nm) Dielectric thickness (nm) Junction depth (nm) Channel depletion thickness (nm) 22 0.8 11.0 11.0 16 0.6 8.0 8.0 11 0.4 5.5 5.5 8 0.3 4.0 4.0
gate dielectric film that is equivalent to two-monolayer-thick (~0.7 nm) silicon dioxide for the 22 nm and 16 nm technology nodes. That is well below the direct tunneling limit (see Section 1.3.5) and would result in an unacceptable large leakage current. This thickness is also impossible for fabrication process control [2]. Searching for a suitable gate dielectric film has been one of the most critical and challenging issues in the state-of-the-art CMOS technology. It is the objective of this book to have a comprehensive study on every aspect of the gate dielectric engineering for nanoscale CMOS devices. The terminologies, the basic physics of MOS devices, the trends, and the limitations of CMOS technology will be highlighted in this chapter. It provides a quick reference for the basic knowledge to be used or to be discussed in this book. In Section 1.2, the operation of a MOS transistor and the classical models will be reviewed briefly. Section 1.3 focuses on the issues related to the short-channel MOS transistors. Section 1.4 highlights the advantages and uniqueness of CMOS technology for digital applications. In Section 1.5, the physics of a MOS transistor operated in the deca- nanometer range will be introduced. In Section 1.6, the technology trends and the possible technological options for future CMOS device fabrication will be discussed. It highlights the possible solutions for conquering the physical and technology constraints in four areas: device structures, channel engineering, source-drain engineering, and gate stack engineering. Scenarios of More Than Moore will also be discussed in this section. Finally, in Section 1.7, a summary and an outlook for the technological options beyond CMOS will be given.
1.2 MOS Transistor: A Quick Introduction to Classical Models

1.2.1 Current-Voltage Characteristics The first insulating gate field-effect transistor (IGFET)which is now known as the metal-oxide-semiconductor field-effect transistor (MOSFET), or simply MOS transistorwas fabricated by Kahng and Atalla in 1960 [8]. This basic idea can even be dated back to the pre-semiconductor era when
LG Gate Source Drain VGS VDS IDS W n+ L n+
p-substrate FIGURE 1.2 Illustration of the structure and variables of an n-channel MOS transistor. Note that the physical channel length (L) is smaller than the gate length (LG) because of the side diffusion of source and drain junctions.
Lilienfeld proposed a metal-insulator-metal (MIM) structure for charge transport control in 1924 [9]. A MOS transistor consists of a source, a drain, and a gate electrode separated from the silicon substrate by gate oxide. The current flow between the source and the drain is controlled by altering the gate and drain voltages. Taking an n-channel MOS (nMOS in short) transistor as an example, it consists of two heavily doped n+ regions (drain and source) on a p-type silicon substrate (see Figure1.2). When a positive voltage is applied to the gate, an inversion layer under the oxide, known as the channel, is formed between the source and the drain. There are two fundamental physical processes, field effect and drift, governing the device operation. When a voltage, VGS, is applied to the isolated gate terminal, ideally there is no current flowthat is, the IGS-VGS relationship is not governed by ohmic law. The voltage is translated into an electric field Eox = VGS/tox across the oxide layer (here tox is the oxide thickness). Under the oxide, charges are induced on the silicon surface by the gate electric field according to the Gauss law, that is, Q = 0 oxE (1.1)
where 0 is the vacuum permittivity and ox is the dielectric constant of the gate oxide. That is why this kind of transistor is called a field-effect transistor. By considering the voltage required for Fermi level alignment between the gate electrode and silicon substrate, for compensating the oxide charge and the depletion charge in silicon, the effective electric field developed on the
silicon surface to produce a strong inversion channel under the oxide layer can be approximated by E = VGS VT tox (1.2)
where VT is the threshold voltage of the transistor (see Section 1.2.2 for details). Thus the charge density in the strong inversion channel is Q = 0 ox VGS VT = COX (VGS VT ) tox (1.3)
Equation (1.3) contains the two most important parameters for MOS devices operation: the oxide dielectric constant ox governs the field effect effectiveness and tox governs the field strength. They are always lumped together to form a new term: COX, the oxide capacitance per unit area. The induced charges can transport along the channel under the lateral electric field (E//) induced by the drain-to-source bias (VDS) according to the following drift equation: J DS = qn E// (1.4)
where q is the electronic charge, is the channel electron mobility, and n is the density of free electrons in the channel. The drain current can be calculated by double integrating Equation (1.4) along the depth and width directions and the first order approximation of the lateral field is VDS/L (here L is channel length of the MOS channel; see Figure1.2). Due to the presence of the lateral field, the inversion charge density is not a constant along the channel; the charge density can be approximated by
L
n=
1 L
C
0
OX
[(VGS VT ) vs ] dy
(1.5)
Assuming the channel mobility is constant and the electric field and then the charge density change gradually along the channel, which is known as the gradual channel approximation, it can be readily shown that the drain current can be approximated by I DS = COXW L
2 1 VDS (VGS VT ) VDS 2
(1.6)
where W is the channel width.
40 L = 0.18 m 30 Drain Current (mA) Linear Region VDS = VGS VT Saturation Region VDS = 1.50 V 1.35 V 1.20 V 1.05 V 10 0.90 V 0.85 V 0 0.80 V 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
20
Drain Voltage (V) FIGURE 1.3 Typical current-voltage characteristics of an n-channel MOS transistor.
Equation (1.6) is the well-known Pao-Sah equation in the linear or ohmic region [10]. This relation holds up to VDS VGS V T. For VDS > VGS V T , all the inversion charge induced by the vertical field will be completely vacated or pinched off by the lateral field. The drain current reaches its maximum value and does not increase further with bigger drain bias. The I-V characteristic in this saturation region is given by I DS = COXW (VGS VT )2 2L (1.7)
for VGS > V T and VDS VGS V T . Figure1.3 depicts the current-voltage (I-V) characteristics of a typical MOS transistor at different gate-to-source voltages showing the pinch-off voltages (dashed curve), linear region, and saturation region. 1.2.2 Threshold Voltage The aforementioned threshold voltage (V T) is governed by several factors. When the metal gate electrode is brought to proximity contact with the substrate silicon, the Fermi levels of the two sides adjust themselves to become equal. This equalization process leads to the formation of a space charge layer and band bending on the silicon surface (see Figure1.4). If oxide charges exist, a potential drop across the oxide also exists. The potential difference between the metal and silicon becomes
Vacuum q S EC EI EF EV EF Inversion Region Metal Charge QD Qinv WD y Silicon
S = q(2F )
qF
FIGURE 1.4 (Top) Energy band diagram showing the surface of a p-type semiconductor at strong inversion (S = 2F) of a MOS structure; (bottom) approximation of inversion charge (Qinv), depletion charge (QD), and depletion layer width (WD) of an nMOS under strong inversion condition.
VFB = MS
Eg QOX Q = M S + + F OX COX 2q COX
(1.8)
Equation (1.8) is also the value of the gate voltage required to maintain the surface charge density at the same level as that of the bulk or to keep the energy band of the silicon surface flat. It is known as the flat-band voltage. The Fermi level of the p-type silicon substrate is governed by the acceptor concentration of NA and is given by F =
kT q
A ln N ni
(1.9)
where KT/q is the thermal voltage and ni is the carrier density of intrinsic silicon.
At strong inversion, that is, the surface potential S = 2F, the holes are completely depleted and the depletion charge can be approximated by QD = 2 0Si qN A (2 F ) (1.10)
Thus, the overall gate voltage required to drive the silicon surface into strong inversion is given by or VT = VFB + 2 F + 2 0Si qN A COX 2 F (1.12) VT = VFB + 2 F + QD / COX (1.11)
Figure 1.5 plots the drain current as a function of gate voltage at VDS = 0.05 V. At small VGS (VGS < V T), IDS is very small as the channel is in weak inversion or in accumulation. IDS increases remarkably when VGS > V T . Here the threshold voltage is defined by the x-intercept of the extrapolated ohmic curve. Different definitions and extraction methods were used for short-channel transistors [11]. Note that the threshold voltage or the turn-on voltage is also affected by the drain voltage because of the charge sharing in
4 L = 0.18 m 3 Drain Current (mA) VDS = 0.05 V
VT
0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Gate Voltage (V) FIGURE 1.5 Typical IDS-VGS plot showing the threshold voltage (V T) determined by extrapolation of ohmic curve for an n-channel MOS transistor.
the drain junction as well as the drain-induced barrier lowering effect (see Section 1.3.5).
1.3 Short-Channel Effects and Short-Channel Modifications

The actual current-voltage characteristics of MOS transistors, particularly for deep submicron and nanometer channel length devices, are very complicated and the characteristics deviated greatly from those given in Equations (1.6) and (1.7). Many revised models were developed based on a large number of empirical parameters and some nonlinear functions [12, 13]. Those modifications mainly involved the more precise considerations of some nonideal or secondary effects, such as charge sharing, velocity saturation, field dependent carrier velocity, channel length modulation, and so on. Determination of these model parameters requires sophisticated measurements and parameter extraction processes. Yet the most inaccurate treatment in Section 1.2 is the assumption of constant channel mobility and neglecting the channel length modulation effect. The channel mobility of a MOS transistor is significantly different from the bulk mobility of the substrate silicon because the channel region suffers seriously from the surface roughness scattering and Coulomb scattering of depletion charge and interface traps. The channel mobility is a strong function of electric field [14]. Figure1.6 plots the channel mobility as a function of electric field for different channel doping concentrations [14]. The low-field mobility is mainly governed by the Coulomb scattering where the high-field mobility is limited by the surface roughness scattering in the silicon channel. In addition, the channel mobility is degraded due to the velocity saturation effect in the high-field region near the drain. Many models were developed to deal with the channel mobility. To consider these effects, Equation (1.13) shows a simple empirical model by considering the velocity saturation effect at high field [15]:
S
(1 + VDS/Esat L ) (1 + (VGS VT ))
(1.13)
where Esat is the electric field for velocity saturation, 0 is the low-field mobility, and is the mobility modification constant. Section 1.3.1 presents a simple revised I-V model by taking these effects into account. In addition to the I-V characteristics, the reduction of channel length leads to several undesirable performance degradations, which are known as short-channel effects (SCE). These effects include threshold voltage roll-off because of the charge sharing in the channel [16], drain-induced
10
104
2 Ee
Mobility e [cm2/Vsec]
77 K
NA [cm3] 3.9 1015 2.0 1016 7.2 1016 3.0 1017 7.7 1017 2.4 1018
103
0.3 Ee
300 K (100) Electron 102 0.1 Eective Field [MV/cm] 1.0
FIGURE 1.6 Universal inversion layer mobility as a function of effective electric field and substrate impurity concentration. (From S. Takagi, M. Iwase, and A. Toriumi, On the universality of inversionlayer mobility in Si MOSFETs: Part I. Effects of substrate impurity concentration, IEEE Trans. Electron Devices, 41 (1994) 23572362. IEEE. With permission.)
barrier lowering (DIBL) as a result of capacitive coupling between source and drain, and source-to-drain punchthrough. For ultrathin gate dielectric, the gate leakage current is significantly enhanced because of the direct tunneling [1719], FowlerNordheim (FN) tunneling [2022], or trap-assisted tunneling through the gate dielectric [20, 2325]. This section reviews these effects briefly. 1.3.1 Effect on I-V Characteristics The velocity saturation effect makes the channel pinch-off occur earlier and the drain saturation current smaller. Another factor that affects greatly the I-V characteristics is the drain-induced effective channel length shortening or channel modulation effect. The depletion width in the drain end increases with the drain bias and that makes the effective channel shorter. As a result, a larger drain bias will lead to a larger value of drain saturation current. In the I-V characteristics, a finite resistance is observed. This phenomenon is particularly obvious in a short channel device. Empirically, the saturation characteristic is modeled by I DS, sat = COXW (VGS VT )2 (1 + VDS ) 2L (1.14)
11
where is an empirical parameter. To maintain the continuity, the ohmic region I-V characteristic is also modified accordingly as I DS = COXW L
2 1 VDS (VGS VT ) VDS 2 (1 + VDS )
(1.15)
This simple treatment is not good enough for device modeling and characterization as the value depends on some other device parameters including the channel length and biases. A simple model that includes the mobility and channel length modulation was developed [26]: I DS = I DS 1 + 2(VGS VT )/Esat L F 2 1+ L 1 + ( ) / V V E L ( GS T sat )
D + VDS VDsat D
(1.16)
where D and are empirical parameters. VDsat is the saturation drain voltage and is given by [15] VDsat = VGS VT 1 + (VGS VT ) / Esat L (1.17)
and F is given by F= 2 Si 0 (2B + VDS ) 2 + ( + 2 / Esat L)( (VGS VT ) LCOX (VGS VT ) ( 1 + (VGS VT )) ( 1 + 2(VGS VT )/ Esat L ) 1 + 1 + VDS / Esat L
(1.18)
Figure1.7 shows the comparison of the experimental results and the data calculated from model fitting using Equation (1.16) for an nMOS transistor with physical gate length of 0.44 m. The transistor had not been well tempered and the drain saturation current increases obviously with the drain bias. However, good correlation in the linear, saturation, and near pinch regions was still obtained with the model given in Equation (1.16). 1.3.2 Subthreshold Conduction Before the strong inversion, that is, VGS < V T, the surface region is in fact a bipolar transistor (see Figure 1.8). If the base width (channel length) is short enough and the drain voltage is large enough, the bipolar transistor can be turned on and there is a current flow, though maybe quite small,
12
8 7 6 Drain Current (mA) 5 4 3 2 1 0
0.5
1.5
2 2.5 3 Drain Voltage (V)
3.5
4.5
FIGURE 1.7 Comparison of experimental I-V characteristics with a simple model by taking the short- channel effects into account. (Reprinted from H. Wong, A new approach to current-voltage characteristics formulation for short-channel MOSFETs, IEEE Trans. Electron Devices, ED-41 (1994) 24802482. IEEE. With permission.)
Barrier Source
Channel
Energy
qVDS (Base) Drain EC EV Channel Length Direction
FIGURE 1.8 Energy band diagram showing an energy barrier near the source end which governs the carrier diffusion in subthreshold conduction.
13
between the source and the drain. This current is called the subthreshold current. The theoretical modeling of this current was based on the framework of the collector current of a bipolar transistor and the subthreshold current of an nMOS is given by [27] I DS = W L Si q N A 4 B
2 Vth exp
(VGS VT )
m Vth
1 exp
VDS Vth
(1.19)
where B is the bulk potential and m is the body factor given by m= 1+ Si q N A 1 C + Cit = 1+ D 4 B Cox Cox (1.20)
where CD and Cit are the capacitance due to the channel depletion charges and the interface oxide charges, respectively. The subthreshold conduction behavior is often characterized with the subthreshold slope, S, which is defined as S= d ( log I DS ) d VGS
1
= 2.3 m
kT (in mV/dec) q
(1.21)
According to Equation (1.20), when the depletion capacitance is much smaller than the oxide capacitance, indicating the surface potential is mainly governed by the gate voltage, m = 1, and S 60 mV/dec at room temperature, which is the theoretical limit. A typical S value is about 100 mV/dec because of the presence of depletion and interface charges. Figure1.9 depicts a typical log IDS versus VGS plot for an nMOS transistor. The subthreshold slopes are 100 and 110 mV/dec, respectively, for 0.05 V and 1.2 V drain bias. This plot also shows the ON current, ION, and the OFF current, IOFF . The flat region at large gate voltage represents the saturation current and is often called the ON current, whereas at VGS = 0 the transistor is turned off but a very low current, which is termed IOFF, may still be detectable. A good MOS transistor should have as large a subthreshold swing (large ION and small IOFF) as possible. 1.3.3 Short-Channel Effects Many characteristics of short-channel (e.g., L < 1 m) devices are often different from those of the long ones due to the more significant effects of the two-dimensional charge distribution, the depletion layer, and some high electric fields in the transistor. In fact, short-channel effects do not necessarily depend on the absolute length of the channel. Short-channel effects may
14
101 100 101 Drain Current (mA) 102 103 104 105 106 107 0.0 IOFF 0.2 0.4 0.6 0.8 Gate-to-Source Voltage (V) 1.0 1.2 DIBL S = 77 mV/dec exp q(VGS VT) mkT VDS = 0.05 V ION (VGS VT)2 VDS = 1.2 V
FIGURE 1.9 Typical subthreshold characteristics of an nMOS transistor showing the ON current (ION), OFF current (IOFF), subthreshold slope (S), and drain-induced barrier lowering (DIBL).
still be absent in a properly scaled short-channel transistor. It depends on how the electric fields and depletion charges are distributed in the transistor. Based on some theoretical derivations, an electrostatic scale length LE was defined in terms of thickness of gate dielectric and channel thickness [28]: 0 = Si tan tox tSi + ox tan LE LE (1.22)
This parameter characterizes the quality of a transistor. It in fact defines a parameter LE, whose value must be much larger than both the oxide thickness (tox) and the channel thickness (tSi ). Thus, if the channel length is larger than LE (or much larger than tox and tSi ), then the transistor should behave with the absence of the short-channel effects. Similarly, for double-gate MOSFETs, the electrostatic scale length can be calculated from [28] 1= Si tox tan ox LE tan tSi 2 LE (1.23)
A similar but much simpler parameter dealing with the short-channel effects is the electrostatic integrity (EI), which is defined as [6, 7]
15
EI 1 +
x2 tox Tdepl j 2 L L L
(1.24)
where xj is the junction extension depth and Tdepl denotes the depletion depth in the channel. In Equation (1.24), the EI value is always greater than unity. A good transistor should have an EI value as close to unity as possible. The relationship defined in Equation (1.24) clearly provides the general guideline for designing a transistor with minimum short-channel effects: keep the junction depth, gate oxide thickness, and channel depletion depth much smaller than the channel length of the transistor. According to this rule, the preferred parameter values for some future technology nodes are listed in Table1.1. 1.3.3 Threshold Voltage Roll-Off Before turning the channel into the strong inversion, the gate voltage needs to compensate for the depletion charges in the channel region. This voltage is the major constitution of the threshold voltage given in Equation (1.12). However, a small portion of the depletion charges near the source and drain region is actually induced by the source and drain junctions (see Figure1.10). That is, the threshold voltage should be smaller. This effect is negligible in long channel transistors when compared with the total depletion charges. It becomes more significant in short-channel devices (see Figure 1.10[b]) and causes the threshold voltage to roll off as shown in Figure 1.11. The threshold voltage roll-off may be alleviated by using thinner junction (xj) and depletion depth (Tdepl) (see Figure1.10 [c]). Empirically, the threshold voltage roll-off can by approximated by [6, 7] VT = 0.64 Si D EI ox (1.25)
where D is the source-to-channel junction built-in voltage. That is, the threshold voltage roll-off can be reduced by achieving a smaller EI value in the device structure design. 1.3.4 Drain-Induced Barrier Lowering (DIBL) In the weak inversion region, there is a potential barrier between the source and the channel region (see Figure1.8). This barrier is important for keeping the transistor in the OFF mode. In a long-channel transistor, the barrier height is essentially governed by the gate-to-source voltage. In a short-channel transistor, the barrier width is small. When a large drain bias is applied, the band edge of the barrier near the drain side is pulled downward and the electrons
16
n+ Gate-induced space charge layer (a) Junction space charge layer
n+
p-substrate
n+
n+
n+
n+
p-substrate (b)
p-substrate (c)
FIGURE 1.10 The charge sharing between the gate-induced space charge layer and junction space charge layers causes a smaller threshold voltage: (a) the charge sharing effect is negligible in longchannel transistor; (b) the charge sharing effect is significant in short-channel transistor; (c) the charge sharing effect may still be negligible in a properly scaled short-channel transistor by using better technology rules. 0.90 0.85 Threshold Voltage (V) 0.80 0.75 0.70 0.65 0.60
Gate Length (m) FIGURE 1.11 By using the gate oxide thickness, junction depth, and channel depletion depth, the threshold voltage of a MOS transistor rolls off as the channel length becomes shorter.
17
50 40 DIBL (mV/V) 30 20 10 0
0.0
0.5
1.0 Gate Length (m)
1.5
2.0
FIGURE 1.12 The drain bias can result in a significant decrease in the threshold voltage of a short-channel transistor.
from the source can surmount the barrier; this leads to a larger drain current, which in effect lowers the threshold voltage. That is, the threshold voltage of a short-channel transistor can be a function of the drain bias. This effect is known as drain-induced barrier lowering (DIBL). An empirical parameter, DIBL is defined as the ratio of the difference in threshold voltage measured at a small and a nominal value VDS to the drain voltage difference, that is, DIBL = VT (in mV/V) VDS (1.26)
In a short-channel device, the DIBL value increases significantly (see Figure1.12). Empirically, DIBL may be estimated by [6, 7] DIBL = 0.8 Si VDS EI ox (1.27)
1.3.5 Gate Leakage Current As mentioned in Section 1.1, to maintain good control of the nanoscale MOS devices, the gate oxide thickness needs to be scaled down accordingly. The oxide equivalent thickness (EOT; see Section 1.6.2) is now below a nanometer. The gate leakage current has been the major concern and that is one of the major reasons for using physically thicker high dielectric constant materials.
18
JFN JPF JTrap JDT EC
EV EF JFN: Fowler-Nordheim tunneling JPF: Poole-Frankel tunneling Metal Oxide Silicon JDT: Direct tunneling JFN: Trap-assisted tunneling
FIGURE 1.13 Energy band diagram of an nMOS structure showing the major tunneling mechanisms giving rise to the gate leakage.
For silicon dioxide thinner than 3 nm, direct tunneling (DT) of the charge carriers from the silicon conduction band or valance band to the gate electrode can take place (see Figure1.13). By using a thicker high-k material, the DT current may be minimized but other charge transport mechanisms may still be significant because of the smaller barrier at the Si/dielectric interface and high trap density in the dielectric film. This section reviews the major current conduction mechanisms that have been reported for the MOS gate dielectric films. 1.3.5.1 Direct Tunneling If the dielectric layer is thin enough, direct tunneling of the carrier from the silicon to the gate electrode may take place (see Figure1.13). The analytical expression for the direct tunneling current can be obtained with the wellknown Wentzel-Kramers-Brillouin (WKB) approximation of barrier transparency [17]. A better version of the approximation is given by [18] J DT = J 0 1
3/2 Vox 4 2 m * q tox B V exp 1 1 ox B B 3 Vox 3/2
(1.28)
19
106 105 104

Gate Current Density (A/cm2)
nFET
Measurement Simulation
10
103 102 101 100 101 102 103 104 105 106 107 108 0.0 0.5 1.0 1.5
15 20 21.9 25.6 29.1 32.2 35.0 36.1 2.0 2.5 3.0
Gate Voltage (V)
FIGURE 1.14 Typical leakage current characteristics of a MOS capacitor illustrating different current conduction mechanisms. (Reprinted from S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wong, IEEE Electron Device Lett., 18 (1997) 209211 IEEC.)
where J0 is a constant, is the reduced Planck constant, Vox is the voltage drop across the dielectric, m* is the electron effective mass in the dielectric, and B is the potential barrier for the direct tunneling. As shown in Equation (1.28), the tunneling current is an exponent function of the films thickness. The tunneling current increases rapidly as the film becomes thinner. Figure1.14 shows the example of direct tunneling current of silicon oxide films with different thicknesses. The current levels are quite large. For 1.5 nm thick oxide film, the leakage current reaches 100 A/cm2 at 1.5 V gate bias [29]. 1.3.5.2 FowlerNordheim Tunneling Even in a thicker gate dielectric, if the applied bias between the silicon substrate and the gate is large enough, the band bending of the dielectric film becomes larger and tunneling through the triangle band edge (see Figure1.13) will occur. This mechanism is known as FowlerNordheim (FN) tunneling [20, 21] and the tunneling current can be calculated with J FN = AE 2 exp(/E) (1.29)
where E is the externally applied field.
20
The pre-exponent A and slope in Equation (1.29) are given, respectively, by A= q3 m0 16 2 B mox
1/2
(in A/V 2)
(1.30)
/2 4 3 2 mox B = m0 3 q
(in V/cm)
where m0 and mox are the electron mass in free space and in the oxide, respectively. 1.3.5.3 PooleFrenkel Emission and Trap-Assisted Tunneling Trap-assisted tunneling is also the main current leakage mechanism in dielectric films with high amount of dielectric traps such as silicon nitride and high-k metal oxides [2, 25]. The trapped charges can be ionized and reemitted into the dielectric conduction band. Depending on the electric field and temperature, the trap-assisted tunneling may involve (1) pure tunneling at low temperatures and high fields, (2) thermally assisted tunneling at medium temperatures, and (3) Frenkel emission at low fields (see Figure1.15). In the classical PooleFrenkel model [23, 24], the trapped electron
Energy qFr
r Frenkel Emission Wt Thermally-Assisted Tunneling Tunneling FIGURE 1.15 Mechanisms involving the PooleFrenkel conduction of different types: (1) pure tunneling at low temperatures and high fields, (2) thermally assisted tunneling at medium temperatures, and (3) Frenkel emission at low fields.
21
can emit into the conduction band at high temperatures and at low electric fields. The trap ionization probability, P, is given by PFP = exp Wt F kT (1.31)
where Wt is the trap energy, = q 3 / 0 is the Frenkel constant, and is the attempt-to-escape factor. At high electric fields and at low temperatures, thermally assisted tunneling (TAT) occurs; the trap ionization probability can be modified as [25] = kT
Wt F
PTAT
E 2 dE exp kT
x2
x1
dx
2 m* ( qV ( x ) E )
(1.32)
where V ( x ) = Wt q Fx 4 0 x
Here, E is the excited energy level. The integral boundaries x1 and x2 are classical turning points and are given by [25] x1,2 1 Wt E qF 1 1 = 2 2 qF 0 (Wt E )
1/2
(1.33)
The last case of trap-assisted conduction involves the multiphonon emission [30]. The rate of trap ionization can be approximated by [25, 30] P=
n=
exp
nWph Wph S Pi (WT + nWph ) (1.34) S coth In 2 kT 2 kT sinh(Wph /2 kT )
where Wph = is the phonon energy, Wt the thermal energy, and Wopt the optical ionization energy; S = (Wopt WT)/Wph and In is the modified Bessel function. The tunnel escape rate through the triangular barrier is given by Pi (W ) = qF 4 2 m 3/2 exp W 3 qF 2 2m * W (1.35)
22
1.4 Features and Uniqueness of MOS Transistor

The MOS transistor has many unique features and advantages in device characteristics, circuit applications, and fabrication, and those features have allowed MOS technology to dominate IC manufacturing for about five decades. From the device operation point of view, it is a field-effect device with near zero gate current (in the recent technology nodes, the gate leakage currents were drastically increased due to the use of ultrathin gate oxide and high-k gate oxide). Thus the MOS device has excellent power efficiency and near infinite input resistance. It is an excellent switching and voltage control device. From the circuit fabrication point of view, the mainstream MOS transistor is a planar (surface) device. The key transistor parameter (gate length) is defined by the lithography process and can be formed by self-aligned together with the formation of source and drain regions. This characteristic is the prerequisite for the device scaling that we have witnessed for five decades. The planar process further makes the mass production and interconnects simpler. Another important factor is the use of silicon dioxide as the gate insulator, although this importance is now dismissed because of the introduction of high-k gate dielectric materials. This is one of the major reasons for the continuous device size miniaturization and scale expansion of Si MOS technology in the past five decades. Meanwhile, the performance of the MOS transistor is greatly governed by the gate dielectric/Si interface as the conduction channel is in the surface region. Silicon oxide/Si has been the best interface with extremely low interface trap density [2]. Silicon oxide is also the best insulator that can be grown on Si because of the low coordination number (see Chapter 2). Meanwhile, silicon dioxide can be easily grown thermally and be removed either with wet or dry etching. This unique masking capability makes the integrated circuit (IC) fabrication process simple and that is not available on other materials. This is another key factor for the success of CMOS technology in the early stage. For the circuit application of MOS transistors, it offers many unique and excellent circuit configurations as the key building blocks in modern digital and analog systems. These structures have not been possible in other kinds of transistor. For example, the two-transistor static CMOS inverter (see Figure1.16) is still the simplest inverter with the least number of interconnects. This inverter is operated by turning on or off the nMOS or pMOS transistor alternatively with negligible input current and it cuts off the current flowing from the power to ground to the greatest extent. It offers the best fan-in value and the lowest power dissipation among all static logic families. It has excellent noise margins also. Another example is the structure of a single transistor dynamic random access memory (DRAM) cell (see Figure1.17) used today. It is really an amazing structure. The three terminalsdrain, gate, and sourceare used, respectively, as bit line, word line, and charge
23
VDD
Vi
Vo
FIGURE 1.16 A CMOS inverter realized using a pMOS and an nMOS transistor as pull-up and pull-down controls, respectively. This structure uses a minimum number of interconnects and achieves the lowest power consumption of static logic devices. Bit Line Word Line
FIGURE 1.17 A dynamic random access memory (DRAM) cell realized using one MOS transistor for access and write control.
storage. (In actual realization, the capacitor is not an independent device. It is realized by using a bigger source region of the MOS transistor.) There is not any redundancy. The gate (word line) is used to access the cell. The sensing (read operation), charging, or discharging (write operation) of the source capacitor is achieved by applying different drain (bit line) voltages. It is the most compact and lowest-cost RAM cell. With a floating gate embedded in the gate insulator (see Figure1.18), a MOS structure is transformed into a memory transistor. This memory cell or with some modifications is the fundamental component of the present nonvolatile flash memory used for USB disks, memory cards, and solid-state disks. The injection of channel
24
Gate Floating Gate Source Drain
n+
n+
FIGURE 1.18 Nonvolatile memory is achieved with a modified MOS structure. The memory function is realized by charge storage in an isolated floating gate to achieve nonvolatile storage for over a 10-year period. Multi-bit per transistor can also be realized by using multiple floating gates.
electrons into the floating gate can be done via avalanche breakdown [31] or FowlerNordheim (FN) tunneling [21], and it modifies the threshold voltage, which in turn causes different drain currents under the same gate bias in the memory transistor. Since the sensing of memory content is done via the field effect, it has very low power dissipation for the read operation. Although the single transistor memory cell does not offer a full access control as the DRAM cell, by connecting a number of identical memory transistors in a bank or in a block using logic NAND or NOR configuration, a near one-bit per transistor structure can be achieved. Multi-bit per transistor can also be realized by using a multiple floating gate structure. The three examples mentioned here are the most successful applications of MOS transistors and have become the most important driving forces for the recent microelectronic technology evolution. The International Technology Roadmap for Semiconductors (ITRS) [32] has put the development/ scaling trend of these three kinds of products as the key technology indicators. Figure 1.19 depicts the trends being predicted by ITRS for the next quarter century. The sizes of the devices will be downscaled according to the Moores law and eventually some deca-nanometer (~10 nm) gate length or half pitch devices will be used in these three major digital technologies.
1.5 MOS in Deca-Nanometer

When the size of the MOS transistor is to be scaled into the deca-nanoscale, the gain in drain current is not merely scaled by the 1/L rule. Theoretical results have demonstrated that a much higher value of drain current can be achieved because of the faster charge transport mechanism. In a deca- nanometer
25
100 Flash 1/2 pitch DRAM 1/2 pitch MPU metal-1 1/2 pitch
Half Pitch Length (nm)
10
1 2010
2012
2014
2016
2018 Year
2020
2022
2024
FIGURE 1.19 The technology trends of the three key productsflash, DRAM, and MPUpredicted by ITRS 2010 (see International Technology Roadmap 2010 update: http://www.itrs.net/ Links/2010ITRS/ 2010Update/ToPost/2010_Update_Overview.pdf).
transistor, the dimension of this device is so small that quantum confinement will occur and the carrier distribution in the quantized subband levels can no longer be neglected [33]. On the other hand, when the channel length is in the same order of magnitude or even shorter than the mean free path of the charge carrier, the carrier transport can no longer be described by the classical scattering model. The carrier may even transport in such a manner that it reaches the drain without suffering any phonon, impurity, or surface defect scattering, which is known as the ballistic transport. According to Natori [34], the ballistic drain current can be calculated by I D ,ballistic = 2 q( kT )3/2 2 2
valley
my F1/2
FS En En qVD F1/2 FS kT kT (1.36)
where my is the electron effective mass along the channel, FS is the Fermi level of the source electrode, En is the nth subband energy at maximum point, and F1/2(*) is the Fermi-Dirac integral.
26
Drain Current/Unit Width (mA/m)
1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Drain Voltage (V) 1 VG = 1.4 V VG = 1.2 V VG = 1.0 V VG = 0.8 V VG = 0.6 V VG = 0.4 V VG = 0.2 V 1.2
77K,
Exp. 70-nm MOS. Ballistic MOS, (E. One-Subband Approx.)
FIGURE 1.20 Experimental I-V characteristics are much poorer than those predicted by the ballistic model because of the carrier quantization effects. (Reprinted from K. Natori,Ballistic MOSFET reproduces current-voltage characteristics of an experimental device, IEEE Electron Device Lett., 23 (2002) 655657. IEEE. With permission.)
However, the experimental results always deviate from the ballistic current predicted by Equation (1.36) [35]. Figure1.20 compares the theoretical results with the single subband approximation and the experimental results for a 70 nm MOS transistor operated at 77 K. The ballistic current is much larger than the experimental results at large gate biases. Although the accuracy in the saturation region could be improved significantly by taking some higher subbands into consideration [35], the discrepancies in the linear region or low electric field region are still very large. There exist several nonideal effects in a practical ballistic or quasi-ballistic MOS transistor as depicted in Figure1.21. In an ultra-short MOS transistor, in the low-electric field or the subthreshold condition, the transistor works well as a bipolar transistor because of the much narrower base width (L). Under this situation, the drain current is governed by the diffusive current as similar to that mentioned in Section 1.3.2 but with a quantized carrier distribution [33]. In addition, the efficiency of the carrier injection from the source and the parasitic source resistance will also limit the current level. At high electric field, the ballistic current is limited by the low field region with width near the source side as depicted in Figure1.22. In this region, the electrons may be scattered back to the source due to the elastic or quasielastic scattering such as impurity and acoustic phonon scatterings. Thus, it is the bottleneck for the charge transport. The backscattering of the carriers significantly reduces the current in the linear region (see Figure1.21). However, if a high-energy electron escapes from this region, it will transport
27
Drain Current (A/m)
Ballistic dominating Back scattering limited Subband limited
Source resistance
Drain Voltage (V)
FIGURE 1.21 Illustration of the dominating or limiting mechanisms governing the charge transport in a ballistic or quasi-ballistic MOS transistor.
Source Energy
qVDS Backscattering Region
Ballistic Region L Channel Length Direction
Drain EC
FIGURE 1.22 Illustration of the energy band diagram of a ballistic MOS transistor showing the backscattering region and ballistic region.
into the drain without suffering any scattering. The backscattering events are governed by the carrier mean free path (). That is, if << , the backscattering is negligible and the transistor is mainly governed by the ballistic effect; on the other hand, if >> , backscattering becomes significant and the drain current will be limited by the backscattering rate. When = L, the
28
backscattering region extends to the whole channel and the transistor does not operate at the ballistic mode at all. The linear and saturation ballistic currents of the transistor can be modified, respectively, by [36] I D ,lin = rlin I D ,ballistic I D , sat = rsat I D ,ballistic 2 rsat (1.37) (1.38)
where the transmission coefficients are given by rlin = + +L (1.39)
rsat =
(1.40)
By considering the backscattering effect, Rahman and Lundstrom developed a compact model [36]: I DS = COX vT W 1 r 1 exp(VDS /Vth ) (VGS VT ) r 1+ r 1+(1 1+ r ) exp( VDS /Vth ) (1.41)
The source injection velocity in (1.41) can be approximated with the equilibrium thermal velocity, which is given by vT = 2 kT m * (1.42)
The typical value of the thermal velocity is slightly about 107 cm/s for carrier sheet density lower than 1011 cm2. The velocity increases for higher sheet carrier density. A more accurate numerical calculation was made by Lundstroms group [37, 38] by using a Greens function approach and Bttiker probes approach for scattering. Figure1.23 shows the I-V characteristics for a 10 nm channel length MOSFET. By taking the mode space into consideration in the channel width direction, the effect of quantum confinement on the threshold voltage was also considered. The drain current is smaller because of a larger threshold voltage yielded by this treatment. The drain current is even smaller (see Figure1.23[b]) if the scattering events are considered by using the Bttiker probe model in the Green function calculations.
29
2000
1500 IDS (A/m)
1000
500
0.1
0.2 VDS (a)
0.3
0.4
2000
1500 IDS (A/m)
1000
500
0.1
0.2 VDS (b)
0.3
0.4
FIGURE 1.23 (a) Current-voltage characteristics of a 10 nm transistor calculated using a classical ballistic transport model (dashed line) and a modified (quantum) model (solid line). (b) Comparison of classical ballistic drain current (dashed line) and quantum dissipative drain current (solid line). (Redrawn from Z. Ren, R. Venugopal, S. Goasguen, S. Datta, and M. S. Lundstrom, nanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs, IEEE Trans. Electron Devices, 50 (2003) 19141925. IEEE. With permission.)
The drain current may be enhanced if the source-to-drain tunneling is taken into account [39]. However, it is noted that significant performance degradations instead of improvements are often reported in the experimental deca-nanometer transistors [40, 41]. Channel mobility is still limited by the classical scattering mechanisms instead of the ballistic transport in these deca-nanometer transistors. Yet these transistors had
30
not been well tempered for ballistic operation. In addition, to circumvent the short-channel effects and DIBL, the channel or part of the channel has to be heavily doped in these devices. These measures degrade the channel mobility because of more significant dopant Coulomb scattering and a higher transverse electric field [42]. The parasitic source and drain resistances also limit the device operation. Meanwhile the direct tunneling from source to drain can cause significant subthreshold leak age. The gate FN leakage current is further enhanced because of the high channel doping. In short, the classical small-size effects become severer in the deca-nanometer transistors.
1.6 Technology Trends and Options

1.6.1 Technology Trends The Semiconductor Industry Association (SIA) extrapolates the historical figures in logarithm-linear plot (Moores law) to predict the future development of silicon microelectronics [32]. The predicted roadmap becomes the goal of semiconductor companies for advancing their technology. According to the roadmap, the MOS physical gate length is halved every 4 years. The physical gate length will be decreased from 25 nm (32 nm technology node in 2009) to 8 nm in 2024 (see Figure 1.24). Making a transistor in this dimension should not pose any physical or technological problems. It was demonstrated that a 4 nm transistor can still function well by using the presently available technology [41]. The 4 nm scale represents a length of 15 Si atoms aligned in a row. That means one atom difference will cause about 6.7% fluctuation in the channel length and might still be too large for the gigascale circuits. If the gate length would be 3 nm, then a single-channel atom induced gate length fluctuation would increase to 9%. The control of a single atom tolerance might be impossible to achieve, and even if it is possible someday, the costs of fabrication facilities might be unacceptable. Hence, from the single device point of view, the downsizing trend can still keep up with Moores law for several decades. However, the manufacturable size of the MOS transistor will be much larger than the physical limit and the device downsizing will end soon whether it is 8 nm, 4 nm, or 3 nm [1]. The device downsizing may even end earlier because of the diminishing return. The rapid increase in fabrication costs, worsened yield, and degraded device performances may reach the point of diminishing economic returns. As a result, Moores law for MOS large-scale circuits may stop at around 8 nm, which is long before the fundamental physical limits. The recent edition of ITRS has realized this scenario and proposed some possible future technological trends in terms of More Moore, More
31
101
Hi
Channel Length (m) 100
sto
ric
al
Fig u
res
101
100 nm
102
ITR 45 nm SP 32 nm red icti Ind 22 nm on ust 16 nm ry 11 nm Lo gic 8 nm No de s
10 nm
103
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025 Year
FIGURE 1.24 Historical trend and ITRS prediction of the downsizing of the gate length of MOS transistors used in logic circuits. Note that gate lengths of 32 nm and 25 nm were used, respectively, for the 45 nm and 32 nm industry nodes because of the different definitions.
Than Moore, and Beyond CMOS [32]. As mentioned, the CMOS device may be further scaled down to sub- deca-nanometer range (More Moore) for a couple of decades because there are still many options available for circumventing the materials and technological constraints (see Section 1.6.2). At the end of Moores law for CMOS technology (Beyond CMOS), there are some new devices available. However, to develop the new devices into the scale of the present CMOS technology would take a long time. Hence more feasible technology development from now on and the technology development at the end of Moores law are to fully utilize and to enrich the present CMOS technology. This technology development is termed as More Than Moore in the ITRS terminology. 1.6.2 Technology Options Over the last five decades, the device drivability or performance improvement of MOS transistors mainly relied on the downsizing. As the transistor size is now approaching the downsizing limit [1], other possibilities have been extensively explored in recent years. In principle (see Equation [1.5]), better performance can be achieved by producing larger charge density with smaller voltage (e.g., larger COX) and by making carrier transport faster (e.g.,
32
using higher mobility material or ballistic transport). On the other hand, in the CMOS logic and memory device, power dissipation is now another major concern. Hence, the OFF current minimization has become another important figure of merit. This can be done with thicker and larger band offsets, dielectric films or better electrostatic integrity (EI) structure (see Section 1.3.3). Meanwhile, the scaling may lead to the overall performance degradation instead of further improvement because of the short-channel effects as mentioned in Section 1.3 and the more significant effects resulted from the parasitic components. Hence the performance improvement can also be achieved with those device structures offering better scalability, smaller parasitic resistances, and fringing capacitances. Thus, the device performance improvements have now been investigated in every aspect of the device physics and material properties of the transistors including (a) device structures, (b) channel materials, (c) source/drain structure, and (d) gate electrode and gate dielectric materials. The feasible fabrication processes for deca-nanometer integrated chip fabrication have been quite clear now. In particular, plasma doping with flash or laser annealing [4347] or metallic junction [4853] can be used for making low resistivity and ultra shallow source and drain junctions; strained Si or germanium can be used as channel material to enhance the mobility [54 60]; and SOI double gate [6164] or even three-dimensional structure [6569] can be used to achieve a better electrostatic control. High-k/metal gate stack [7075, 9096] can be used for the gate structure to achieve low gate leakage and better threshold voltage control; the deca-nanometer size patterning can be done with EUV or nano-imprint technique; and low-k interlayer insulator can be used for the copper interconnects [7678]. These technologies have already been on schedule to be introduced in future technology nodes (see Figure1.25). Detailed discussion on these materials and processes related to the deca-nanometer transistors is given below. 1.6.2.1 Device Structures Many device structures that demonstrate better performances or scalability have been reported. According to the EI quoted in (1.24), one way to improve the EI is to reduce the junction and depletion depths, that is, xj and Tdepl. This can be done effectively with an ultrathin body (UTB) by using a siliconon-insulator (SOI) structure. Figure1.26 shows the cross-sectional view of a UTB SOI transistor. If the silicon layer, TSi, is not thin enough, the channel depletion layer (Tdepl) may still be smaller than TSi, which is known as partially depleted SOI (PDSOI). Since xj > TSi, xj is replaced by TSi, which still leads to a better EI value. If the whole Si layer is fully depleted, then Tdepl is replaced by TSi also and we have a much smaller Tdepl /L ratio. To obtain the lowest subthreshold slope (60 mv/dec) and acceptable DIBL in an FDSOI device, a practical rule is used: TSi L/4. That is, for 10 nm gate length, TSi
33
Year Gate Length (nm) Gate Dielectric EOT (nm) Junction Depth (nm) Lithography Bulk/SOI Multiple Gate Channel Material S/D Junction Gate Dielectric Low-k (inter-metal)
2009 28 1.0 14.0 ArF PDSOI
2011 22 0.8 11.0
2013 16 0.6 8.0
2016 11 0.4 5.5
2019 8 0.3 4.0
2022 7.4 0.3 3.7
ArF Immersion
EUV/Nano imprint FDSOI
Single Gate Si
Double Gate Strained Si Ge
FinFET III-V Metal La-based Low-k
Ultra-shallow junction Hf-based SiO2
FIGURE 1.25 Available technology options to be introduced for CMOS chip fabrication. Gate
Source
Drain
xj
n+
L BOX
n+
TSi
Silicon substrate FIGURE 1.26 Illustration of silicon-on-insulator (SOI) MOS transistor based on buried oxide (BOX) structure.
should be less than 2.5 nm, which is still difficult to achieve with the present technology. Thus PDSOI may be first introduced in the coming technology nodes instead of FDSOI. Physically, even better device structures such as the multi-gate devices [6165], FinFET, and other gate-all-around (GAA) [6669] structures have been proposed and many feasible fabrication techniques have been developed. By reducing the thickness of buried oxide and applying a second gate electrode (see Figure 1.27), the channel electrostatic control can be further
34
Gate 1
Source n+ L BOX Gate 2 (Substrate)
Drain n+
FIGURE 1.27 Cross-sectional view of a double-gate MOS transistor (DG-FET) based on SOI technology.
Fin Gate Source Drain
Buried Oxide FIGURE 1.28 Structure of a FinFET.
improved. The improvement can be readily understood by considering the junction and depletion depths to be half of silicon thickness (Tdepl1 = Tdepl2 = xj = TSi/2). This structure provides a better control on the short-channel effects and drivability. It was reported that a subthreshold swing of 60 mV/dec can be obtained with this structure and a volume inversion can be achieved in the saturation region [63]. Meanwhile, the DG structure also reduces the transverse electric field by 50% as compared with the single-gate structure [64]. Hence, the channel mobility can be significantly enhanced because of the reduction of the surface roughness scattering in this structure. In the FinFET or tri-gate structure, current flow on the three surface regions provides even better electrostatic control (see Figure1.28). These structures look promising for transistors with gate lengths in the deca-nanometer range. 1.6.2.2 Channel Engineering In the short-channel devices, the channel mobility has been greatly degraded due to the significant increase in Coulomb and surface roughness scatterings.
35
Stress
Without Strain
Under Tensile Stress 4-fold degenerate ellipsoids
6-fold degenerate ellipsoids
2-fold degenerate ellipsoids Si Conduction Band FIGURE 1.29 Comparison of normal silicon conduction band and degenerated ellipsoids with those with tensile stress.
The typical channel electron mobility is now below 200 cm2/V-s, which is much smaller than the bulk mobility of silicon. Although using a higher mobility channel material is a straightforward method to boost the performance of a MOS transistor, it was not used in the past because it involves a substantial change in material and fabrication processes. Scaling has been the easiest way to improve the performance of MOS transistors. As the transistor size is scaling toward the economically viable lithography limit, use of high-mobility channel material will become a viable option in the coming technological nodes. Without substantial change of the fabrication process, strained silicon seems to be the first choice. By applying compressive or tensile strain, the band structure of silicon can be modified. Figure1.29 illustrates the idea of this effect. The biaxial strain results in the conduction band splitting and electron redistribution in the degenerated ellipsoids. As the unprimed subbands have lower energies, more electrons reside in the transverse direction and they have smaller conductivity masses; as a result, the conduction mobility is enhanced. Meanwhile, due to the band bending in the valence band, more light holes are generated. Hence, both electron mobility and hole mobility can be increased in the strained silicon. Bulk relaxed SiGe pseudo sub strates obtained by graded SiGe buffer were intensively investigated for this purpose during the last couple decades [5459]. By growing pseudomorphic silicon on SiGe substrates, the lattice mismatch between the silicon and the germanium induces a high biaxial
36
1000 Channel Electron Mobility (cm2/Vs) Universal Mobility Strained Si/Relax. SiGe 28% Strained Si/Relax. SiGe 13% 600
800
400 Controlled Si
200
0.2
0.4
0.6 0.8 1.0 Electric Field (MV/cm)
1.2
1.4
FIGURE 1.30 Comparison of effective channel electron mobility for strained silicon based on bulk relaxed SiGe pseudo sub strates. (Redrawn from K. Rim, J. Chu, , H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, Characteristics and device design of sub-100 nm strained Si n- and pMOSFETs, Tech. Dig. Symp. VLSI Technology (2002), 9899. IEEE. With permission.)
strain on the silicon layer. The peak mobility of this material can be doubled (see Figure1.30) [59]. The strain can also be obtained by other processes such as silicon nitride deposition or compressive or tensile contact etch stop layer. Up to 20% improvement on the drain current can be achieved by these processes [60]. These materials or processes are quite promising and have already been used in some processes. On the other hand, it was known that hole in (110) crystal orientation has much higher mobility. A dual orientation process with (100) orientation for n-channel and (110) orientation for p-channel was also proposed [84]. Germanium was also proposed to be an alternate channel material because of its higher mobility. Particularly, it has much higher hole mobility than silicon (see Table1.2). On the fabrication aspect, the process advantage of silicon is now negligible because of the use of high-k materials and the excessive use of non-silicon-based thin film materials in the fabrication processes in recent years. Consequently, the unavailability of stable Ge oxide is not an issue anymore from the device fabrication point of view. In addition, germanium has larger energy relaxation time and may cause velocity overshoot to occur in longer gate lengths. Figure 1.31 shows the idea of using highmobility channel materials such as Ge or stained Si in future technology nodes. Different channel materials may be used, respectively, for nMOS and
37
TABLE1.2 Electrons, Holes Bulk Mobilities, Bandgaps, and Thermal Conductivities of Major Semiconductor Materials at 300 K
n (cm2/Vs) 1350 3900 8900 78000 1800 p (cm2/Vs) 450 1900 400 750 1800 Bandgap (eV) 1.12 0.66 1.42 0.17 5.47 Thermal Conductivity (W/m/K) 141.0 59.9 46.0 >2000
Material Si Ge GaAs InSb C Diamond
nMOS Gate Metal Junction
pMOS
Gate
Source
Strained Si SiGe
Drain Source Buried Oxide Si Substrate SiGe or Ge
FIGURE 1.31 Cross-sectional view of dual channel CMOS using strained silicon for nMOS and germanium for pMOS.
pMOS transistors in the same process. In farther technology nodes, some other higher mobility materials such as carbon diamond, GaAs, and InSb (see Table1.2) may also be used and achieving quasi-ballistic or ballistic carrier transport may be possible [85, 86]. 1.6.2.3 Source and Drain Engineering For better electrostatic integrity control, the junction depths of the source and drain junctions should be as shallow as possible, that is, xj << L. For a 10 nm gate length transistor, xj should be less than 4 nm to fulfill a good technology rule [6, 7]. However, the shallowest junction achievable is around 10 nm for the state-of-the-art technology. This ultra-shallow junction can be achieved by very low energy (<1 keV) implantation of heavy molecules such as BF3 and B10H14 [87, 88] or plasma doping [4346]. To minimize the thermal enhanced diffusion during the defect annealing, flash annealing or
38
excimer laser annealing must be used [47]. On the other hand, as mentioned in Section 1.5, the parasitic source and drain resistances may become comparable with the channel resistance and cause significant degradation on the ON current. Thus it is important to maintain the source and drain resistances to be a reasonable fraction (10%) of the channel resistance. Metallic source and drain (metals or silicides Schottky structure) electrodes could be the ultimate option [4853]. The key issue of this option is the selection of suitable material that has a suitable work function for achieving adequate Schottky barrier for channel and low enough contact resistance for both nMOS and pMOS, respectively. 1.6.2.4 Gate Stack Engineering To maintain proper switching characteristics and to suppress the short-channel effects of MOS transistors, the downsizing of the channel length requires an equal factor of reduction in the gate oxide thickness. Figure1.32 shows the technology roadmap for the gate oxide thickness scaling [2]. In the 65 nm technology node with a gate length of 32 nm, the thickness of the silicon gate oxide (SiO2) should be around 0.9 nm. This thickness is already below the technologically manageable thickness for mass production (about 1 nm)
102 Oxide (or Equivalent) Thickness (nm)
101 Direct tunneling limit 100
High Range
Bulk SiO2 physical limit Si-Si distance
ITR
S 20
03
2015 2020
1970
1975
1980
1985
1990
1995 Year
2000
2005
2010
FIGURE 1.32 The roadmap suggested by the Semiconductor Industry Association (SIA) for gate dielectric thickness scaling. See H. Wong and H. Iwai, The road to miniaturization, Phys. World, 18(9) (2005) 4044. (Reprinted with permission from H. Wong and H. Iwai, On the scaling issues and high-k replacement of ultrathin gate dielectrics for nanoscale MOS transistors, Microelectron. Engineer. 83. (2006) 18671904 with permission from Elsevier.)
39
108 107 106 Current Density @ 1V (A/cm2) 105 104 103 1/2 mono layer = 5% uctuation Gate oxide for 107 nm node 101 One mono layer Si-O 101 102 103 104 105 106 107 Min bulk oxide thickness 100 Direct tunneling occurs 2.0 2.5 3.0 3.5 102
0.0
O-Si-O thick 0.5
1.0
1.5
Oxide Thickness (nm) FIGURE 1.33 Direct tunneling current in thin silicon dioxide. Oxide thinner than 1.2 nm would result in too large a gate leakage current and difficulties in process control; high-k material must be used. (Reproduced from D. Misra, H. Iwai, and H. Wong, High-k gate dielectrics, Electrochem. Interface, 14(2) (2005) 3032. Markers are theoretical data taken from S.-.H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, Quantum mechanical modeling of electron tunnelling current from the inversion layer of ultra-thin-oxide nMOSFETs, IEEE Electron Device Lett., 18 (1997) 209211.)
and is very close to the theoretical limit (0.7 nm or 2-monolayer thick) for the bulk silicon dioxide (see Figure1.33) [2]. That is, we have already run out of atoms in the device downsizing and further device scaling would require an even thinner gate dielectric film. Hence, without the introduction of a new dielectric material, Moores law for MOS device downsizing will come to an end very soon [2]. By using a dielectric with a higher dielectric constant, a larger value of gate capacitance can be achieved without reducing the thickness of the dielectric film. With reference to the same capacitance value as that implemented using silicon dioxide, the effective thickness of a high-k dielectric film can be reduced by a factor of ox/khigh-k (where ox and khigh-k are the dielectric constants of the silicon oxide and the alternative high-k material, respectively). This is the concept of equivalent oxide thickness (EOT), which is defined as EOT = ox k high-k thigh-k (1.43)
where thigh-k is the physical thickness of the high-k dielectric film being used for replacing the conventional silicon oxide film.
40
10 Current Density (A/cm2)
|Vg| = 1 V
SiO2 Nitrided SiO2
102
Lu2O3 Sm2O3 Nd2O3
106
La2O3
1010
0.5
1.0 1.5 Equivalent Oxide Thickness (nm)
Pr2O3
HfO2 NH3 + HfO2 HfSiON Al2O3 + HfO2 ZrO2 Zr-Silicate NH3 + ZrO2 Al2O2 ZrAlSiO Ta2O5 Dy2O3 Gd2O3
FIGURE 1.34 Example of leakage current reduction by using some high-k materials. Data are taken from various sources.
It has been suggested that suitable candidates for next-generation gate dielectrics should have a dielectric constant of about 20 to 30 [70, 71]. That is, the physical thickness of a proper high-k gate material can be khigh-k/ox times, typically 4 to 7 times, thicker. Thus, even for dielectric film with 0.8 nm EOT, the physical thickness of high-k film is still above the direct tunneling (DT) limit and the gate leakage current can be kept at a very low level. It has been further demonstrated that material with too large a k value, such as TiO2, is not a good candidate, as it will result in a two-dimensional electric fringing field from the drain through the thick (physical) gate dielectric of the MOS transistors [2, 72]. This fringing field can lower the source-to- channel potential barrier and hence the threshold voltage. Figure1.34 depicts the leakage current of some gate dielectric films reported in the literature [19, 73]. It can be seen that the leakage current level could be reduced by several orders of magnitude by replacing the conventional silicon oxide with high-k materials of the same EOT values. High-k material has made the gate oxide scaling beyond the sub-nanometer EOT range possible; and the downsizing of CMOS devices is expected to proceed for more generations [2]. A practical example of the benefits of using high-k gate dielectric is the Intel Core 2 processor family, which is fabricated using 45 nm CMOS technology. By adopting hafnium-based high-k dielectric film, the power dissipation of the Core 2 microprocessor has been significantly reduced as compared with the Pentium 4 duo, with a significant improvement in speed and certain
41
other performances [89]. However, gate capacitance and leakage current are not the only concerns in the ultimate nanoscale CMOS devices. When interfacing with a silicon substrate, the overall performances of MOS device with high-k gate dielectric are far below those with silicon oxide, which has been used as a MOS gate dielectric material and has been studied intensively for more than 40 years. There is a general consensus that the next-generation gate dielectric materials must meet certain other requirements in addition to their higher k value [2, 74, 75]. The high-k materials should be chemically stable with the Si substrate and gate electrode, and they should be thermally stable at temperatures of no less than 500C. Moreover, they should have good interface properties with the Si substrate so that the structure can exhibit low interface trap density, high channel mobility, low oxide trap density, and large band offset energies [2]. These issues will be discussed in detail in Chapters 2 to 5. 1.6.3 More than Moore It was predicted that the downsizing of the transistor will end within a couple decades, but the CMOS technology will still be the dominating technology for most of the electronic products we already have and the new electronic products we may have in the future. Beyond the boundaries of the digital world powered by Moores law, there are lots of great unexplored domains. Digital CMOS technology will still be the solid base and the main framework for future electronics as well as other technology advancements. Indeed CMOS technology has already penetrated into many nontraditional areas in the last decade as the digital CMOS technology has kept pace with its historical speed: Moores law. For example, the CMOS technology has made quite successful advancement in the analog and radio-frequency (RF) applications for mobile wireless communications [9094]; with the availability of nanoscale CMOS fabrication technology, visible light emitting or even lasing effects were observed in low-dimensional (LD) silicon materials [9598]. The SIA recently became aware of this trend and termed the CMOS technology developments other than digital functionalities as More Than Moore [99]. In the ITRS white paper, as also depicted in the x-y plane of Figure1.35, the domains being identified are (a) RF and analog applications of CMOS, (b) passive devices, (c) high voltage (HV) and power devices, (d) transducers and sensors for physical and electrical signals such as electromagnetic, mechanical, chemical, and biological sensors, and (e) biochips. The developments and the advancements of these devices are most likely not to be characterized with the size or density as used in Moores law. These devices may be built with the existing CMOS technology such as RF CMOS and power MOS devices and circuits or may be built with other completely different technologies but will be integrated with CMOS circuits via system-on-chip (SoC) or system-in-package (SiP) technology [102]. These technologies not only provide viable techniques for incorporating non-CMOS devices but also
42
M or (c e th om a pu n M tin oo g) re
Software, Architectures Applications
o Mo re o M
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s ore Mo OS CM e lin ase
w La
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m level)
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ive
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oo nM tha ore M
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FIGURE 1.35 Possible scenarios More Than Moore. The baseline digital CMOS technology will still be the main framework for future electronic products. It will be enriched with better human-machine, machine-environment interfacing. The impact of CMOS technology will be further enhanced with better algorithms, better system architectures, and more diversified applications.
solve the technical difficulties of making gigascale systems. The major constraints for gigascale integration are the yield and interconnection complexity. Both of the constraints may be overcome by using multichip modules or the SiP approach. The subsystems or modules can be fabricated separately and then can be fitted in the grooves made on a mother chip and follow with multilevel interconnection. This approach not only increases the chip density and simplifies the interconnection complexity but also significantly reduces the intra-chip parasitic capacitance and thus the signal delay. This is the major technology trend described by ITRS. At present, the More Than Moore concept sketches the possible technologies or functional units for enriching the mainstream digital CMOS technology so that the CMOS technology will improve the human-environment and human-machine interfaces. Another More Than Moore domain (x-z plane in Figure1.35) that can lead to significant technology advancement is the software, algorithms, new system architectures, and new applications. Without substantial advancement in the CMOS technology, more powerful computers will still be made
8n m ?
ITR
SD
om
ain
vir Sen onm Ac sors/ tua ent tor Bio s chi ps
and
en
re (So C, SiP )
43
by introducing some novel algorithms and system architectures (z-axis). Some new applications of the existing CMOS chips may also produce a great impact in the future. The Internet and now cloud computing are the best examples of this domain. There should be much room for this domain development in the More Moore and Beyond CMOS eras. In terms of individual element response time, the MOS device is several orders of magnitude faster than any biological system where the synapse interaction is normally in the millisecond range. In terms of system scale, the latest computer system has been on the order of the human brain in terms of number of neural cells. However, in terms of intelligence and power consumption, the performances of the modern computer are even far below that of an insect [102]. A revolution in the system architecture and computing methods is expected. Hence, the ultimate More Than Moore, as depicted in Figure1.35, paves the way for a complete development of every capability and potential of the existing CMOS technology, for its integration with other technologies and incorporation with new system architectures and algorithms, as well as for its new applications.
1.7 Summary
The decreasing of the device feature size will end soon, although many new devices have been proposed. Experiments on single electrode devices and quantum computing have been reported. However, to enable the entanglement between two solid-state quantum bits, the operation was based on low-temperature superconducting tunnel junctions [103]. Hence, even if the device itself is extremely small, the system size and the operation cost will be much higher than the smaller-larger-faster-cheaper CMOS technology. Carbon-nanotube FET or graphene FET are other possible substitutions for CMOS technology. However, processes for manufacturing and interconnecting such fine structures are still unavailable, not to mention using them in ultra-large-scale circuit fabrication. CMOS microchips should still be the heart of future electronic products for a long period. However, under the framework of CMOS technology and beyond the boundaries of Moores law, many new domains are being explored to enrich the functionalities and to improve the human interfaces with the electronic products as well as to develop some new applications. We shall have more powerful computers and electronic systems even as Moores law comes to an end. CMOSphotonics integration will be a very attractive technology option for this purpose. With the availability of the nanoscale Si and the mature microfabrication technology, it has been demonstrated that the photonic devices and systems can be built on Si materials. This trend will be very attractive as we can move gradually from electronic system to photonic system.
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There is no need to invest too much or to devote too much research effort at one time to commercialize the intermediate hybrid electronic-photonic products. Another impact of CMOS-photonics integration is the on-chip optical interconnection. The interconnects have been the major technology bottleneck for ultra-large-scale Si microchips because of the complexity, the significantly increased resistance in thin copper wires, and the interconductor capacitance of the denser interconnects. With optical interconnects, hundreds of address lines, data lines, and control lines between the functional blocks can be replaced by a single optical waveguide. This may be a way to extend the myths of smaller-larger-faster-cheaper Si technology. The smaller feature is still provided by the CMOS system. Larger scale is possible with the available optical interconnection, faster operation can be provided by the optical computing, and cheaper is certainly attributed to the Si materials and CMOS microfabrication technology. In any case, CMOS technology will still be the most important technology in the foreseeable future.
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CMOS Technology Overview

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1

Overview of CMOS Technology

Nano-CMOS Gate Dielectric Engineering

4004 103 1970 1975

Overview of CMOS Technology

1.2  MOS Transistor: A Quick Introduction to Classical Models

Nano-CMOS Gate Dielectric Engineering

LG Gate Source Drain VGS VDS IDS W n+ L n+

Overview of CMOS Technology

where W is the channel width.

Nano-CMOS Gate Dielectric Engineering

Overview of CMOS Technology

Vacuum q S EC EI EF EV EF Inversion Region Metal Charge QD Qinv WD y Silicon

Eg QOX Q = M S + + F OX COX 2q COX

Nano-CMOS Gate Dielectric Engineering

Overview of CMOS Technology

1.3  Short-Channel Effects and Short-Channel Modifications

Nano-CMOS Gate Dielectric Engineering

300 K (100) Electron 102 0.1 Eective Field [MV/cm] 1.0

Overview of CMOS Technology

Nano-CMOS Gate Dielectric Engineering

8 7 6 Drain Current (mA) 5 4 3 2 1 0

2 2.5 3 Drain Voltage (V)

qVDS (Base) Drain EC EV Channel Length Direction

Overview of CMOS Technology

Nano-CMOS Gate Dielectric Engineering

Overview of CMOS Technology

Nano-CMOS Gate Dielectric Engineering

n+ Gate-induced space charge layer (a) Junction space charge layer

Overview of CMOS Technology

1.0 Gate Length (m)

Nano-CMOS Gate Dielectric Engineering

JFN JPF JTrap JDT EC

Overview of CMOS Technology

106 105 104

15 20 21.9 25.6 29.1 32.2 35.0 36.1 2.0 2.5 3.0

Gate Voltage (V)

where E is the externally applied field.

Nano-CMOS Gate Dielectric Engineering

Overview of CMOS Technology

nWph Wph S Pi (WT + nWph ) (1.34) S coth In 2 kT 2 kT sinh(Wph /2 kT )

Nano-CMOS Gate Dielectric Engineering

1.4  Features and Uniqueness of MOS Transistor

Overview of CMOS Technology

Nano-CMOS Gate Dielectric Engineering

Gate Floating Gate Source Drain

1.5  MOS in Deca-Nanometer

Overview of CMOS Technology

Half Pitch Length (nm)

FS En En qVD F1/2 FS kT kT (1.36)

Nano-CMOS Gate Dielectric Engineering

Drain Current/Unit Width (mA/m)

Exp. 70-nm MOS. Ballistic MOS, (E. One-Subband Approx.)

Overview of CMOS Technology

Drain Current (A/m)

Ballistic dominating Back scattering limited Subband limited

Drain Voltage (V)

qVDS Backscattering Region

Ballistic Region L Channel Length Direction

Nano-CMOS Gate Dielectric Engineering

where the transmission coefficients are given by rlin = + +L (1.39)

Overview of CMOS Technology

1500 IDS (A/m)

1.2 MOS Transistor: A Quick Introduction to Classical Models

1.3 Short-Channel Effects and Short-Channel Modifications

1.4 Features and Uniqueness of MOS Transistor

1.5 MOS in Deca-Nanometer

1.6 Technology Trends and Options