XD-DV290

K(B),EZ(B)

SERVICE MANUAL
DVD PLAYER BASIC DVD MECHANISM : LDM-H109 (6721R-0300A)

This Service Manual is the Revision Publishing and replaces Simple Manual K<B>:(S/M Code No.09-99C-337-5T2) EZ<B>:(S/M Code No.09-99C-337-5T3).

RE
S/M Code No. 09-99C-337-5R2

DA TA

VI

SIO

TABLE OF CONTENTS
SPECIFICATIONS .................................................................................................................................. 3 ACCESSORIES/PACKAGE LIST ........................................................................................................... 3 PROTECTION OF EYES FROM LASER BEAM DURING SERVICING/ Precaution to replace Optical block......................................................................................................... 4 DISASSEMBLY INSTRUCTIONS ...................................................................................................... 5-10 ELECTRICAL MAIN PARTS LIST ........................................................................................................ 11 TRANSISTOR ILLUSTRATION ............................................................................................................ 12 BLOCK DIAGRAM-1 (OVERALL) ......................................................................................................... 13 BLOCK DIAGRAM-2 (POWER) ............................................................................................................ 14 BLOCK DIAGRAM-3 (RF/DSP/SERVO) ............................................................................................... 15 BLOCK DIAGRAM-4 (AUDIO) .............................................................................................................. 16 BLOCK DIAGRAM-5 (MPEG) ............................................................................................................... 17 BLOCK DIAGRAM-6 (SYSTEM CONTROL) ........................................................................................ 18 WIRING-1 (MAIN: COMPONENT SIDE) ........................................................................................ 19, 20 WIRING-2 (MAIN: CONDUCTOR SIDE) ........................................................................................ 21, 22 SCHEMATIC DIAGRAM-1 (MAIN 1/5) ............................................................................................ 23, 24 SCHEMATIC DIAGRAM-2 (MAIN 2/5) ............................................................................................ 25, 26 SCHEMATIC DIAGRAM-3 (MAIN 3/5) ............................................................................................ 27, 28 SCHEMATIC DIAGRAM-4 (MAIN 4/5) ............................................................................................ 29, 30 SCHEMATIC DIAGRAM-5 (MAIN 5/5) ............................................................................................ 31, 32 SCHEMATIC DIAGRAM-6 (JACK) ................................................................................................. 33, 34 WIRING-3 (JUNCTION/JACK) ........................................................................................................ 35, 36 SCHEMATIC DIAGRAM-7 (JUNCTION) ........................................................................................ 37, 38 WIRING-4 (TIMER/KEY/POWER) .................................................................................................. 39, 40 SCHEMATIC DIAGRAM-8 (TIMER/KEY) ....................................................................................... 41, 42 SCHEMATIC DIAGRAM-9 (POWER) ............................................................................................. 43, 44 WAVE FORM ................................................................................................................................... 45-47 TROUBLE-SHOOTING .................................................................................................................... 48-57 LCD DISPLAY ....................................................................................................................................... 58 IC DESCRIPTION ............................................................................................................................ 59-77 IC BLOCK DIAGRAM ....................................................................................................................... 78-80 MECHANICAL EXPLODED VIEW 1/1 .................................................................................................. 81 MECHANICAL PARTS LIST 1/1 ........................................................................................................... 82 MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 83, 84 MECHANISM PARTS LIST 1/1 ............................................................................................................. 85

SPECIFICATIONS
DVD VIDEO PLAYER
Power supply Power consumption Mass External dimensions Signal system Laser Frequency range (digital audio) Signal-to-noise ratio (digital audio) Audio dynamic range (digital audio) Harmonic distortion(digital audio) Wow and flutter Operating conditions 100V~240V, 50Hz 20 W 3.5kg(7.7lbs) 430 * 91 * 293 (W * H * D) NTSC SSemiconductor laser, wavelength 655nm (DVD) /795nm (CD) 2Hz to 44kHz More than 105dB (EIAJ) More than 95dB (EIAJ) 0.003% Below measurable level (less than +0.001% (W.PEAK) (EIAJ) Temperature : 5C(41F) to 35C(95F), Operation status : Horizontal

OUTPUTS
Video outputs S video outputs Component video output Audio output (digital audio) Audio output (optical audio) Audio output (analog audio) 1.0V (p-p), 75 , negative sync., RCA jack x 1 (Y) 1.0V (p-p), 75, negative sync., Mini DIN 4-pin * 1 (C) 0.286V (p-p), 75 (Y) 1.0V (p-p), 75,negative sync., RCA jack * 1 (Pb)/(Pr) 0.7V (p-p), 75 0.5V(p-p), 75, RCA jack * 1 Optical connector * 1 2.0Vrms (1kHz, 0dB), 330, RCA jack (L, R) * 2

Design and specifications are subject to change without notice . Weight and dimensions shown are approximate.

ACCESSORIES/PACKAGE LIST

REF. NO 1 2 3 4 5

PART NO. S8-35R-S00-09G S8-615-20G-000 S7-11R-2N0-13A S5-640-17B-000 S5-640-18B-000

KANRI NO.

DESCRIPTION

INSTRUCTION ASSY DVD-2520N CABLE ASSY REMOTE CONTROLLER A PLUG ASSY PHONE CORD 1WAY PLUG ASSY PHONO CORD

PROTECTION OF EYES FROM LASER BEAM DURING SERVICING

This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing.

CAUTION
Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE FROM A DISTANCE OF MORE THAN 30cm FROM THE SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL PICK-UP BLOCK. Caution: Invisible laser radiation when open and interlocks defeated avoid exposure to beam. Advarsel:Usynling laserstling ved bning, nr sikkerhedsafbrydere er ude af funktion. Undg udsttelse for strling.

ATTENTION
L'utilisation de commandes, rglages ou procdures autres que ceux spcifis peut entraner une dangereuse exposition aux radiations.

ADVARSEL!
Usynlig laserstling ved bning, nr sikkerhedsafbrydereer ude af funktion. Undg udsttelse for strling. This Compact Disc player is classified as a CLASS 1 LASER product. The CLASS 1 LASER PRODUCT label is located on the rear exterior.

VAROITUS!
Laiteen Kyttminen muulla kuin tss kyttohjeessa mainitulla tavalla saattaa altistaa kyt-tjn turvallisuusluokan 1 ylittvlle nkymttmlle lasersteilylle.

VARNING!
Om apparaten anvnds p annat stt n vad som specificeras i denna bruksanvising, kan anvndaren utsttas fr osynling laserstrlning, som verskrider grnsen fr laserklass 1.

CLASS 1 KLASSE 1 LUOKAN 1 KLASS 1

LASER PRODUCT LASER PRODUKT LASER LAITE LASER APPARAT

Precaution to replace Optical block (LPC-512A)

Body or clothes electrostatic potential could ruin laser diode in the optical block. Be sure ground body and workbench, and use care the clothes do not touch the diode. 1) After the connection, remove solder shown in the right figure.

Solder

DISASSEMBLY INSTRUCTIONS
CAUTION BEFORE STARTING SERVICING Electronic parts are susceptible to static electricity and may easily damaged, so do not forget to take a proper grounding treatment as required. Many screws are used inside the unit. To prevent missing, dropping, etc. of the screws, always use a magnetized screw driver in servicing. Several kinds of screws are used and some of them need special cautions. That is, take care of the tapping screws securing molded parts and fine pitch screws used to secure metal parts. If they are used improperly, the screw holes will be easily damaged and the parts can not be fixed.

CABINET DISASSEMBLY 1. Top Case

1) Release 7 screws (A). (See Fig-1) 2) Lift the top case with holding the back of it, and remove it in the direction of the arrow.

3. Front Panel
1) 2) 3) 4) Eject the disc tray. (See Fig-2) Remove the tray door. (See Fig-2) Release 2 screws (B). Pull the front panel toward you while pressing 7 stoppers to disengage, and remove the front panel. (See Fig-3)

Top Case (A)

(A)

(A)

(A) (A)

(A) (A) (B) (B) Stopper

Stopper Front Panel Fig-1

Fig-3

2. Tray Door
1) Eject the disc tray. 2) Lift up the tray door in the direction of the arrow.

Tray Door

Disc Tray Fig-2

CIRCUIT BOARD DISASSEMBLY

Note: Before removing the main circuit board, be sure to shortcircuit the laserdiode output land. After replacing the main circuit board, open the land after inserting the flexible connector. (Refer to Mechanism Disassembly)

6. TIMER and Key C.B

1) Remove the front panel. (See Fig-3) 2) Release 5 screws (E), and remove the TIMER C.B.

4. Main/JACK C.B
1) Remove the top case. (See Fig-1) 2) Release 10 screws (C), and take out the main/JACK C.B. (See Fig-4) 3) Remove the flexible connectors and the connector from main circuit board. 4) Then, remove the main JACK C.B. (C) (C) JACK C.B (C) Main C.B Flexible connector (C) TIMER C.B Flexible connector (C) (C) (C) (C) Fig-6 Key C.B (E) (E) (E) (E) (E)

(C)

Fig-4

5. Power C.B
1) Release 4 screws (D). (See Fig-5)

Power Code (D) (D) (D) (D)

Power C.B

Fig-5

DECK MECHANISM PARTS LOCATION

Bottom View
Procedure Starting No.
1 Parts Junction P.C.Board Fixing Type 4 Screws, 4 Locking Tabs 2 3 4 5 Bracket Assembly Clamp Bracket Clamp Clamp Assembly Disk Plate Clamp Magnet Clamp Clamp Lower Tray Disk Base Assembly Feed Rubber R Spring Skew Shaft PU Main Shaft PU Sub Mechanism Assembly PU Unit 1 Locking Tab 1 Connector 1 Screw 1 Hook 2 Screws 4-2 4-2 4-2 4-2 4-2 4-2 4-3 4-4 4-4 4-4 4-4 4-4 4-4
Disassembly Figure

Bottom

4-1

5 5, 6 2 2, 8 2, 8 2, 8

6 7 8 9 10 11 12 13 14

Top View

2, 8, 11 2, 8, 11 2, 8, 12, 13 2, 8, 12-14 2, 8, 12-14 2, 8, 12-16 2, 8, 9 2, 8, 9 2, 8, 9 2, 8, 9-20 1, 2, 8, 9 1, 2, 8, 9 2, 8, 9 2, 8, 9 2, 8 2, 8, 26 2, 8, 26, 27 2, 8, 26-28 2, 8, 26-29

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Guide Freed PU Spring Guide Feed Pick up Assembly General Motor (Mech.) Shaft Lead Screw

1Screw

4-4 4-4 4-4

3Screws

Bottom

4-4 4-4

Motor Assembly PU Freed 2 Locking Tabs Base PU (Outsert) Base Assembly Main Holder Assembly Deck on 1 Locking Tab
Frame Assembly Up/Down

Bottom

4-4 4-4 4-5

Bottom

4-5 4-5 4-5 4-5

2 Locking Tabs

Rubber F Belt Loading GearPulley Gear Loading Gear Emergency Cam Loading Motor Assembly Loading 2 Screws 1 Locking Tab Bottom 1 Screw

4-5 4-5 4-5 4-5 4-5 4-5

1, 2, 8, 26-30 31

1, 2, 8, 26-31 32 Base Main

Note: When reassembling, perform the procedure in reverse order. The Bottom on Disassembly column of above Table indicates the part should be disassembled at the Bottom side.

DECK MECHANISM ASSEMBLY

DECK ASSEMBLY TRAY DISK (B) (L1) (L1) (L2)

EMERGENCY EJECT HOLE (L1) (L1) (C4) (C3) (C2) (C1) JUNCTION C.B (A) (A) (B) LEVER

(S1)

(S1) Fig-7

(S1)

(S1) BOTTOM SIDE VIEW Fig-9

8. Bracket Assembly Clamp (Fig-8)

BRACKET CLAMP PLATE CLAMP MAGNET CLAMP CLAMP LOWER (S2) (S2) (Fig-A) BRACKET CLAMP CLAMP ASSEMBLY DISK 1) Put the Deck Assembly on original position. (Top side) 2) Release 2 Screws (S2). 3) Lift up the Bracket Assembly Clamp.

(A)

8-1.

Clamp Assembly Disk

1) Place the Clamp Assembly Disk as Fig-(A). 2) Lift up the Clamp Assembly Disk in direction of arrow (A). 3) Separate the Clamp Assembly Disk from the Bracket Clamp. 8-1-1. Plate Clamp 1) Turn the Plate Clamp to counterclockwise direction and then lift up the Plate Clamp. 8-1-2. Magnet Clamp 8-1-3. Clamp Lower

8-2.
DECK ASSEMBLY

Bracket Clamp

9. Tray Disk (Fig-9)

1) Insert and push a Driver in the emergency eject hole (A) at the front side, or put the Driver on the Lever (B) of the Gear Emergency and pull the Lever (B) in direction of arrow (A) so that the Tray Disk is ejected about 1520mm. 2) Pull the Tray Disk until the moving is locked by the Locking Tab (L2). 3) Unlock the Locking tab (L2) in direction of arrow (B). 4) Separate the Tray Disk completely.

Fig-8

7. Junction C.B (Fig-7)

1) 2) 3) 4) Put the Deck Assembly face down. (Bottom side) Release 4 Screws (S1). Unlock 4 Locking tabs (L1). Lift up the Junction C.B a little to disconnect the Connector (C1). 5) Disconnect 3 Connectors (C2, C3, C4).

CABLE FLEXIBLE MOTOR ASSEMBLY PU FEED BASE PU (OUTSERT) (A)

SHAFT PU SUB

SHAFT PU MAIN Fig-(A)

PICK UP ASSEMBLY GENERAL (C5) (S3) SPRING GUIDE FEED (S4) SPRING SKEW BASE PU (OUTSERT) (A) RUBBER R (L4)

P.C. BOARD RED BLACK

GUIDE FEED PU

MOTOR ASSEMBLY PU FEED

(L3) (A) MOTOR (MECH.) SHAFT LEAD SCREW

(S5) (S5) Fig-10

10. Base Assembly Feed (Fig-10)

1) Disconnect the Connector (C5) 2) Release the Screw (S3).

10-5-3. Pick Up Assembly General

10-6. Motor (mech.)

1) Release the 3 Screws (S5) at bottom side. 2) Push down the Motor (Mech.) and separate from the Base PU (Outsert).

10-1. Rubber R 10-2. Spring Skew

1) Press the (A) position of the Spring Skew and unlock the Spring Skew locking.

10-7. Shaft Lead Screw

1) Push the Shaft Lead Screw in direction on arrow (A) a little and lift up the Shaft Lead Screw.

10-3. Shaft PU Main 10-4. Shaft PU SUB

Note: When reassembling, be careful not to change the Shaft PU Main (Long) and the Shaft PU Sub (Short).

10-8. Motor Assembly PU Feed.

1) Unlock the Locking tab (L3) and lift up the P.C.Board. 2) Unlock two Locking Tabs (L4) and push down the Motor Assembly PU Feed. 3) Separate the Motor Assembly PU Feed from the Base PU (Outsert). Note: When reassembling, place the Motor Assembly PU Feed as Fig-(A) and insert the Cable Flexible to the Hole (A) of the Base PU (Outsert). (See Fig-(A))

10-5. Mechanism Assembly PU Unit

10-5-1. Guide Feed PU 1) Release the Screw (S4) and separate the Guide Feed PU from the Pick up Assembly General. 10-5-2. Spring Guide Feed

10-9. Motor (mech.)

9

(R2)
Fig-(B)

(R1)

FRAME ASSEMBLY UP/DOWN RUBBER F

Fig-(D) GEAR EMERGENCY (S6) GEAR PULLY GEAR LOADING CAM LOADING (L6) BASE MAIN (R2) (R1)

(S7) (L7) (L6) HOLDER ASSEMBLY DECK ON

(L5) Fig-(C) BELT LOADING MOTOR ASSEMBLY LOADING CONNECTOR(2 PIN) (L5)

(A) Fig-(E) BOTTOM SIDE VIEW Fig-(A)

Fig-11

11. Base Assembly Main (Fig-11)

11-1. Holder Assembly Deck On
1) Push the Locking tabs (L5) at bottom side of the Holder Assembly Deck On in direction of arrow (A) and separate to bottom side. (See Fig-(A))

11-6. Gear Loading 11-7. Gear Emergency

Note: When reassembling, confirm that the Hole (A) of the Cam Loading is aligned to the Hole (B) of the Gear Emergency as Fig-(C). For this alignment, place the Gear Emergency and Cam Loading as Fig-(D), and then move the Gear Emergency in direction of arrow (B) until these two gears are aligned as Fig-(C).

11-2. Frame Assembly Up/Down.

1) Push the two Locking tabs (L6) and lift up the Frame Assembly Up/Down. Note: When reassembling, insert the Lever (R1) of the Frame Assembly Up/Down to the Groove (R2) of the Gear Emergency and lock the two Locking Tabs (L6). (See Fig-(B))

11-8. Cam Loading 11-9. Motor Assembly Loading

1) Release two Screws (S7). 2) Unlock the Locking tab (L7) and separate the Motor Assembly Loading to bottom side. Note: When reassembling, confirm that the Connector (2 Pin) is aligned as Fig-(E)

11-3. Rubber F 11-4. Belt Loading 11-5. Gear Pulley

1) Release the Screw (S6) and lift up the Gear Pulley.

11-10. Base Main

10

ELECTRICAL MAIN PARTS LIST

REF. NO IC

PART NO.

KANRI NO.

DESCRIPTION

REF. NO C204 C207 C213 C214 C215 C216 C218 C219 C220 C224 C226 C230 C302 C310 C311 C708 C709 C712 C713 C714 C718 CE201 CE202 CE203 CE205 CE206 CE210 CE211 CE221 CE223 CE228 CE609 CE610 CE710 X101 X301

SI-AM2-980-01A SI-AL2-402-10E SI-AL4-981-92B SI-RH5-983-20A SI-RH6-859-20A SI-RW8-610-00A SI-HY2-580-10A SI-GS7-142-60E SI-HI6-417-03B SI-SS4-310-00A SI-SS7-542-00A SI-SS7-808-00H SI-KE3-930-00G SI-KE4-310-00A 87-001-196-010 SI-SS4-161-02F SI-SA8-661-12C SI-JR3-414-00C SI-JR4-580-00B SI-BB1-716-00A SI-BB1-700-00A SI-SH2-050-00A SI-SH3-130-00A SI-TI7-437-40K SI-SK6-153-00A SI-TO1-254-00B SI-TO1-254-00A SI-TO7-040-00F SI-MQ5-316-25A SI-CU3-000-00A SI-GS7-216-16C TRANSISTOR

IC,AM29F800B-120EC IC,AT24C02N-10SC-2.7 IC,AT49F8192A-90TC IC,BA5983FP-E2 IC,BA6859AFP-E2 IC,BT861 IC,GDC25D801AA IC,GM71C4260CJ-60 IC,HD6417034AFI20 IC,KA431AZ IC,KA7542Z IC,KA78R08 4P IC,KIA393F-EL IC,KIA431 3P IC,KIA7042P IC,KM4161020CT-G7 IC,LC866112B-5N21 IC,NJM3414AM-TE1,3K/REEL IC,NJM4580M IC,PCM1716E 28P IC,PLL1700E 20P IC,PQ20WZ5U 20WZ51 IC,PQ3DZ13U IC,SN74AHC374PWLE IC,STR-G6153T 5P IC,TA1254AF IC,TA1254F IC,TC7W04FU IC,V53C16256HK50 IC,ZIVA3-PE0 ICGM72V161621ET-7

KANRI DESCRIPTION NO. SC-H71-06C-611 C-CAP,10UF-6.3V SC-H71-06C-611 C-CAP,10UF-6.3V SC-H71-06C-611 C-CAP,10UF-6.3V SC-H71-06C-611 C-CAP,10UF-6.3V SC-H71-06C-611 C-CAP,10UF-6.3V SC-H71-06C-611 SC-H71-06C-611 SC-H71-06C-611 SC-H81-07C-621 SC-H71-06C-611 SC-H71-06C-611 SC-H71-06C-611 SC-H81-07C-691 SC-H71-06F-621 SC-H71-06F-621 SC-H71-06C-611 SC-H82-27D-611 SC-H71-06C-611 SC-H71-06C-611 SC-H71-06F-621 SC-H71-06C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H84-76C-611 SC-H81-07F-611 SC-H81-07F-611 SC-H84-76C-611 S2-12H-B20-02A S2-02R-427-01G C-CAP,10UF-6.3V C-CAP,10UF-6.3V C-CAP,10UF-6.3V C-CAP,100UF-6.3V C-CAP,10UF-6.3V C-CAP,10UF-6.3V C-CAP,10UF-6.3V C-CAP,100UF-6.3V C-CAP,10UF-16V C-CAP,10UF-16V C-CAP,10UF-6.3V C-CAP,220UF-10V C-CAP,10UF-6.3V C-CAP,10UF-6.3V C-CAP,10UF-16V C-CAP,10UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,47UF-6.3V C-CAP,100UF-16V C-CAP,100UF-16V C-CAP,47UF-6.3V CCR20.0MC6T TDK 20000000H C-RESO 27MHZ 20P

PART NO.

ST-R10-500-9AD ST-R10-300-9AE ST-R10-500-9AB ST-R11-510-0AA ST-R12-670-9AC ST-R15-040-9BF ST-R15-050-9AD ST-R31-980-9AC ST-R13-040-9BA ST-R10-000-9CB ST-R10-000-9BM 87-070-334-070 SM-TZ6-8CT-000 DIODE SD-D19-300-9AB ST-R10-370-9BB ST-R10-300-9AA ST-R38-750-9AC SD-R15-402-0BA 87-020-465-080 SD-R10-451-0AA SD-D01-000-9CA SD-R18-020-9AA 87-A40-284-080 SD-D01-000-9AC 83-NEG-677-080 SD-R49-500-9AA 87-017-352-010 87-070-173-010 MAIN C.B

TR,KRA105M TR,KRC103M TR,KRC105M TR,KSB1151-Y TR,KTA1267-GR TR,KTA1504S-Y TR,KTA1505S-Y TR,KTC3198-TP-BL TR,KTD1304S TR,UMX1N TR,UMZ1N 3K ZENER,MTZ10B ZENER,MTZ6.8C

JUNCTION C.B CE450 CE451 CE452 CE453 R451 R452 TIMER C.B C500 C502 C506 C507 C512 C513 DIG501 LED501 RC501 SW501 SW502 SW503 SW503 SW504 SW505 SW506 SW507 SW510 SW511 SW512 SW513 SC-E22-73D-638 SC-E10-63F-638 SC-E47-63J-638 SC-E10-63F-638 87-010-140-080 87-010-140-080 S3-02H-V00-1D0 SD-L32-531-9AA S7-12R-083-8GA S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 S5-562-19B-000 CAP,E CAP,E CAP,E CAP,E CAP,E 220-10V 10-16V 47UF-35V 10-16V 47-16V 87-010-140-080 87-010-140-080 87-010-140-080 87-010-140-080 SR-D01-01H-633 SR-D01-01H-633 CAP,E 47-16V CAP,E 47-16V CAP,E 47-16V CAP,E 47-16V RES,1-1/2W RES,1-1/2W

C-DIODE,KDS193 C-TR,2SA1037K-Q C-TR,KRC103S-T1 C-TR,KTC3875S-GR-T1 DIODE,1N5402 DIODE,1SS133 DIODE,B10A45V1 DIODE,EG01CW DIODE,ERA18-02KFRB DIODE,ERA22-10 DIODE,EU01W DIODE,MTZ5.6B DIODE,RB495D DIODE,RU3YXLF-C1 100V2 DIODE,S1WBA60

CAP,E 47-16V 7-BT-259GK DH LED SPR325MVWT31(GRN) TSOP1238UQ1 TEMIC 8MM 37 RC SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B SW,SKHV10910B

11

REF. NO SW514 X501 JACK C.B CV1 CV2 CV3 CV6 CV8 CV10 CV12 CV13 CV14 CV15 CV16 CV21 JACK1 JACK2 JACK3 JACK4 JACK8 KEY C.B SW508 POWER C.B C900 C901 C902 C902 C905

KANRI DESCRIPTION NO. S5-562-19B-000 SW,SKHV10910B S6-160-20P-000 CSA6.00MGU MURATA 6MHZ

PART NO.

REF. NO C906 C907 C913 C916 C918 C919 C921 C923 C924 C925 C926 C927 C929 C932 C934 !F901 !IC903 !L901 !L901 L902 L903 R901 R902 R911 R922 !T901 !V901

KANRI DESCRIPTION NO. S6-240-87B-000 CAP,100P-1KV SA-1B3-0KH-2M0 CAP,220PF-400V 87-012-379-010 CAP,3300PF-400V 87-010-387-010 CAP,E 470UF-25V KME 87-010-112-080 CAP,E 100-16V 87-010-408-040 SC-E22-76F-638 87-010-237-910 87-010-237-910 87-010-375-080 87-010-408-040 87-015-684-080 87-010-112-080 SC-E47-7CD-638 SC-E47-7CD-638 S5-850-11T-000 S6-570-62B-000 S6-161-45H-000 S6-161-45J-000 S6-330-88G-000 S6-330-88D-000 S6-140-07R-000 SR-S10-03K-619 SR-S05-10K-619 SR-S12-00J-619 S6-420-23T-000 S6-560-04F-000 CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E 47UF-50V 220UF-16V 1000UF-16V 1000UF-16V 330-10V 47UF-50V 47-16V 100-16V 470UF-10V 470UF-10V

PART NO.

87-010-060-080 SC-E22-76F-638 87-010-237-910 87-015-681-080 87-010-140-080 SC-E10-86F-630 87-015-681-080 87-015-684-080 87-015-681-080 87-015-681-080 87-016-577-080 87-010-060-080 S6-12H-K26-02A S5-720-75A-000 S6-12R-IH0-05D S6-12R-BH0-08A

CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E CAP,E

100-16V 220UF-16V 1000UF-16V 10-16V 47-16V 1000-16V 10-16V 47-16V 10-16V 10-16V

CAP,E 470UF-16V CAP,E 100-16V TOTX178 TOSHIBA AN/DIP BJP-202L BAEEN BLACK JACK,PPJ6031J YKF51-5506 JALCO HORIZONT4P

FUSE,1600MA 250V SENSOR PC123Y FILTER SHT LFS2020V4-04350 FL BUJEON V-04350 COIL,CHOCK TP 5MM COIL,20UH RES,2.7-2W RES,100K-2W RES,0.51-2W RES,M/F 120-1W PT,SHT-023T/KSE-023T SVR681D10A SAMYANG 680V

S5-562-19B-000

SW,SKHV10910B

87-010-408-040 S6-240-88B-000 S6-240-88B-000 S6-240-88F-000 87-016-375-010

CAP,E 47UF-50V CAP,0.1UF-250V CAP,0.1UF-250V CAP,PCX2 275V 0.1UF,M CAP,0.01UF-630V

Regarding connectors, they are not stocked as they are not the initial order items. The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE

Chip Resistor Part Coding

8 8
A
Resistor Code Value of resistor Chip resistor
Dimensions (mm)

Figure

Wattage 1/16W 1/16W 1/10W 1/8W

Type 1005 1608 2125 3216

Tolerance 5% 5% 5% 5%

Symbol CJ CJ CJ CJ

Form
L W

L 1.0
t

W 0.5 0.8 1.25 1.6

t 0.35 0.45 0.45 0.55

:A Resistor Code : A
104 108 118 128

1.6 2 3.2

TRANSISTOR ILLUSTRATION C2 C B ECB KRA105M KRC105M KRC103M ECB KSB1151 E 2SA1037K KTC3875S KTA1504S KTC4419 KTA1505S KTD1304S KTC3198
12

B1 E1

BCE KSE13005F

E2 B2 C1 UMX1N UMZ1N

DISC

DVD_LDQM, DVD_SD_CS1
RFRP, RFCen, TE, Vref

DVD_MA[0:11] DVD_MD[0:15]

Comp. DRAM 256K x 16bit

DVD : A, B, C, D DVD : RF CD : A, B, E, F
IC201 TA1254F RF SIGNAL PROCESSOR

IC307 GM72V1621 1M x 16bit SDRAM

DVD_SD_CAS, DVD_SD_RAS DVD_SD_CLK DVD_MWE

SPINDLE MOTOR

M
ICADDR[0:8]
IC306 GM72V1621 1M X 16bit SDRAM
DVD_SD_CS0, DVD_UDQM

PICK UP

FE, TE, RFRP, SBADD, DVD/CD RF TEBAL, FEBAL, DPOCTL, EQF, EQB

LOADING MOTOR

spindle

MON, SPINDLE_DRV
DVD_DATA[0:7] SDCLKI, ZISENB REQZI 33.8688MHz DA_DATA, DA_LRCK, DA_BCK DA_XCK

M
FDO,TDO, FMO

Loading

BLOCK DIAGRAM-1 (OVERALL)

OPEN S/W

CLOSE S/W

LIMIT S/W

DECK MECHANISM

IC400 BA6859FP SPINDLE MOTOR DRIVER IC401 BA5983 POWER DRIVER

IC206 DVDSP-3301 CD/DVD DSP DVD SERVO

-22.5V

LOADING DRIVE

SPINDLE_FG, SLD_FG

ICDATA[00:15]

focus, tracking sled

SENS, FOK, SLD_FG, MSDAT0,DEFECT,DSP_SENSE, SQSO, SQCK, SCOR, AO[0:5] XLAT, S_CLK, S_DATA, DO[0:7]

IC301 ZiVA-3 MPEG A/V Decoder

AC 100 ~240V, 50 ~60Hz

POWER BOARD IC108 SH7034

POWER CONTROL
S_CLK, S_DATA, DPLL_L IIC_DATA, IIC_CLK

+5VD

+5VU

AGND,GND,UGND

IC308 PLL1700 CLOCK GENERATROR

27MHz

VDATA[0:7]

Hsync

Vsync

KEY INPUT
AUDIO OUT

Composite

13
D[00:07] A[00:02]

-27V

-21.8V

+9V

+5VA

27MHz X-TAL
DA_DATA, DA_LRCK, DA_BCK

IC800/IC801 BT865A/861A NTSC/PAL Encoder

Component

Composite, Y, C

RXDO/TXDO/SCKO F_Reg/M_Reg/M_Reset/MD_SW
REMOCON RECEIVER

DRAM

FL DISPLAY

IC500 LC866112

DAC_L0, S_CLK S_DATA

L R
FLASH MEMORY AMP FILTER FILTER

IC703/IC601~603 PCM176x4 AUDIO DAC

Pr

Pb

VIDEO OUT

F+ FRECTIFIER(FLD) -24V

BLOCK DIAGRAM-2 (POWER)

RECTIFIER(14V)

LPF

12V

TRANS

RECTIFIER RECTIFIER(10V) LPF

REG(8V)

8V

Q901 KTC4419 SWITCHING IC

14

RECTIFIER(5.2V)

LPF

D5V A5V

LINE FILTER FEED B.

U5V

PWR ON/OFF

AC100V~240V

RFRP, RFCen, 4 TE, Vref

IC204 comp.
RFZ_HOLD 3 FE,TE,RFRP,SBADD 4 3 SQSO, SQCK, SCOR XLAT,S_CLK, S_DATA 5 SENS, FOK, SLD_FG, MSDATO, DEFECT, DSP_SENSE

2 MIRR,TZC

DVD : A,B,C,D

PICK UP
DVD/CD RF 8 4 8 5 TEBAL, FEBAL, DPOCTL, EQF, EQB

DVD : RF

CD : A, B, E,F

UCOM I/F

DO[0:7] AO[0:5] ZO[0:7]

BLOCK DIAGRAM-3 (RF/DSP/SERVO)

IC201 TA1254AF RF Signal Processor

IC206 GDC25D801AA CD/DVD DSP

UCOM I/F MPEG I/F

16

ICADDR[0:8] 9

MON, SPINDLE_DRV

FDO, TDO, FMO

spindle

IC400 BA6859AFP Spindle Motor Driver

IC401 BA5983 Power Driver

IC205 DRAM 256K x 16bit

M/D

focus, tracking, loading, sled

SPINDLE_FG, SLD_FG loading drive

ICDATA[00:15]

15

MCK

MPEG I/F

UCOM I/F

MPEG_RST

BLOCK DIAGRAM-4 (AUDIO)

-com I/F (IC108)

L0 Lt

S_DATA

S_CLK

DAC_L0

16
R0

DA_LRCK

IC703 PCM1716 Audio DAC

IC704 LPF & Buffer NJM4580M OP AMP

Rt

TO JACK BOARD

DA_BCK

MPEG I/F (IC301)

DA_XCK

DA_DATA0

CH 1/2 : DOWNMIX Lt / Rt

DVD_DATA[0:7]

8 2 SPDIF DA_BCK

DA_DATA[0:3]

DSP I/F
SDCLK1,ZISENB REQZ1

AUDIO I/F(A/V)

BLOCK DIAGRAM-5 (MPEG)

Y HSYNC, VSYNC VDATA[0:7] 8 2 Pb Pr COMPOSITE1 Y/C

A[00:02]

3 8 DA_XCK MPEG_CLK

IC301 ZiVA-3 MPEG A/V Decoder

-COM I/F
D[00:07] MPEG_ERROR

IC801 BT861A NTSC/PAL Encoder

VIDEO I/F(A/V)

17
IIC_DATA, IIC_CLK DVD_SD_CS0, DVD_UDOM 2 16 DVD_LDOM, DVD_SD_CSI 12 2 DVD_MD[0:15] DVD_MA[0:11] 2 4 DVD_SD_CAS DVD_SD_RAS DVD_SD_CLK DVD_MWE S_CLK, S_DATA, DPLL_L

UCOM I/F

IC306 GM72V1621 1M x 16bit SDRAM

IC307 GM72V1621 1M x 16bit SDRAM

IC308 PLL1700 CLOCK GENERATROR

27MHz X-TAL

MCK

SERVO I/F

A/V I/F MPEG I/F

ECHO, MIC_A, DISC_A, S_DATA, S/CLK

BCA_CODE SPINDLE_FG, SLD_FG,

SERVO I/F
D[00:07], A[00:02], IIC_CLK, IIC_DATA, SCLK0, MPEG_INT D[00:07], A[00:05], E_SIN, E_CLK LOAD FR, F/R, LOCK, DEFECT, FOK, DSP_SENSE IIC_CLK, IIC_DATA

DSP I/F

2 8 D[00:07] SENS_MCOM, MICOM_WAIT 2 8

IC114 EEPROM AT24C02

MPEG_ERROR, DAC_L0, RF_LAT, /DSP_CS, /MPEG_CS, /PP_CS 6

IC102 74HC374

BLOCK DIAGRAM-6 (SYSTEM CONTROL)

/IOCSI, /WR 2

MPEG_CTL, E_DR, /ZOOM_RST, /S_XRST, XLAT, ACT_MUTE, V_MUTE, A_MUTE

18
8

IC101 XC9536 EXPANDER

A[19:21] D[00:04]

2 2

IC108 SH7034 MAIN -COM

EXP_W2, /PWR_CLT PWR_CTL, SENS, LIMIT_SW, MIC_ON, CLOSE_SW, OPEN_SW, MPEG_WAIT, ZIERR A[01:21] 21 16 D[00:15] 2

16 MICOM_RESET A[01:19] 19

D[00:15] A[01:09] 9

FRONT I/F

16

D[00:15]

IC106 FLASH MEMORY 512K x 16

IC107 DRAM 256K x 16

WIRING-1 (MAIN: COMPONENT SIDE)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
TO/FROM POWER C.B CON902

MAIN C.B
(COMPONENT SIDE)
2 1

TO/FROM JUNCTION C.B CN404

TO/FROM JUNCTION C.B CN402

20 19 1

26 25

10

E E E

C
1 2

TO/FROM TIMER C.B CN507

64 1

49 48 R801

16 R184 C128 14 15 17 32

33 5 1 8 5

TO/FROM JACK C.B CON06

22 1 2

R191

5 5 1 R787 R714 C227

1 CE711

21 R732 R729 R726 C715 R723 R721 C713

R727

1 C712 104 105 53 52

84 85

57 56 R399 R365 R366 R364 E

156 157

105 104

F
TO/FROM JACK C.B CON07

112 1 28

29 156 157 208 1

NOTE
Cxxx

14

15 21 1 40 R384 208 1 R385 53 52 R312 R309 R307 22

Lxxx Rxxx
20 21

C E B E

19

20

WIRING-2 (MAIN: CONDUCTOR SIDE)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

MAIN C.B
B

(CONDUCTOR SIDE)
20 11

10

6 1 8 1

4 3 5 4

50

50

25

24

48

1 1 40 25 33 26 25 26

E
1

44

34

11 12

23 22

3 1 4 6 E

1 4

8 8 5

5 11 10

C728

20 1 4

21

20

28

15

R777

R717 CE712

G NOTE
Cxxx

R188

14

R736

E E

R193 E

8 E

1 E E 80 1 61 60 E

C202

H
Lxxx Rxxx
1 4 8 5

E 20 21 40 41 R823 E

I
E B

C E

21

22

SCHEMATIC DIAGRAM-1 (MAIN 1/5)

23

24

SCHEMATIC DIAGRAM-2 (MAIN 2/5)

25

26

SCHEMATIC DIAGRAM-3 (MAIN 3/5)

27

28

SCHEMATIC DIAGRAM-4 (MAIN 4/5)

29

30

SCHEMATIC DIAGRAM-5 (MAIN 5/5)

31

32

SCHEMATIC DIAGRAM-6 (JACK)

AA+12V SCART1 (16:9) SCART2 (DVD/AV)

U (B) V (G)

COMPO1

R1

L1

QV01 KTA1267 CV16 470F /16V RV31 180 RV32 680 RV03 10K QV07 KTA1267 RV33 75 CV24 220F /16V CV12 10F RV04 2.2K

RV08 820 QV03 KRC103M

DV02 1SS133 QV02 KRC103M RV05 1.0K

JK08 SCART JACK A Rout A Lout GND GND

JACK08 EURO AV (TV)

FV06

BVD01 BEAD

BLUE CONTROL
FV07 BVD02 BEAD

GREEN
FV08

BVD03 BEAD

GND GND RED GND GND V.out GND

FV05

33

LV01 1H

34

WIRING-3 (JUNCTION/JACK)
1 2 3 4 5 6 7 8 9 10 11 12 13 14

JACK03 AUDIO OUT L

JACK04 S-VIDEO OUT 1 R VIDEO OUT 5

JACK08 EURO AV (TV)

DIGITAL OUT JACK01 JACK02 OPTICAL COAXIAL

10

15

20

JACK C.B
3 1

D
SW1 INSIDE LIMIT SW M1

M
SPINDLE MOTOR TO/FROM MAIN C.B CON201 TO/FROM MAIN C.B CON201 TO/FROM MAIN C.B CON801

JUNCTION C.B
M2 (SLED MOTOR)

TO/FROM MAIN C.B CON202

M3 (LOADING MOTOR)

M
F

NOTE I

OPEN/CLOSE SWITCH

J
PICK UP ASSY TO/FROM POWER C.B CON904

K 35 36

SCHEMATIC DIAGRAM-7 (JUNCTION)

37

38

WIRING-4 (TIMER/KEY/POWER)
1 2 3 4 5 6 7 8 9 10 11 12 13 14

K 39 40

SCHEMATIC DIAGRAM-8 (TIMER/KEY)

41

42

SCHEMATIC DIAGRAM-9 (POWER)

POWER C.B

T901

+8V REG.

C932 470/10V

A5V REG. 4 1

2
TO TIMER C.B CN503

INSULATOR POWER CONTROL

AC 200-240V 50Hz

43

44

TO JUNCTION C.B CN401

TO MAIN C.B CON999

WAVE FORM

IC201 Pin ( (LVL) SBADD IC201 Pin (FEO) Focus Error

VOLT/DIV: TIME/DIV: VOLT/DIV: TIME/DIV:

500mV 2mS 2.9V 2mS

IC206 Pin 88 (A OUT3) SLED Drive (FMO)

VOLT/DIV: 2.12V TIME/DIV: 10mS

IC201 Pin ) (TEO) Tracking Error

6
VOLT/DIV: 2.2V TIME/DIV: 2mS

IC201 Pin (FEO) Focus Error (In Focus search) IC206 Pin 83 (A OUT1) Focus Drive (FDO)

VOLT/DIV: TIME/DIV: VOLT/DIV: TIME/DIV:

200mV 100mS 2.14V 100mS

IC201 Pin ) (TEO) VBR Tracking Error

VOLT/DIV: 2.27V TIME/DIV: 500S

IC801 Pin #-^ (P0-P3) IC801 Pin (- (P4-P7) MPEG Data

Tek Stop : 1 00kS/s [ 3290 Acqs T ]

VOLT/DIV: 280mV TIME/DIV: 500S

Record Length

Fit to Screen OFF T

500 points in 10divs 1000 points in 20divs 2500 points in 50divs

M 500 s

Ch3

1.00V

CH1

280/mV

more 1 of 3

Time Base Main

Trigger Position 50%

Record Length 2500

Horiz Scale (/div)

Horiz Pos

FastFrame Setup

IC201 Pin (RFO)

VOLT/DIV: 0.5V TIME/DIV: 0.1S

45

IC801 Pin 57 (DACC) Composite

VOLT/DIV: 500mV TIME/DIV: 20S

IC801 Pin 71 (CLK IN) MPEG Clock

Tek Stop : 1 00kS/s [ 3290 Acqs T ]

VOLT/DIV: 280mV TIME/DIV: 500S

Edge Slope

Ch3

1.00V

M 500s

CH1

280/mV

Type <Edge>

Source Ch1

Coupling DC

Slope

Level 280mV

Mode & Holdoff

IC801 Pin 58 (DACB) Chrominance

VOLT/DIV: 500mV TIME/DIV: 20S

IC801 Pin (VSYNC) Vertical SYNC

Tek Stop : 10.0kS/s [ 13 Acqs T ]

VOLT/DIV: 280mV TIME/DIV: 5mS

Edge Slope

Ch3

1.00V

M 5 .00ms CH1

280/mV

Type <Edge>

Source Ch1

Coupling DC

Slope

Level 280mV

Mode & Holdoff

$
IC801 Pin Luminance
Tek Stop : 2.50MS/s

IC801 Pin (HSYNC)

Tek Stop : 2.50MS/s [ 7 Acqs T

59

(DACA)

VOLT/DIV: 500mV TIME/DIV: 20S

VOLT/DIV: 280mV TIME/DIV: 20S

] Edge Slope

4 Acqs [T ]

T 3

Ch3

1.00V

M 20.0s

CH1

280/mV

Type <Edge>
M20.0s

Source Ch1

Coupling DC

Slope

Level 280mV

Mode & Holdoff

Glitch Ch1

Ch3

500mV

2 Apr 1999 14:47:27

IC801 Pin IC801 Pin SDA/SCL

75 76

(SID) (SIC)

VOLT/DIV: 2.06V TIME/DIV: 25mS

IC801 Pin + (DACF) Component Pb

VOLT/DIV: 500mV TIME/DIV: 20S

46

IC801 Pin , (DACE) Component Pr

VOLT/DIV: 500mV TIME/DIV: 20S

&

IC801 Pin < (DACA) Component Y

VOLT/DIV: 500mV TIME/DIV: 20S

47

TROUBLE-SHOOTING
1. Power Circuit
Input Voltage: 120V It is possible to malfunction, if the unload condition is left for a long time when power is on. (More than Dummy load 100mA) A Primary side is abnormal when the fuse is short, secondary side is abnormal when the IC103 oscillates intermittently. The resistor value of both terminal is measured with DVM crossing each other to check the each element is normal or abnormal. (It is normal when the numerical value is different each other.)

START

Is F901 normal? Check the GND of C901 and IC901 Pin 3 with oscilloscope. NO When IC901 oscillating Does oscillate continuously when the CON903 is disconnected ? YES Secondary side is abnormal. Front Circuit
Board is abnormal

NO A primary side is abnormal.

Is voltage of BD901 140V? YES Are R907, D902, D903 and R902 normal? YES Are D901, R904, R905 and R906 normal? YES

NO

YES NO Is IC901 Pin 3 Is IC905 switching normally? normal? <Fig-3-1> YES YES In condition of DC140V. (Feedback is abnormal) NO Is CN903 Pin 3 5.2V? YES After connect CON903 Pin 1, 3 short. (A) Are R922, C927, R921 NO and R918 normal? Check or replace D908.

NO

NO

NO Is PC901 normal? YES

Are D908, D909, D907, D910, D906 and D905 normal? YES

NO

Are CON902 Pin 5, 6 and 9 5V? YES Is CON904 Pin 3 8V? YES Is CON902 Pin 3 12V? YES
Are CON903 Pin 5 -24V, Pin 7 -20V and Pin 8 -16V?

END

Replace Q908 and Q909. NO Is CON903 Pin 3 5.2V? YES NO

Replace defective parts.

Replace IC902. NO Check Q904 and ZD903.

Replace defective parts.

To (A).

NO IC901 Pin 3 Normal switching waveform on the stand-by mode at the AC110V

YES END

48

2. -COM Circuit
A. No Power

POWER ON

Power RED LED on?

NO

Refer to Front Part.

YES NO

Does Bar appear at FLD?

YES

Do all five Bars appear? NO

NO

Is CON107 connected normally?

YES

Reconnect it. Check power. (Refer to power) If power is normal NO

Does Logo appear on the screen? YES

NO

OK

Is CON107 Pin 6 normal? YES

Refer to Front Part

A
Is oscillation of X101 normal? YES Check short Are IC107 Pin $, and normal? YES NO Check short. OK YES Replace IC107 or IC108. Replace IC101. NO NO Check the oscillation NO

The waveform on A [00:21] and D [00:15] of IC108 normal?

YES

Are IC101 Pin 7, 8 normal?

Replace Main B/D.

END

49

B. Audio abnormal

C. Video abnormal

AUDIO ABNORMAL

VIDEO ABNORMAL

Check Audio jack. YES (If OK) Check PLL FC of MPEG part. YES (If OK) Refer to Audio part. YES (If OK) Refer to MPEG part. YES (If OK) Replace B/D.

Check Video jack. YES (If OK) Refer to Video part. YES (If OK) Refer to Encoder part. YES (If OK) Refer to MPEG part. YES (If OK) Replace B/D.

END

END

D. Open/Close abnormal

OPEN/CLOSE ABNORMAL

Check Front. YES (If OK) Check the connection of CON107. YES NO Check the connection of MD. Check IC101 Pin #, $. YES Refer to SERVO part. NO

Reconnect it.

YES

50

E. Picture abnormal
PICTURE ABNORMAL

Check the disc.

Refer to Servo part If OK Check PLL IC of MPEG part YES (If OK) Check DSP YES (If OK) Check MPEG YES (If OK) Replace B/D

END

F. Disc Error

DISC ERROR

Check Disc YES (If OK) Refer to Servo part YES (If OK) Replace B/D

END

51

3. MPEG Circuit

Power is on

Does aiwa Logo appear on the screen? YES

Does the moving picture of the DVD Disc play on the screen normally?

NO

Check power & clock. YES

NO

Is MPEG data signal normal? YES

NO

Check CD/DVD DSP output signal. OK

YES

OK

Check MPEG Decoder input signal.

YES Is error signal normal?

NO

Check CD/DVD DSP output signal. OK

Check MPEG Decoder input signal.

Does the moving picture of the video CD play on the screen normally?

NO

Is MPEG data signal normal? YES

NO

Check CD/DVD DSP output signal. OK Check MPEG Decoder input signal.

YES

I OPTION If included VCD function.

Is Clock normal? YES

NO Check clock signal H

Does the audio sound output normally? YES END

NO

Does the audio sound output from MPEG decoder? YES

Check clock signal

52

4. Front Circuit (Digitron & key)

START

Power on.

LED ON? YES Is Digitron on normally? YES Do all the buttons work normally? YES

NO

Is oscillation of X501 normal? YES

NO

Check Power.

NO CD NO

Check waveform of IC500 Pin 6. YES

NO

Replace IC501.

Is waveform of IC500 Pin 76 normal? YES

NO

Check waveform of IC500 Pin #. YES

NO

Solder Key part.

Check waveform of IC500 Pin #. YES

NO

Replace IC500.

Solder defective parts again

Check waveform of Q500 Pin 2. YES

NO

Replace Q500.

Check and replace R516, R507, R506, R500, R505, R504, R512 and R503.

Replace LED501.

Does remote control work normally? YES

NO

Does pulse waveform of RE500 Pin 3 appear? YES Is IC500 Pin connected to RE500 Pin 3? YES

NO

Is RE500 Pin 2 5V? YES

NO Solder defective parts

Replace RE500 YES

Complete repairing Front B/D.

Replace IC500. YES

Re-solder. YES Recheck

53

5. RF/Servo Circuit
A.

CHECK POINT (General)

Does signal goes High to IC206 Pin 194 when the power is on?

NO

YES

Does signal pulse input to IC206 Pin when the power is on?

58

59

NO

Check 2.-COM Part.

YES

Does TTL pulse output to IC206 Pin 140 , 142 ? YES

NO

Does 33.8688MHz clock input to IC206 Pin 63 ? YES

NO

Replace X301 or IC308 (30MHz clock defect)

Replace IC206 (IC206 soldering or IC defect).

Is IC206 Pin
83, 84 , 88 , 89

voltage about 2.2V? YES

NO

Replace IC700 (IC700 soldering or IC defect).

END

54

B.

No disc

Power on

Check loading Part.

Does tray open or close? YES

NO

Push Pick-up to inner track to the end by hand.

Does CON202 Pin & change high to low? YES

Pressing the open/close key repeatedly, check the voltage of CON202 Pin 9 change 0V to 5V

NO

DECK assembly is defective. (Limit sw)

NO

check -COM Part.

YES Junction Board

Does the voltage change at IC401 Pin %, ^ more than 2V on the basis of 4.5V?

NO

Replace IC401.

YES

Fig-1. SLED Driver waveform

DECK assembly is defective.

Does the pick-up slide inner or outer track? YES

NO

Check SLED Driver output. IC206 Pin 88 IC401 Pins *, &.

IC206 Pin 88 no output : IC206 is defective IC401 Pin * no output : IC401 is defective

Fig-2. Focus Driver waveform NO Check Focus Driver output. IC206 Pin 83 no output : IC700 is defective (IC206 Pin 83 , IC401 Pins !, @) IC401 Pin 1, 2 no output : IC701 is defective

Does the pick-up lens move up and down? YES Slide the pick-up to inner track.

END

55

C.

DISC IN

OPEN/CLOSE

Fig-3. FOCUS ERROR waveform NO FOCUS ON? YES

Check the focus error moving the lens up and down. (IC201 Pin )

NO

Check IC201 Pin Check IC201 Pin

52 , 53 , 54 , 55 58 , 59 , 60 , 61

in DVD Mode in CD Mode

YES

IC201 no output: Pick-up is defective.

Does the TTL level change at IC206 Pin 78 and 132 moving the lens?

NO Replace IC206.

YES

Replace -COM or IC206.

NO Does the disc turn? YES

Check CON404 Pin 4, 6 Motor turn when the Pin 4 is less than 1.6V

Check IC206 and IC403 when the Pin 4 is abnormal

NO IC206 Pin 169 is High? YES -COM part is defective. Check 2.-COM Circuit. Check A

NO Is OK the track jump. YES

Does the signal pulse input at IC700 Pin , and ? YES

NO

NO Does the screen appear? YES

Video Par is defective. Check 5.MPEG Circuit. Check 7.OSD/Video Circuit.

Replace IC700.

END

56

D.

CHECK A Fig-5. RF waveform NO Check RF Eye-Pattern. RF: 1.0-2.1V (IC201 Pin ) YES Check IC201 Pin Check IC201 Pin
52 , 53 , 54 , 55 58 , 59 , 60 , 61

in DVD Mode. in CD Mode.

No signal: Pick-up is defective

NO Is the eye-pattern vivid? YES

Does the sawtooth waveform emit at IC201 Pin )? YES

NO

Does the 1.6V emit? YES

NO Replace IC201.

Replace IC206.

Check IC206 Pin

84 .

No signal at IC206: IC206 is defective

Check IC206 Pin 162 Check the clock at the IC206 Pin , .

Both are normal: IC206 is defective

END

57

LCD DISPLAY

58

IC DESCRIPTION IC, BT861

Pin No. Pin Name I/O Description Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A 1-6 VID2-7 I higher index corresponds to a greater bit significance. Data on the VID port is latched by rising edge of VIDCLK. (Connected to GND.) 7 8 9 VDD GND VIDCLK I Digital power. Digital ground. 2x pixel clock for secondary video input port. Synchronization circuitry exists for this port to lock it to the primary video port. (Connected to GND.) Video data valid qualifier. A logical 1 indicates data on VID [7:0] is valid data. The 10 VIDVALID I sense of this signal is controlled by the VIDVALIDI bit of register 0x1C. (Connected to GND.) 11 VIDVACT I Vertical active display region. The sense of this signal is controlled by the VIDVACTI bit of register 0x1C. (Connected to GND.) Horizontal active pixel signal. A logical 1 indicates data on VID [7:0] is in the 12 VIDHACT I horizontal display region. The sense of this signal is controlled by the VIDHACTI bit of register 0x1C. (Connected to GND.) Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher 13-16 P0-P3 I index corresponds to a greater bit significance. (1) Data is latched on the rising edge of the system clock. 17 18 GND VDDMAX Digital ground. Refer to the PC Board Considerations section of this This pin must be tied to the maximum digital input value. Use 3.3 V if only 3.3 V inputs are used, and 5 V if 5 V inputs are used. Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher 19-22 P4-P7 I index corresponds to a greater bit significance. (1) Data is latched on the rising edge of the system clock. Composite blanking control input (TTL compatible). BLANK is registered on the 23 BLANK I rising edge of the system clock. The P [7:0] inputs are ignored while BLANK is a logical 0. The sense of this signal is controlled by the BLANKI bit of register 0x19. Vertical sync input/output (TTL compatible). As an output (master mode operation), 24 VSYNC I/O VSYNC is output following the rising edge of the system clock. As an input (slave mode operation), VSYNC is registered on the rising edge of the system clock. The sense of this signal is controlled by the VSYNCI bit of register 0x19. Horizontal sync input/output (TTL compatible). As an output (master mode 25 HSYNC I/O operation), HSYNC is output following the rising edge of the system clock. As an input (slave mode operation), HSYNC is registered on the rising edge of the system clock. The sense of this signal is controlled by the HSYNCI bit of register 0x19. Field control output (TTL compatible). FIELD transitions after the rising edge of the system clock, two clock cycles following falling HSYNC. The sense of this signal is 26 FIELD O controlled by the FIELDI bit of register 0x19. The state of this pin at power-up determines the default state of the PCLK_SEL register. If not loaded, this pin will be pulled low with an internal pull-down resistor. 27 28 GND VDD Digital ground. Digital power.

59

Pin No.

Pin Name

I/O

Description Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video

29, 30

ALPHA0, 1

and graphic overlay data. Signals are latched using the system clock. (Connected to GND.)

31-36 37 38 39, 40 41 42 43 44 45 46

OSD0-5 GND VDD OSD6 ,7 AGND DACF DACE DACD VBIAS2 VAA

I I O O O

Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format. Signals are latched using the system clock. (Connected to GND.) Digital ground. Digital power. Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format. Signals are latched using the system clock. (Connected to GND.) Analog ground. Component chrominance U channel, component blue, or composite video. Component chrominance V channel, component green, or composite video. Component luminance, component red, or optional luma-delayed composite video. AGND; the capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Analog power. This pin to VAA. The capacitor must be as close to the device as possible to keep lead

47

COMP2

lengths to an absolute minimum. COMP1 is used with DACs A/B/C and COMP2 is used with DACs D/E/F. Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

48

FSADJ2

pins and AGND controls the full-scale output current on the analog outputs. For standard operation, use the nominal values shown under Recommended Operating Conditions. FSADJ2 controls DACs D/E/F.

49 50 51 52

VREF N/C AGND VAA

Voltage reference pin. Not used. Analog ground. Analog power. Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

53

FSADJ1

pins and AGND controls the full-scale output current on the analog outputs. For standard operation, use the nominal values shown under Recommended Operating Conditions. FSADJ1 controls DACs A/B/C.

54 55 56 57 58 59 60 61

COMP1 VAA VBIAS1 DACC DACB DACA AGND GND

O O O O

Compensation pin. Analog power. DAC bias voltage. Composite video. Modulated chrominance video signal or optional luma-delayed composite video. Luminance video or optional composite video. Analog ground. Digital ground. Alternate slave address input (TTL compatible). A logical 1 corresponds to write

62

ALTADDR

address of 0x88 and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A and a read address of 0x8B. See the Serial Programming Interface section for more detail. (Connected to GND.) 60

Pin No.

Pin Name

I/O

Description Reset control input (TTL compatible). Setting to zero resets both video timing

63

RESET

(horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and the serial control interface, and resets the registers. RESET must be a logical 1 for normal operation.

64 65 66 67 68 69 70 71

VDD GND PGND XTI XTO VPLL CLKO CLKIN

I O O I

Digital power. Refer to the PC Board Considerations section of this Digital ground. Dedicated ground for PLL. Crystal input for genlock PLL. (Not used.) Crystal output for genlock PLL. (Not used.) Dedicated power supply for PLL. (Connected to VDD.) 2x pixel clock for the primary video port. Generated by PLL or pass-through from CLKIN pin. (Not used.) 2x pixel clock input (TTL compatible). Field indicator for video input port. A logical 1 indicates data is from an odd field. The

72

VIDFIELD

sense of this signal is controlled by the VIDFIELDI bit of register 0x1C. (Connected to GND.)

73 74 75 76 77 78

TTXREQ TTXDAT SID SIC GND VDD

O I I/O I

Teletext request output (TTL compatible). (Connected to VDD.) Teletext bit stream input (TTL compatible). (Connected to GND.) Serial interface data input/output (TTL compatible). Data is written to and read from the device via this serial bus. Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz. Digital ground. Digital power. Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A

79, 80

VID0, 1

higher index corresponds to a greater bit significance. Data on the VID port is latched by rising edge of VIDCLK. (Connected to GND.)

61

IC, CL61330
Pin No. 1 Pin Name P100 I/O I/O Programmable I/O pins. 8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via 2-4 HDATA0-2 I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA [7:0]. 5 VDD_3.3 3.3-V supply voltage for I/O signals. 8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via 6 HDATA3 I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA [7:0]. 7 VSS Ground for core logic and I/O signals. 8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via 8-11 HDATA4-7 I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal egisters and local SDRAM/ROM via HDATA [7:0]. 12 VDD_2.5 2.5-V supply voltage for core logic. Hardware reset. An external device asserts RESET (activeLOW) to execute a decoder 13 RESET I hardware reset. To ensure proper initialization after power is stable, assert RESET for at least 20 ms. 14 VSS Ground for core logic and I/O signals. Transfer not complete/data acknowledge. Active LOW to indicate host initiated 15 /WAIT O transfer is not complete. WAIT is asserted after the falling edge of CS and reassertedwhendecoderis ready to complete transfer cycle. Open drain signal, must be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate. 16 17 18 19 20 21-26 27 28 29 30 31-35 36 37 38 39 40 41 42 43-46 HDATA8-13 VDD HDATA14 VSS HDATA15 HADDR12-16 VDD HADDR17 VSS HADDR18 VDD HADDR19 VSS HADDR20-23 I/O I/O I/O I/O I/O I/O I/O I/O Programmable I/O pins. Input mode after reset. 3.3-V supply voltage for I/O signals. Programmable I/O pins. Input mode after reset. Ground for core logic and I/O signals. Programmable I/O pins. Input mode after reset. Programmable I/O pins. Output mode after reset. 3.3-V supply voltage for I/O signals. Programmable I/O pins. Output mode after reset. Ground for core logic and I/O signals. Programmable I/O pins. Output mode after reset. 2.5-V supply voltage for core logic. Programmable I/O pins. Output mode after reset. Ground for core logic and I/O signals. Programmable I/O pins. Output mode after reset. /INT VDD /AMWE VSS O Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven high for 10 ns before tristate. 3.3-V supply voltage for I/O signals. Not used. Ground for core logic and I/O signals. Description

62

Pin No. 47 48 49 50, 51 52 53, 54 55 56 57 58-60 61 62 63 64 65 66 67 68 69 70 71 72-74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Pin Name VDD BEO VSS NC P101 MDATA15, 0 VDD MDATA14 VSS MDATA1, 13, 2 VDD_3.3 MDATA12 VSS MDATA3 VDD MDATA11 VSS MDATA4 VDD MDATA10 VSS MDATA5, 9, 6 VDD MDATA8 VSS MDATA7 LDQM UDQM VDD /MWE VSS SD-CLK /SD-CAS /SD-RAS VDD SD-CS1 VSS SD-CS0 VDD NC

I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O 3.3-V supply voltage for I/O signals.

Description

Programmable I/O pins. Output mode after reset. Ground for core logic and I/O signals. No Connection Programmable I/O pins. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 2.5-V supply voltage for core logic. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. SDRAM LDQM. SDRAM UDQM. 3.3-V supply voltage for I/O signals. SDRAM write enable. Decoder asserts active LOW to request a write operation to the SDRAM array. Ground for core logic and I/O signals. SDRAM system clock. Active LOW SDRAM column address. Active LOW SDRAM row address. 3.3-V supply voltage for I/O signals. Active LOW SDRAM bank select. Ground for core logic and I/O signals. Active LOW SDRAM bank select. 2.5-V supply voltage for core logic. No Connection.

63

Pin No. 93 94 95 96 97 98-100 101 102 103 104-106 107 108 109 110-112 113 114 115 116 117 118 119 120-122 123 124 125 126, 127 128 129 130 131, 132 133 134, 135 136 137 138 139, 140 141

Pin Name VSS NC VDD MADDR9 VSS MADDR1, 8, 10 VDD MADDR7 VSS MADDR0, 8, 1 VDD MADDR5 VSS MADDR2, 4, 3 VDD MADDR12 VSS MADDR13 VDD MADDR14 VSS MADDR15-17 VDD MADDR18 VSS MADDR19, 20 /ROM_CS P102 NC VDD P103 VDD VSS VDD P104 VDD P105

I/O O O O O O O O O O O O O O O I/O O I/O I/O I/O

Description Ground for core logic and I/O signals. No Connection 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 2.5-V supply voltage for core logic. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. Memory address. (Not used.) Ground for core logic and I/O signals. Memory address. (Not used.) Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Programmable I/O pins. No Connection. 3.3-V supply voltage for I/O signals. Programmable I/O pins. 3.3-V supply voltage for I/O signals. Ground for core logic and I/O signals. 3.3-V supply voltage for I/O signals. Programmable I/O pins. 3.3-V supply voltage for I/O signals. Programmable I/O pins. Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

142, 143

VDATA0, 1

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

144

VDD

2.5-V supply voltage for core logic.

64

Pin No.

Pin Name

I/O

Description Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

145

VDATA2

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

146 147

VSS P105

I/O

Ground for core logic and I/O signals. Programmable I/O pins. Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

148

VDATA3

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

149

VDD

3.3-V supply voltage for I/O signals. Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

150

VDATA4

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

151

VSS

Ground for core logic and I/O signals. Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

152

VDATA5

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

153

P107

I/O

Programmable I/O pins. Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the

154, 155

VDATA6, 7

decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.

156 157

P108 /HSYNC

I/O I/O

Programmable I/O pins. Horizontal sync. The decoder begins out putting pixel data for a new horizontal line after the falling (active) edge of HSYNC. Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the

158

/VSYNC

I/O

first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical synchronization or top/bottom field notification from an external source. (VSYNC HIGH = bottom fie

159 160 161 162 163-165 166

DA-IEC VDD DA-DATA0 VSS DA-DATA1-3 DA-LRCK

O O O O

Bitstream data in IEC-1937 or PCM data out in IEC-958 format. 3.3-V supply voltage for I/O signals. PCM data out, eight channels. Serial audio samples relative to DA-BCK clock. Ground for core logic and I/O signals. PCM data out, eight channels. Serial audio samples relative to DA-BCK clock. PCM left-right clock. Identifies the channel for each audio sample. the polarity is programmable.

167 168 169 170 171 172

DA-BCK VDD DA-XCK VSS DAI-DATA DAI-LRCK

O I/O I I

PCM bit clock. Divided by 8 from DA-XCK, DA-BCK can be either 48 or 32 times the sampling clock. 2.5-V supply voltage for core logic. Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can be either 384 or 256 times the sampling frequency. Ground for core logic and I/O signals. PCM input data, two channels. Serial audio samples relative to DAI-BCK clock. PCM input left-right clock.

65

Pin No. 173 174 175 176 177 178 179

Pin Name DAI-BCK P109 CLKSEL A_VDD VCLK SYSCLK A-VSS DVD-DATA0/CD-

I/O I I/O I I I PCM input bit clock. Programmable I/O pins.

Description

Clock Select: Internal = VDD, External = VSS 3.3-V analog supply voltage. Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz. System clock. Decoderrequires an external 27MHz TTL oscillator. Drive with the same 27-MHz as VCK. Analog ground for PLL. Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. ERROR

180

DATA VDD DVD-DATA1/CDLRCK

200 I Error in input data. If ERROR signal is not available from the DSP it must be grounded.

181 182 183 184

I I

3.3-V supply voltage for I/O signals. Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH). This pin is shared with DVD compressed data DVD-DATA1. Ground for core logic and I/O signals. CD bit clock. Decoder acceptmultipleBCKrates. This pin is shared with DVD compressed data DVD-DATA2. Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture

VSS DVD-DATA2/CDBCK DVD-DATA3/CD-

185

C2PO

on-screen until the next valid picture is decoded. This pin is shared with DVD compressed data DVD-DATA3. DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words, it must write the DVD-DATA5/CDG_VFSY MSB first. CDG-SDATA: CD+G (Subcode) Data. Indicates serial subcode data input. CDG-VSFY: CD+G (Subcode) Frame Sync. Indicates

186-189

DVD-DATA4/ CDG_SDATA

DVD-DATA6/CDG_SOSI DVD-DATA7/CDG_SCLK

frame-start or composite synchronization input. CDG-S0S1: CD+G (Subcode) Block Sync. Indicates block-start synchronization input. CDG-SCLK: CD+G (Subcode) Clock. Indicates subcode data clock input or out-put. 190 191 PI101 VREQUEST I/O O Programmable I/O pins. Video request. Decoder asserts VREQUEST to indicate that the video input buffer has available space. Polarity is programmable. Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In 192 VSTROBE I Asynchronous mode, anexternal sourcepulses VSTROBE to indicate data is ready for transfer. In synchronous mode VSTROBE clocks data. 193 194 195 VDD AREQUEST VSS O 3.3-V supply voltage for I/O signals. Audio request. Decoder asserts AREQUEST to indicate that the audio input buffer has available space. (Not used.) Ground for core logic and I/O signals. In synchronous mode, Video data acknowledge. Asserted when DVD data is valid. 196 V-DACK/ASTROBE I Polarity is programmable. In asynchronous mode, data strobing for audio bit stream input. 197 VDD 2.5-V supply voltage for core logic.

66

Pin No. 198 199 200 201 202-204 205

Pin Name A-DACK VSS

I/O I Audio data acknowledge.

Description

Ground for core logic and I/O signals.

HOST&SEL HADDR0-2 DTACKSEL

I I I

Pull up. Host address bus. 3-bit address bus selects one of eight host interface registers. Tie HIGH to select WAIT signal, LOW to select DTACK signal (Motorola 68K mode).

206

/CS

Host chip select. Host asserts CS to select the decoder for a read or write operation. The falling edge of this signal triggers the read or write operation.

207 208

R/W /RD

I I

Read/write strobe in M mode. write strobe in I mode. Host asserts R/W LOW to select write and Read strobe in I mode. Must be held HIGH in M Mode LOW to select Read.

67

IC, GDC25D801
Pin No. 1-16 17 18-21 22 23-27 28 29 30 31 32 33 34 35 36 37 38 39-45 46 47-52 53-56 57 58 59 60 61 62 63 64 65 66-68 69 70 71 72 73 74 75 76 77 78 79 Pin Name DAT1-16 VSS ADD1-4 VDD ADD5-9 X2_MCK VSS MCK VDD RAS UCAS LCAS WE OE SCAN_IN TEST_SE TEST_OUT12-6 T_SEL TEST_OUT5-0 TEST_SEL0-3 TESTSERVO E_SIN E_CLK E_ENB E_DRB VSS SERVO CLK E_SOUT VDD E_ST0-2 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VSS SENS VDD I/O I/O O I O I I O O O O O I I O I O I I I I I I I O O I/O I/O I/O I/O I/O I/O I/O I/O O Bi-directional data to DRAM. Digital GND. Address output to DRAM. Digital power supply. Address output to DRAM. Master clock from oscillator for 2x decoding. Digital GND. Master clock from oscillator. Digital power supply. Row address strobe to DRAM. Column address upper byte control strobe to DRAM. Column address lower byte control strobe to DRAM. Write enable signal to DRAM. Output enable signal to DRAM. Scan data input (Not used.) Test mode selection (low for normal) (Connected to GND.) Test output (Not used.) Test selection : 0 for normal. Test output (Not used.) Test mode output selection. TEST PIN (NORMAL STATE = H ) (Connected to VDD.) SERVO DSP PGM. DOWNLOADING DATA INPUT. SERVO DSP PGM. DOWNLOADING CLK. SERVO DSP DOWNLOADING ENABLE. SERVO DSP PGM. DOWNLOADING DIRECTION. Digital GND. SERVO DSP CLOCK INPUT. SERVO DSP PGM. DOWNLOADING DATA OUTPUT. Digital power supply. SERVO DSP DOWNLOADING STATUS 0-2. SERVO DSP GENERAL I/O: FSON (FOCUS OK INVERTING). SERVO DSP GENERAL I/O: PSEL. SERVO DSP GENERAL I/O: ADADDR3 (Not used.) SERVO DSP GENERAL I/O: FKRST (Not used.) SERVO DSP GENERAL I/O: FKSET (Not used.) SERVO DSP GENERAL I/O: FEL (Not used.) SERVO DSP GENERAL I/O. SERVO DSP GENERAL I/O: DSP_SENSE. Digital GND. SERVO DSP INTERNAL STATUS MONITOR. Digital power supply. Description

68

Pin No. 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106-111 112 113 114 115 116 117 118 119 120 121 122 123 124 125

Pin Name SCLK SDATA XLAT AOUT1 AOUT2 AVDD VCM AGND AOUT3 AOUT4 DGND RFVCM DVDD AGND VREFN VREFP INP AGND AIN4 AIN3 AVDD AIN2 AIN1 AIN0 ADCVCM SCK EXT_AD0-5 SELEFM EXCK SQCK C16M DOTX VDD SQSO VSS PWMCH1 PWMCH2 PWMCH3 PWMCH4 PWMCH5 PWMCH6

I/O I I I O O I O O I I I I I I I I I I O I I I I O O O O O O O O O Serial Command CLOCK. Serial Command DATA. Serial Command LATCH. TDF. TDF. Analog power supply for ADC. TDF. Analog GND for ADC. TDF. TDF. Digital GND for ADC. TDF (Connected to VREF.) Digital power supply for ADC. Analog GND for ADC. TDF. TDF. TDF (Connected to VREF.) Analog GND for ADC. TDF (Connected to VREF.) TDF. Analog power supply for ADC. TDF. TDF. TDF. TDF (Connected to VREF.) PLL clock output. ADC data input (Not used.)

Description

EFMDATA INPUT SELECTION (Connected to GND.) SUB DATA REQUEST INPUT (Not used.) SUB Q DATA REQUEST. 5.6448 MHz (DIGITAL OUT CLOCK) (Not used.) CD DIGITAL DATA OUTPUT (Not used.) Digital power supply. SUB Q DATA OUTPUT. Digital GND. PWM CHANNEL1 (x3 CARRIER). PWM CHANNEL1 (x3 CARRIER). PWM CHANNEL1 (x3 CARRIER): SLED DRIVE OUTPUT. PWM CHANNEL1 (x1 CARRIER): PDO_CTR PWM OUTPUT. PWM CHANNEL1 (x1 CARRIER): RF_GAIN_CTL PWM OUTPUT. PWM CHANNEL1 (x1 CARRIER): TE_BAL_CTL PWM OUTPUT.

69

Pin No. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147-154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173

Pin Name DEFECT_IN_A SI_ENC1 SI_ENC2 TZC MIRR MSDATAO FOK VDD DEFECT VSS SLD_FG C_SIG COMP INT1_ INT2_ VSS INT3_ INT4_ VDD PADCSB ADCOMP VDCDATA0-7 ADADDR0 DVDD ADADDR1 DGND AGND VRT AVDD RF VRM VRB MDS MDP OVER64 MON LOCK FG_M VSS SCAN_OUT VDD

I/O I I I I I O O O O O O O O O I I I I O I I I I I O O O O O I O EXTERNAL DEFECT INPUT PIN. SLED ENCODER1 INPUT.

Description

SLED ENCODER2 INPUT (Connected to GND.) TRACK CROSS PULSE 2 INPUT. TRACK CROSS PULSE 1 INPUT. SERVO DSP INTENAL STATUS SERIAL OUTPUT. INTERNAL GENERATED FOK (Focus OK) H=OK. Digital power supply. INTERNAL GENERATED DEFECT: H=DEFECT. Digital GND. SLD_FG=(SL_ENC1) XOR (SL_ENC2) (Not used.) TRACK CROSS PULSE. TRACK CROSS MONITOR (Not used.) SERVO DSP INTERRUPT 1 MONITOR (MICOM COMMAND INT) (Not used.) SERVO DSP INTERRUPT 2 MONITOR (FOCUS SERVO INT) (Not used.) Digital GND. SERVO DSP INTERRUPT 1 MONITOR (TRACK SERVO INT) (Not used.) SERVO DSP INTERRUPT 1 MONITOR (Not used.) Digital power supply. A/D 7824 OUTPUT ENABLE (LOW ACTIVE) (Not used.) A/D 7824 A/D CONVERTER A/D CONVERSION END STATUS (Not used.) A/D 7824 A/D CONVERTER DATA BUS0-7. (Connected to GND.) A/D 7824 A/D CONVERTER ADDRESS (Not used.) Digital power supply for ADC. A/D 7824 A/D CONVERTER ADDRESS (Not used.) Digital GND for ADC. Analog GND for ADC. TDF. Analog power supply for ADC. TDF. TDF. TDF. Spindle motor control signal (Not used.) Spindle motor control signal (Not used.) Not used. Spindle motor ON/OFF control signal. CLV servo lock signal. TDF. Digital GND. SCAN DATA OUTPUT (Not used.) Digital power supply.

70

Pin No. 174 175 176 177 178-183 184 185 186 187-193 194 195 196 197-204 205 206 207 208

Pin Name INT RN WN CS A0-5 VSS PS0 VDD PS1-7 RESET REQ_DIVX REQ_MPEG MPEG1-8 SENB SDCLK SERR SYNC

I/O O I I I I I I/O I I I O O O O O Interrupt request to Host. Read strobe from HOST. Write strobe from HOST. Chip select from HOST.

Description

Internal register address from HOST. Digital GND. Bi-directional data to HOST. Digital power supply. Bi-directional data to Host. HARDWARE RESET. Data request from DIVX module. Data request from MPEG. MPEG data. MPEG data valid signal (low for valid). MPEG data transfer clock. MPEG data error detection signal (low indicates error occurred). MPEG data sector sync. signal.

71

IC, HD6417034AFI20
Pin No. 1 Pin Name Z06 I/O I/O Description SUB Q Code Sync Detection Signal (CD Disc Mode). 1. Interrupt request signal to -COM (DVD disc mode). 2. Type: a. Track miss occurred b. Search End 2 DSP_INT I/O c. New sector out start d. DSI data is ready e. New sector in f. System data is ready g. Back track jump request 3 4-11 12 13, 14 15 16-21 22 23-30 31 32-39 40 41, 42 43 44-47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 GND D00-D07 GND D08, D09 VCC D10-D15 GND A00-A07 GND A08-A15 GND A16, A17 VCC A18-A21 /ROM_CS /CASH /IOCS1 /CASL GND BCA_CODE /RAS DPLL_L /MICOM_WAIT /WR E_SOUT /RD DSP_SENSE GND E_SIN E_CLK MPEG_WR M_REQ I I/O I I/O I I/O I O I O I O I O O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O GND. Data Line 00-07. GND. Data Line 08, 09. 5VD. Data Line 10-15. GND. Address Line 00-07. GND. Address Line 08-15. GND. Address Line 16, 17. 5VD. Address Line 18-21. Chip Enable For Flash ROM. CAS for Higher Byte for DRAM. Chip Enable to Multiplexer (IC101). CAS for Lower Byte for DRAM. GND. BCA Code Input when DIVX Disc Mode Not used. RAS for DRAM. Digital PLL IC Serial Data Latch Out. MPEG IC Internal Status Serial Input. Write Signal for DRAM/FlashROM/DSP/MPEG. Servo DSP Program Downloading Data Out. Read Signal for DRAM/FlashROM/DSP/MPEG. Command response signal (SERVO/DSP -COM). GND. Servo DSP Program Downloading Data IN. Servo DSP Program Downloading Clock. MPEG and Host I/F Read/Write Control Output. Serial Communication Request to Front -COM.

72

Pin No. 66 67

Pin Name F_REQ /STROBE

I/O I/O I/O

Description Serial Communication Request from Front -COM. Flash ROM Download I/F (Data Strobe in). 1. Servo Event detection signal input 2. Type: a. Focus Error S-curve detection

68

SENS_MCOM

I/O

b. 1 track jump completed c. 10 track jump completed d. etc

69 70 71 72 73 74 75 76 77 78 79 80 81, 82 83-85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105

MPEG_INT VCC NC GND X1 X2 VCC NC VCC NC MICOM_RESET VCC GND VCC VCC SBADD ECHO MIC_A DISC_A GND F/R LOCK DEFECT FOK GND IIC_DATA IIC_CLK VCC LOAD_FR MSDATA0 S_DATA S_CLK SLD_FG SPINDLE_FG

I/O I I I O I I I I I I I I I I I I I I I I I I/O I/O I I/O I/O I/O I/O I/O I/O

Interrupt Input from MPEG (IC301). 5VD. NC. GND. Crystal (20MHz) Input. Crystal (20MHz) Output.

5VD.

NC. Low Active Reset Input from Front. 5VD. GND. 5VD. 3.3VD. SBADD (Sub Beam Add) Signal Input from RF IC Not used. DC voltage of Echo Volume Input. Mic Audio Signal Input for Karaoke Score Function Not used. Disc Audio Signal Input for Karaoke Score Function Not used. GND. Spindle Rotation direction Input from Spindle Motor IC. CLV Servo Locking Signal Input from DSP IC. DISC DEFECT DETECTION Signal Input (Active High). FOCUS OK signal (H=OK) from DSP. GND. IIC Bus Data for EEPROM (IC114) and Video ENCODER. IIC Bus Clock for EEPROM (IC114) and Video ENCODER. 5VD. Tray Open and Close Control output. Servo DSP IC Internal Status Serial Input. Serial command interface port between RF or SERVO/DSP IC and -COM. Sled Motor FG Input. Input the FG Signal of Spindle Motor.

73

Pin No. 106 107 108 109 110 111 112

Pin Name GND RXDO TXDO SQSO MODE_SW SCKO SQCK

I/O I I/O I/O I/O I/O I/O I/O GND. Serial Data Input from Front. Serial Data OUT to Front.

Description

SUB Q Data Input from Servo & DSP IC. Program Download mode detect (Download mode is L). Serial Interface Clock to Front. SUB Q Data Request to Servo & DSP IC.

74

IC, LC866112B-5N21
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14, 15 16 17-20 21 22 23 24 25-31 32-40 41 42 43-52 53-56 57 58 59 60-64 65 66 67 68-70 71 72 73 74 75 76 77 Pin Name P35 P36 P37 PWM1 TEST1 /RES XT1 XT2 VSS CF1 CF2 VDD P80 P81, P82 P83 P84-P87 MODE_SW M_REQ P72 P73 G1-G7 P1-P9 VPP VKK P10-P19 S26-S29 S30 S31 P00 P01-P05 ZOOM_RST V07 VSS P10-P12 F_RXD F_TXD F_CLK F_REQ M_RESET PWR_CTL P31 I/O I I I O I I O I O I I I I I/O I I I O O I I O I/O O I I O O O I/O GND. Reserved. Serial data to IC108 (Main -COM, SH7034). Serial data input from IC108 (Main -COM, SH7034). Serial clock input from IC108 (Main -COM, SH7034). Request signal (Active LOW) to IC108 (Main -COM, SH7034). Reset signal (Active LOW) to IC108 (Main -COM, SH7034). Power control (Active HIGH) to main board. Not used. Not used. Description Select down SW input from CN505 (SW509). Enter SW input from SW501. Select right SW input CN505 (SW509). Not used. Not used (Test port). Reset signal input from IC501 3 pin. Not used (Input for 32.768kHz crystal oscillation). Not used (Output for 32.768kHz crystal oscillation). GND. Ceramic resonator X501 (6MHz) oscillation input. Ceramic resonator X501 (6MHz) oscillation output. VCC (5V). KEY IN input from CN504. Reserved. Shuttle 3 line A/D input. Not used. LOW at program download mode. Request signal (Active LOW) from IC108 (Main -COM, SH7034). Not used. Remocon receiver signal input. VFD display control signal output. DIG 501 G1 to G7. VFD display control signal output. DIG 501 P1 to P9. VCC (5VAU). -27V from CN503 (SMPS). VFD display control signal output. DIG 501 P10 to P19. Not used. D503 option (Present at AIWA remocon model). Not used. Diode option input.

75

Pin No. 78 79 80

Pin Name P32 P33 P34

I/O I I I

Description UP signal input from CN505 (SW509). JOG signal JSW1 input CN505 (JS500). LEFT signal input from CN505 (SW509).

76

IC, XC9536-15VQ44C
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28-30 31 32 33 34 35 36 37 38 39-43 44 Pin Name SCART1 SCART2 TEST PIN GND PWR_CTL TEST PIN MPEG_CS DSP_CS TD1 TMS TCK PP_CS CLOSE_SW OPEN_SW VCC SENSE GND ZISERR DAC_LO DINO_CS WR MICOM_WAIT MIC_ON TDO1 GND VCC RF_LAT A21-A19 MPEG_WAIT LIMIT_SW MICOM_RESET EXP_W2 VCC PWR_CTL MPEG_ERROR SENSE_MCOM DO0-DO4 IOCS1 I/O O O O O O O O I I I O I I I I O O I O I O O I I I I O I O O I/O I Software download adapter select. Tray limit SW input (LOW is input at tray close end position). Tray limit SW input (LOW is input at tray open end position). VCC. Interface signal for IC206 (DSP IC, GDC25D801). Ground. EDC (Error detection & correction) signal input from IC206 (DSP IC, GDC25D801). Audio DAC latch strobe signal. Not used. IC108 (Main -COM, SH7034) bus write signal. -COM WAIT signal. Karaoke MIC input. JTAG program port for CPLD Upgrade. Ground. VCC. IC201 (RF IC, TA1254) serial interface latch signal. IC108 (Main -COM, SH7034) address signal. Wait signal from IC301. (MPEG IC, ZIBA-3) Sled limit switch input. -COM, expander reset signal input. IC103 (Expander, 74HC374) latch strobe. VCC. Power control input from IC500 (Front -COM). EDC (Error detection & correction) signal output to IC301 (MPEG IC, ZIBA-3). IC206 (DSP IC, GDC25D801) interface signal to IC108 (Main -COM, SH7034). IC108 (Main -COM, SH7034) data bus. IC101 (CPLD, XC9536) chip select from IC108 (Main -COM, SH7034). JTAG program port for CPLD upgrade. Description Wide disc playback high output (16:9 mode detect). DVD power on HIGH (HIGH signal output to SCART 8 pin, SCART enable). For software debugging. Ground. Power control output to expander IC. For software debugging. IC301 (MPEG IC, ZIBA-3) chip select. IC206 (DSP IC, GDC25D801) chip select.

77

IC BLOCK DIAGRAM IC, BA5983FP

IC, BA6859AFP

78

IC, KIA393F

IC, PLL1700E

79

IC, SN74AHC374PWLE

IC, TA1254F

80

MECHANICAL EXPLODED VIEW 1/1

462

MECHANICAL PARTS LIST 1/1

462

P.C.B

463

REF. NO 250 280 283 300 452 462 463 464

KANRI DESCRIPTION NO. S1-10R-014-3A0 CASE TOP S7-21R-F12-5A0 PANEL ASSY FRONT[NO S5-81R-000-7A0 TRAY DOOR ASSY S4-10R-AHC-02B NI NM CORE SP-2 1 POW<EZ> S3-530-51A-000 SCREW,SPECIAL S3-530-46K-000 S3-530-51B-000 S3-530-46N-000 SPECIAL SCREW 3-10 B.K SPECIAL SCREW SPECIAL SCREW 3-8 BK

PART NO.

464

462

463

463

463

P.C.B

250

COLOR NAME TABLE

Basic color symbol Color Basic color symbol Color Basic color symbol Color B Black C Cream D Orange G Green H Gray L Blue LT Transparent Blue N Gold P Pink R Red S Silver ST Titan Silver T Brown V Violet W White WT Transparent White Y Yellow YT Transparent Yellow LM Metallic Blue LL Light Blue GT Transparent Green LD Dark Blue DT Transparent Orange

300

462

MAIN CHASSIS ASSY

283

452

452

463

P.C.B 452 LDM-H109 452 P.C.B

81

463

463

463

280

P.C.B

463

82

MECHANISM EXPLODED VIEW 1/1

418

031

A02
418 004 428

A06
038 035 427 041 040

PU BASE

039

418

012

037

418

MAIN BASE

011

423

018

419

013 014

P.C.B
017

026 016

015

019

418 418 418

418

83

84

MECHANISM PARTS LIST 1/1

REF. NO 004 011 012 013 014 015 016 017 018 019 026 031 035 037 038 039 040 041 428 A02

KANRI DESCRIPTION NO. S8-10H-105-5A0 CLAMP,LDM-R608 BRACKET S2-10H-101-1A0 FRAME UP/DOWN S0-40H-103-9B0 RUBBER F(D2) S4-00H-101-0A0 LOADING BELT S4-70H-112-9A0 PULLEY GEAR S6-81R-102-1A0 S4-70H-113-1A0 S4-30H-000-4A0 S4-70H-113-0A0 S9-31H-000-3A0 S3-90H-102-1A0 S3-70H-108-5B0 S3-70H-108-5A0 S6-80H-B10-24B S9-70H-110-0A0 S3-71H-100-9A0 S6-81H-102-0A0 S0-40H-104-0B0 SS-ZZH-101-6A0 S8-61H-001-1A0 LOADING MOTOR ASSY LOADING GEAR LOADING CAM EMERGENCY GEAR HOLDER ASSY DECK ON DISC TRAY SHAFT PU SUB SHAFT PU MAIN MOTOR(MECH) SPRING SKEW LEAD SCREW SHAFT PU FEED MOTOR ASSY RUBBER R(D2) SCREW,+2.0-3.5 DISC CLAMP ASSY MECHANISM ASSY

PART NO.

A06 S4-05H-108-0B0

85

211, IKENOHATA 1CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111
931196 Printed in Singapore