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Experiment #1: Flip Flops and Sequential Circuits

Flip Flops and Sequential Circuits Objective The goal of this lab is to verify the performance of various flip-flops at the gate level and as Integrated circuits I!"s#$

Introduction %lip %lops are the main parts of se&uential circuits such as shift and registers$ In this laboratory e'periment( the functioning of )-* and + flip-flops( as ,ell as counters and shift registers ,ere e'amined$ In the first portion of this lab report( simulations are presented( ,hile the second portion sho,s the e'perimental part of the lab$

Apparatus -rotoboard Triple -o,er .upply +igital /ultimeter %unction 0enerator +igital 1scilloscope

Components 7273 +ual )-* %lip %lop 7272 4dge Triggered + %lip %lop 7255 T,o Input 676+ gate

Soft are /ulti.im 7 8ab9I4:

Section I Simulation Figure 1 sho,s the 8atch circuit that ,as implemented on /ulti.im$ The :ord 0enerator generated the + and !- inputs ,hile the 8ogic 7naly;er monitored outputs and inputs$

%igure <= + 8atch !ircuit

The simulation of this + type flip-flop produced the timing diagram sho,n in Figure 2$

%igure >= + 8atch Timing +iagram

7s it can be seen in figure 2( ,henever the cloc? pulse is high cloc?@<# the A output of the latch ta?es on the value of the + input$ :hen the cloc? is lo, cloc?@5#( the A output

stays the same$ This behavior is e'pected( since the circuit uses a +-type edge triggered flip-flop$ Figure 3 sho,s the B-bit .ynchronous !ounter that ,as implemented on /ulti.im$ 7273 )-* flip-flop I!s ,ere used in order to count from 5 C 7 modulo D#$

%igure B= B-bit .ynchronous !ounter

/ulti.im"s :ord 0enerator produced cloc? pulses ,hile the 8ogic 7naly;er monitored the cloc? pulses and outputs A5( A<( and A>$ The simulation of this B-bit .ynchronous !ounter produced the follo,ing timing diagram sho,n in figure 4:

%igure 2= B-bit .ynchronous !ounter

.imilarly( Figure 5 sho,s the B-bit 7synchronous !ounter that ,as implemented on /ulti.im$ 7273 )-* flip-flop I!s ,ere used in order to count from 5 C 7 modulo D#$ Enli?e the circuit for the .ynchronous counter( the use of a 676+ gate ,as not necessary and the previous bit of each counter ,as used to control the ne't bit( only the cloc? of the first counter ,as connected to the function generator$

%igure F= 7synchronous !ounter

The simulation of the B-bit 7synchronous !ounter produced the follo,ing timing diagram sho,n in figure 6:

%igure 3= Timing +iagram for the 7synchronous !ounter

Figure 7 sho,s a 2-bit .hift Gegister that implemented on /ulti.im$ T,o 7272 + flipflop I!s ,ere used in order to count from 5 C <F modulo <3#$

Figure 7= 2-bit .hift Gegister

These flip-flops are edge triggered + flip-flops$ The circuit sho,n in Figure 7 ,as simulated and /ulti.im and produced the timing diagram sho,n in Figure 8, ,here the outputs appear to be shifting the input bits =

Figure 8= 2-bit .hift Gegister"s Timing +iagram

The timing diagram sho,n in Figure 8 represents the cloc? inputs produced the /ulti.im"s :ord 0enerator and the outputs A5( A<( A>( AB that ,ere monitored by the 8ogic 7naly;er$

Section II Experimental !esults

In this section( the results obtained from implementing the circuits of figures 3, 5, and 7 on the protoboard are reported$ The .ynchronous !ounter sho,n in figure 3 ,as built on the protoboard$ The inputs ,ere produced by the %unction 0enerator$ In order to reduce noise( a 5$< micro capacitor could have been placed across the 9!! and 0round pin for each of the I!s( but that ,asn"t done here$ 7lso( <5? ohms resistors could have been placed in series ,ith the long output ,ires( but that ,as not done( as it ,as possible to obtain the accurate results ,ithout using these components$ .imilarly( the 7synchronous !ounter( figure 5, ,as also built on the protoboard and analy;ed$ The follo,ing figures 9-11# sho, the 1scilloscope Images of the synchronous counter for A5( A<( and A>( respectively$

Figure 9: Oscilloscope Image for Sy c!ro ous "ou #er $ %&

Figure 1&: Oscilloscope Image for Sy c!ro ous "ou #er $ %1

Figure 11: Oscilloscope Image for Sy c!ro ous "ou #er $ %2

8astly( the .hift Gegister sho,n in figure 7 ,as built on protoboard$ This time 8ab9I4: 9I ,as used$ The :ord 0enerator long ,ires connected to -ort 7# provided the inputs( the cloc? pulses ,ere provided by The !loc? long ,ires connected to -ort !#( and the 8ogic 7naly;er -ort H# monitored the outputs A5( A<( A>( and AB$

Fiure 12: S!if# 'egis#er O (ro#o)oar*

+a)le 1 sho,s the .hift Gegister built on the protoboard counting as e'pected=

+a)le 1: S!if# 'egis#er Ou#pu#

Conclusion

This e'periment allo,ed students to understand ho, se&uential circuits ,or? through simulations and e'perimental analysis$ 4'perimental results of .ection > matched the simulation results obtained in .ection <$ It ,as observed that synchronous counters lin? all I!"s to one cloc?( ,hile an asynchronous counters lin? outputs to the cloc?s of its I!s$ The .hift Gegister ,as observed to shift one binary bit after another$ 1verall( students successfully designed various se&uential systems$ :hile doing so( ,e learned the differences bet,een a synchronous counter and an asynchronous counter and ho, a shift register actually ,or?s$ :e feel ,e have gained enough ?no,ledge to design our o,n se&uential circuits( ,hich ,e could not do( successfully( before this laboratory e'periment$