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Chapter 2 - 8255

Chapter 2: 8255 Programmable Peripheral Interface

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Chapter 2 - 8255

Features
The 8255 is a programmable, parallel I/O device simply called PPI. It can be programmed to transfer data in various modes of I/O. It provides 24 I/O pins that can be grouped into three 8 bit parallel ports: PORT A, PORT B and PORT C. The 8 bits of port C is separated into two 4-bit ports: PORT C UPPER (PC4-PC7) and PORT C LOWER (PC0-PC3) see the fig1.0.

-The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral chip originally developed for the Intel 8085 microprocessor. Intel 8255A is NMOS version. N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. - 82c55A is the high performance CMOS version of 8255 by Intersil Company. CMOS uses complementary and symmetrical pairs of ptype and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Department of Mechatronics Le Thanh Hai

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Chapter 2 - 8255

PIN Diagram and its description

The IC available in DIP, CLCC, DLCC packages.
PLCC-Plastic leaded chip carrier

dual in-line package (DIP or DIL)

CLCC: Ceramic Leadless Chip Carrier

In electronics, a chip carrier is one of several kinds of surface mount technology packages for integrated circuits.
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Chapter 2 - 8255

PIN Diagram and its description

VCC: The +5V power supply pin. A 0.1mF capacitor between pins 26 VCC and 7 GND (DIP) is recommended for decoupling.

IC power supply pin (VCC), plus collector supply line voltage in a common NPN circuit. In electronics, decoupling refers to the preventing of undesired coupling between subsystems via the power supply connections. Noise caused by other circuit elements is shunted through the capacitor.
GND: Ground. DATA BUS (D0-D7): The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode. CHIP SELECT: Chip select is an active low input used to enable the 82C55A. READ: This control signal enables the Read operation. When the signal is low, the microprocessor reads data from a selected I/O Port of the 8255.

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Chapter 2 - 8255

PIN Diagram and its description

WRITE: This control signal enables the write operation. When the signal goes low, microprocessor writes data into a selected I/O Port or control register. ADDRESS (A0,A1): These input signals, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1.

PORT A (PA0-PA7): 8-bit input and output port. PORT B (PB0-PB7): 8-bit input and output port. PORT C (PC0 -PC7): 8-bit input and output port.
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Chapter 2 - 8255

82C55A BASIC OPERATION

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Chapter 2 - 8255

Functional Diagram
There are two different operating modes for the 8255. These modes must be defined by the microprocessor writing program or control words of 8255. 1) Bit Set-Reset mode (BSR) : BSR mode is used to define the handshaking signals. 2) I/O mode: It is used for I/O data transfer.

In the functional diagram two control groups, labeled group A control and group B control define how the three I/O ports operate. The upper 4 bits of PORT C along with PORT A are associated with group A control while the lower 4 bits of PORT C along with PORT B are associated with group B control.
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Chapter 2 - 8255

Control Word Register

The 8255 may be operated in one of the two modes (BSR or I/O), by initializing D7 bit in Control word register.

If bit D7=1, 8255 operate in I/O mode and the bits D6-D0 determines I/O operations in various modes. Bits D2, D1, D0 determine the Group B control. Bit D2 is for I/O mode selection and bits D1 and D0 are used to initialize the ports as Input or output. Similarly the bits D6-D3 determines the Group A control. D6 and D5 bits are for mode selection and the bits D4 and D3 are used to initialize the ports as input or output.
BSR Mode

I/O Mode

If bit D7=0, 8255 operates in BSR mode and the Port C bits are used to initialize handshaking signals.

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Chapter 2 - 8255

Setting/Resetting PORT C bits as handshaking signal in BSR mode:

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Chapter 2 - 8255

Control word in I/O mode :

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Chapter 2 - 8255

I/O Operating Modes Mode 0: Simple Input or Output:

In this mode, ports A, B and C are used as simple 8-bit I/O ports. This mode doesnt require handshaking signals. Hence no need of BSR mode. So we can directly program the control word to I/O mode. Note: BSR mode is used to define the handshaking signals. Note: The two halves of PORT C are independent, so one half can be used as input, and other half used as output. Fig 1.5 shows that control word is programmed as simple I/O mode or mode 0 by setting D7 = 1.

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Chapter 2 - 8255

Mode 1: Strobed I/O or single Handshake I/O

This functional configuration provides a means for transferring I/O data to or from, a specified port in conjunction with strobes or hand shaking signals. When Group A and Group B are programmed to mode1. The two ports operated in strobed I/O mode. To do this first of all the control word register is programmed to BSR mode to define the strobe signal as handshaking. After that again control word register is programmed to I/O. Mode 1 Basic Function Definitions: Two Groups (Group A and Group B) Each group contains one 8-bit port and one 4-bit control/data port The 8-bit data port can be either input or output. Both inputs and outputs are latched. The 4-bit port is used for control and status of the 8-bit port.

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Chapter 2 - 8255

Group A and B as input in mode1:

D2, D1, D0 thuc v PORTB

D6, D5, D4, D0 thuc v GROUP A

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Chapter 2 - 8255

Group A and B as input in mode1 Input control signal Definition

STB (Strobe Input) A Logic low on this input loads data into the port from external peripheral device. IBF (Input Buffer Full) Logic high on this output indicates to the peripheral device that the data has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) INTR is a signal used to indicate the microprocessor, that a byte has been received on 8255 port. Now the microprocessor collects the data byte from the 8255 port. INTR is set by the condition: STB == 1, IBF == 1 and INTE == 1. It is reset by the fallingedge of RD. INTE A Controlled by bit set/reset of PC4 INTE B Controlled by bit set/reset of PC2.

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Chapter 2 - 8255

Group A and B as output in mode1

Trong ch Mode 1: + PORT A,B l 2 PORT I/O + PORT C l PORT cung cp tn hiu handshaking + Tuy nhin c chn PC4 v PC5 l I/O port.

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Chapter 2 - 8255

Group A and B as output in mode1 Output control signal Definition

OBF (Output Buffer Full): The logic low on this signal is an indication to the peripheral device that the microprocessor written a data byte into the 8255 port. The OBF will be set by the rising edge of the WR input and reset by ACK input being low. ACK (Acknowledge input): After receiving OBF signal, the peripheral sends ACK signal as low to 8255 indicating that it is ready to accept the data. INTR (Interrupt request): Logic high on this output can be used to interrupt the microprocessor when an output device has accepted data transmitted by the microprocessor. INTR is set when ACK == 1, OBF == 1 and INTE == 1. It is reset by the falling edge of WR. INTE A Controlled by Bit Set/Reset of PC6. INTE B Controlled by Bit Set/Reset of PC2.

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Chapter 2 - 8255

COMBINATIONS OF MODE 1

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Chapter 2 - 8255

Mode 2 (Bi-Directional handshaking I/O):

This mode is used primarily in applications such as data transfer between two computers. In this mode, PORT A can be configured as the bidirectional port and PORT B either in Mode0 or Mode1. PORT A uses five signals from PORT C as handshake signals for data transfer. The remaining three signals from PORT C can be used either as simple I/O or as handshake for port B.

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Chapter 2 - 8255

Mode 2 (Bi-Directional handshaking I/O):

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Chapter 2 - 8255

Mode 2 (Bi-Directional handshaking I/O)

Bi-Directional Bus I/O Control Signal Definition
INTR (Interrupt Request): A high on this output can be used to interrupt the microprocessor for both input or output operations. Output Operations OBF (Output Buffer Full). The logic low on this signal is an indication to the peripheral device that the microprocessor written a data byte into the 8255 port. ACK (Acknowledge). After receiving OBF signal, the peripheral sends ACK signal as low to 8255 indicating that it is ready to accept the data . INTE1 (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4 as shown in fig 1.8. Input Operations STB (Strobe Input): A Logic low on this input loads data into the port from external peripheral device. IBF (Input Buffer full): Logic high on this output indicates to the peripheral device that the data has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB input being low and is reset by the rising edge of the RD input. INTE 2 (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4 as shown in fig 1.8 .
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Chapter 2 - 8255

MODE 2 COMBINATIONS

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Chapter 2 - 8255

MODE 2 COMBINATIONS

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Chapter 2 - 8255

Interfacing of 8255 with 8085 processor

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Chapter 2 - 8255

Interfacing PIC using PPI

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Chapter 2 - 8255

Interfacing ADC0808 with 8255

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Chapter 2 - 8255

Interfacing ADC0808 with 8255

Vcc Supply pins +5V GND GND Vref + Reference voltage positive +5 Volts maximum. VrefReference voltage negative 0Volts minimum. I/P0I/P7 Analog inputs ADD A,B,C Address lines for selecting analog inputs. O7 O0 Digital 8-bit output with O7 MSB and O0 LSB SOC Start of conversion signal pin EOC End of conversion signal pin OE Output latch enable pin, if high enables output CLK Clock input for ADC ALE Address latch enable; Input pin; low to high pulse is required to latch in the address
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Chapter 2 - 8255

How does a key-matrix works?

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Chapter 2 - 8255

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Chapter 2 - 8255

Interfacing a 4x4 matrix keypad to PICMicro

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