Ix 721

AudioMAX™ LX1721 / 1722
I N T E G R A T E D P R O D U C T S Class-D Stereo Power Amplifier Controller

P RODUCTION
DESCRIPTION KEY FEATURES
WWW . Microsemi .C OM
The LX1721/1722 is a monolithic high A complete audio amplifier module is Integrated Switching Class-D
performance Class-D stereo controller IC available to quickly evaluate the LX1721 Stereo Controller IC
designed for high efficiency or space or LX1722 stereo controller. Simply Full 20Hz-20kHz Audio
constrained audio requirements such as connect the amplifier to the power source, Bandwidth
portable or battery operated products, audio signal, and speakers. Reference High Fidelity (LX1721) Or
automotive amplifiers, and multi-channel designs support a variety of requirements High Power (LX1722)
Versions Available
multimedia computer and video game including multi channel systems, Single Supply Operation
applications. This high frequency, full subwoofers, satellite / subwoofer com- THD+N <0.06% Typical
audio bandwidth switching power binations and various speaker loads (2Ω, (1Wrms, 1kHz, 4Ω)
amplifier controller offers dramatically 4Ω, 8Ω). The versatile amplifier solution Maximum Efficiency 80%-
improved performance over Linfinity’s can easily be adjusted for frequency 85%
previous generation amplifier products. response, optimized for efficiency and Output Power >60Wrms per
Enhancements include higher output performance, or designed to minimize Channel (LX1722, 4Ω, 1%
power, better SNR, lower noise floor, and PCB area and component count. The THD+N)
reduced THD. Combined with output LX1721/1722 is available in a space PSRR –70dB Typical
Differential Input To Minimize
power MOSFET’s and an output filter, the saving 44-pin QSOP package. Noise Effects
LX1721/1722 is a complete Class-D audio (Continued Next Page)
Supports Multi-Channel
solution. Systems
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Complete LXE1721or
LXE1722 Amplifier Evaluation
Module Available
PRODUCT HIGHLIGHT 44-Pin QSOP Package
7V - 25V
Channel
1
IN +
Output Power vs. Supply Voltage APPLICATIONS
IN - FETs Left 1kHz, 4Ω, THD+N=1%
LX1722
Multimedia Speakers
Stereo Surround Sound Game
Channel 2
IN +
FETs Right Systems
IN - Notebook Computers
CLOCK 2Ω, 4Ω, 8Ω
Desktop Computers
Automotive Amplifiers And
Head units
LX1711 Battery Operated Equipment
FETs
Channel 3 Mono (Megaphone, Public Address
IN +
IN - System)
Subwoofer
Portable Audio (Boom Box)
Wireless Speakers
High Power Subwoofer
Automotive Audio Systems
2.1 Audio Amplifier
Home Theatre
Configuration LX1721 / 22
PACKAGE ORDER INFO
VDD Plastic QSOP

TJ (°C) DB 44-Pin
-20 to 70 7V – 15V LX1721CDB
-20 to 70 7V – 25V LX1722CDB
Note: Available in Tape & Reel.
Append the letter “T” to the part number. (i.e. LX1722CDBT)
Copyright  2001 Microsemi Page 1

Rev. 1.1,2003-06-10
Linfinity Microelectronics Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
P RODUCTION
THERMAL DATA PACKAGE PIN OUT
DB 44-PIN QSSOP PACKAGE LFAOUT 1 44 LFBK-
CPWM LFBK+
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 50°C/W RPWM LISN

LMUTE VDD
Junction Temperature Calculation: TJ = TA + (PD x θJA).

LEAOUT CN
LEAIN PVDD
The θJA numbers are guidelines for the thermal performance of the device/pc-board VREF PGND
CLOCK LN+
system. All of the above assume no ambient airflow. GND LP+
V25 LP-
LIN+ LN-
LIN- RN-
LAMPOUT RP-
RIN+ RP+
RIN- RN+
RAMPOUT PGND
SLEEP CP
STATUS PVDD
RMUTE NC
REAIN RISN
REAOUT RFBK+
RFAOUT 22 23 RFBK-
DB PACKAGE
(Top View)
DESCRIPTION (CONTINUTED)
The stereo output controller is available in either an THD+N levels of 0.06%(1kHz, 1Wrms). Efficiency is
LX1722 high power version (>65Wrms, 4Ω) with a supply greater than 80% typical, which eliminates the need for
voltage range of 7V-25V or an LX1721 high fidelity heatsinks in most applications. The AudioMAX™ solution
version (better SNR performance) with a supply voltage requires a single supply voltage, simplifying input power
range of 7V-15V. The current rating of the external requirements where a dual supply may not be available. To
MOSFET’s, the available supply voltage, and speaker load minimize potential environmental noise issues and ease the
primarily limits the maximum output power. The amplifier integration of the amplifier into a variety of applications,
provides high fidelity performance and is designed to features such as a balanced/differential audio input and a high
operate over the full 20Hz to 20kHz audio band. Signal power supply rejection ratio help reduce the effects of noise
distortion measurements yield. from the audio signal or power supply.
PACKAGE DATA

Rev. 1.1,2003-06-10
P RODUCTION
FUNCTIONAL PIN DESCRIPTION
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
LFAOUT Left Feedback Amplifier Output LFBK- Left Feedback Amplifier Inverting Input
Left Feedback Amplifier Non-Inverting
CPWM PWM Capacitor Connection LFBK+
Input
RPWM PWM Resistor Connection LISN Left Current Limit Sense Input
LMUTE Left Mute Input (Active High) VDD Analog Supply Voltage
LEAOUT Left Error Amplifier Output CN Supply Decoupling for NFET Drivers
LEAIN Left Inverting Input of Error Amplifier PVDD Output Driver Supply Voltage
VREF 5V Reference PGND Output Driver High Current Ground
Left Drive for NFET on Positive Half of
CLOCK Input / Output Clock for Synch Operation LN+
Bridge
Left Drive for PFET on Positive Half of
GND Low Current Ground LP+
Bridge
Left Drive for PFET on Negative Half of
V25 2.5V Reference LP-
Bridge
Left Drive for NFET on Negative Half of
LIN+ Left Positive Audio Input LN-
Bridge
Right Drive for NFET on Negative Half of
LIN- Left Negative Audio Input RN-
Bridge
Right Drive for PFET on Negative Half of
LAMPOUT Left Input Amplifier Output RP-
Bridge
Right Drive for PFET on Positive Half of
RIN+ Right Positive Audio Input RP+
Bridge
Right Drive for NFET on Positive Half of
RIN- Right Negative Audio Input RN+
Bridge
RAMPOUT Right Input Amplifier Output PGND Output Driver High Current Ground
SLEEP Sleep Input (active low) CP Supply Decoupling for PFET Drivers
STATUS UVLO Indicator (Open Collector Output) PVDD Output Driver Supply Voltage
RMUTE Right Mute Input (Active High) NC No Connect
REAIN Right Inverting Input of Error Amplifier RISN Right Current Limit Sense Input
Left Feedback Amplifier Non-Inverting
REAOUT Right Error Amplifier Output RFBK+
Input
RFAOUT Right Feedback Amplifier Output RFBK- Right Feedback Amplifier Inverting Input
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (PVDD, VDD) ............................................................................................................................. -0.3V to 30V

SLEEP , STATUS, R/LFBK+, R/LFBK- .................................................................................................-0.3V to VDD +0.3V
R/LISN .........................................................................................................................................PVDD –2 to PVDD to +0.3V
RPWM, CPWM, R/LMUTE ................................................................................................................... -0.3V to VREF +0.3V
R/LIN+, R/LIN-, R/LAMPOUT.............................................................................................................. -0.3V to VREF +0.3V
PACKAGE DATA
R/LEAIN, R/LEAOUT, R/LFAOUT ..................................................................................................... -0.3V to VREF + 0.3V
CLOCK ........................................................................................................................................................-0.3V to CN +0.3V
Operating Junction Temperature Plastic........................................................................................................................... 125°C
Storage Temperature Range ...............................................................................................................................-65°C to 150°C
Lead Temperature (Soldering, 10 seconds) ...................................................................................................................... 300°C
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into negative out of the
specified terminal.

Rev. 1.1,2003-06-10
P RODUCTION
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C < TA < 70°C (NOTE 2).
Test conditions: RPWM = 34.8k, CPWM = 100pF, VDD = PVDD = 15V
LX1721 / 1722
Parameter Symbol Test Conditions Units
Min Typ Max
Evaluation Module (See LXE1721)
Supply Voltage LX1721 7 15
VDD V
LX1722 7 25
VIN = 15V, VRIPPLE = 1VRMS, 20Hz
Power Supply Rejection Ratio PSRR -70 dB
to 20kHz
VIN = 15V, RL=4Ω, THD+N=1%,
25
10Hz to 22kHz
Output Power (Per Channel) PO W
VIN = 25V, RL=4Ω, THD+N=1%,
60
10Hz to 22kHz
VIN = 15V, fIN = 1kHz, PO = 10W 82
Efficiency %
VIN = 15V, fIN = 1kHz, PO = 20W 85
fIN = 1kHz, PO = 1W .06
Total Harmonic Distortion Plus Noise THD+N %
fIN = 20Hz to 20kHz, PO = 1W .2
Signal-To-Noise Ratio SNR RL = 4Ω, PO = 1W 81 dBr
Oscillator Section
Oscillator Frequency FOSC 450 kHz
Charge Current ICHG (varies with VDD pin voltage) -225 µA
Discharge Current IDIS (varies with VDD pin voltage) 225 µA
Oscillator Peak Voltage VPK (varies with VDD pin voltage) 3.6 V
Oscillator Valley Voltage VVAL (varies with VDD pin voltage) 1.4 V
Voltage Stability VDD = 8V to 25V 0.6 2 %
O O
Temperature Stability TA = 0 C to 70 C 1.0 2 %
Error Amplifier
Input Offset Voltage VIO 5 ‘mV
DC Open Loop Gain AOL 60 dB
Unity Gain Bandwidth UGBW 7 ‘MHz
High Output Voltage VOH IOUT = -100µA 3.5 V
Low Output Voltage VOL IOUT = +100µA 100 ‘mV
Input Bias Current IIN VIN = 1V to 4V 1 µA
Input Amplifier
Stage Gain Set by Internal Resistors 3.465 3.5 3.535 V/V ELECTRICALS
Output Voltage, High VOH IOUT = -100µA 3.85 V
Output Voltage, Low VOL IOUT = +100µA 1.3 V
Input Impedance 180 ‘kΩ
Feedback Amplifier
Stage Gain LX1721 Set by Internal Resistors 89 91 93 ‘mV/V
LX1722 Set by Internal Resistors 56 57 58 ‘mV/V
Input Impedance LX1721 250 kΩ
LX1722 400 kΩ

Rev. 1.1,2003-06-10
P RODUCTION
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1721 / 1722
Parameter Symbol Test Conditions Units
Min Typ Max
Current Limit Comparator
Voltage Sense Threshold 190 210 230 mV
Blanking Pulse Delay 500 ‘ns
Response Time Excluding blanking pulse 250 ‘ns
IUM Pulses required to Current Limit
4 4 4 ‘cycles
Latch
Consecutive Clear Pulses required to
2 2 2 ‘cycles
reset IUM counter
Reference Voltage Section
Initial Accuracy (VREF) 5.0
Voltage Stability (VREF) ± 50 ± 100 ‘mV
Initial Accuracy (V25) 2.5
Voltage Stability (V25) ± 25 ± 50 mV
O O
Temperature Stability TA = 0 C to 70 C 2 5 ‘mV
Line Regulation VDD = 9V to 15V 0.5 ‘mV
Load Regulation IOUT = 0 to 10mA 5 ‘mV
Under Voltage Lockout Section
Start Threshold Voltage 6 V
UV Lockout Hysteresis 250 mV
UVLO Delay To Output Enable 62,500 clkcyc
Supply Current
O
Sleep Current SLEEP Input = 0V, TA = 25 C 30 µA
SLEEP Input = 2V, VIN = 15V,
Operating Current 8 11 ‘mA
No MOSFETs connected
Sleep to Output Enable 62,500 clkcyc
Sleep Threshold 1.45 1.6 1.75 V
Mute Section
Mute Threshold 1.2 1.35 1.5 V
Output Drivers For N-Channel MOSFETs
ISINK = 3mA 30 100 ‘mV
NFET Drivers, Low Level Voltage VOL
ISINK = 100mA 0.3 1.0 V
ISOURCE = 3mA, CN = 5.2V
30 100 ‘mV
applied externally
NFET Drivers, High Level Voltage VOH
ISOURCE = 100mA, CN = 5.2V
0.3 1.0 V
applied externally
Output Drives For P-Channel MOSFETs
ISINK = 3mA 30 100 ‘mV
PFET Drivers, Low Level Voltage VOL
ELECTRICALS
ISINK = 100mA 0.5 1.0 V
ISOURCE = 3mA, CP = 5.2V
30 100 ‘mV
(applied externally)
PFET Drivers, High Level Voltage VOH
ISOURCE = 100mA, CP = 5.2V
0.5 1.0 V
(applied externally)
Note 2: The LX1721 / 22CDB is guaranteed to meet performance specifications from 0° to 70°C. Specifications over the -20° to 0°C operation temperature
range are assured by design, characterization, and statistical process control.

Rev. 1.1,2003-06-10
P RODUCTION
BLOCK DIAGRAM
VDD 41 17 SLEEP
7 VREF
UVLO
PVDD
LISN 42 & 10 V25
REFERENCE 5V
+ 40 CN
220m V Reference
CLOCK 8 SYNC -
RPW M 3 OSC CLK
27,39 PVDD
CPW M 2
5V
28 CP
CURRENT SENSE Reference
LEAOUT 5
36 LP+
LEAIN 6 FAULT
TIMER OUTPUT 37 LN+
DRIVERS
ERROR AMP
&
LAMPOUT 13
LOGIC 34 LN-
S Q
CLK R Q 35 LP-
LIN- 12
MUTE 1 LFAOUT
LIN+ 11
INPUT AMP MUX
MUTE 44 LFBK-
2.5V 43 LFBK+
FEEDBACK AMP
LMUTE 4
2.5V
FIGURE 1 – LX1721 / 22 SIMPLIFIED BLOCK DIAGRAM (LEFT CHANNEL CIRCUIT SHOWN)
BLOCK DIAGRAM

Rev. 1.1,2003-06-10
P RODUCTION
APPLICATION INFORMATION
Frequency Synchronization Oscillator Configuration (RPWM and CPWM selection)
Two or more LX1721 / LX1722 oscillators can be configured for The oscillator is programmed by the external timing components
synchronous operation. One unit, the master, is programmed for RPWM and CPWM. For a nominal frequency of 333kHz, RPWM and
the desired frequency with the RPWM and CPWM as usual. CPWM should be set to 49.9kOhms and 100pF respectively. Note that
Additional units will be slave units, and their oscillators will be in order to keep the slope of the PWM ramp voltage proportional to
disabled by leaving the RPWM pin disconnected. The CLOCK pin the supply voltage, both the ramp peak and valley voltages, and the
and the CPWM pin of the slave units should be tied to the CLOCK charge and discharge currents are proportional to the supply voltage.
pin and the CPWM pin of the master unit respectively. In this This keeps the frequency relatively constant while keeping the slope
configuration, the CLOCK pins of the slave units begin receiving of the PWM ramp proportional to the voltage on the VDD pin. For
instead of transmitting clock pulses. Also, the CPWM pins quit operating frequencies other than 333kHz, the frequency can be
driving the PWM capacitor in the slave units. Note that for approximated by the following equation:
optimum performance, all slave units should be located within a
1
few inches of the master unit. Frequency =
(0.577)( RPWM )(CPWM ) + 320ns
APPLICATION

Rev. 1.1,2003-06-10
P RODUCTION
CHARACTERISTIC CURVES
dx=-18.20 W dy=-0.17812 %
100 FIGURE 2 – THD+N VS. OUTPUT POWER
50
20
10
2
VIN = 15V
1 fIN = 1kHz
0.5
RL = 4Ω
THD+N (%)
0.24563
0.2
0.1
0.06751
0.05
0.02
0.01
0.005
0.002
0.001
100m 200m 500m .91611 2 5 10 19.12
20 50 100
Output Power (W)
dx=58.73 W dy=0.47633 %
50
20
10
5
2
VIN = 25V
1 fIN = 1kHz
0.5
0.53924 RL = 4Ω
THD+N (%)
0.2
0.1
0.0629
0.05
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1 1.225 2 5 10 20 5059.95 100
Output Power (W)
dx=-36.99 W dy=-0.22386 %
50
20
10
5
2
1 VIN = 15V
0.5 fIN = 1kHz
THD+N (%)
0.26783
0.2 RL = 2Ω
0.1
0.05
0.04397
GRAPHS
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1 1.252 2 5 10 20 38.24 50 100
Output Power (W)

Rev. 1.1,2003-06-10
P RODUCTION
CHARACTERISTIC CURVES (CONTINUED)
dx=108.8 W dy=0.48800 %
50
20
10
5
2
1 VIN = 25V
0.5
0.53924 fIN = 1kHz
THD+N(%)
0.2 RL = 2Ω
0.1
0.05
0.05123
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1.136
1 2 5 10 20 50 109.9
100 200 300
Output Power (W)
dx=-4.8988 kHz dy=-0.17080 %

100
FIGURE 6 – THD+N VS. FREQUENCY
50
20
10
5
2
1
0.5
VIN = 15V
RL = 4Ω
THD+N (%)
0.2
0.19402
0.1 PO = 1WRMS
0.05
0.02322
0.02
0.01
0.005
0.002
0.001
20 50 100126.2 200 500 1k 2k 5.025k
5k 10k 20k
Frequency (Hz)
dx=-4.8988 kHz dy=-0.11937 %

100 FIGURE 7 – THD+N VS. FREQUENCY
50
20
10
5
2
1 VIN = 25V
0.5
RL = 4Ω
THD+N (%)
0.2
0.1798 PO = 1WRMS
0.1
0.06044
0.05
0.02
GRAPHS
0.01
0.005
0.002
0.001
20 50 100126.2 200 500 1k 2k 5.025k
5k 10k 20k
Frequency (Hz)

Rev. 1.1,2003-06-10
P RODUCTION
dx=-17.869 kHz dy=-0.155 dB
+10
FIGURE 8 – FREQUENCY RESPONSE
+8
+6
+4
+2
VIN = 15V
Voltage Amplification (dBr)
+0 RL = 4Ω
-0.965
-1.119
-2 PO = 1WRMS
-4
-6
-8
-10
10 18.220 50 100 200 500 1k 2k 5k 10k 17.8875k
20k 50k 80k
Frequency (Hz)
dx=-17.869 kHz dy=+0.170 dB

+10 FIGURE 9 – FREQUENCY RESPONSE
+8
+6
+4
+2 VIN = 25V
Voltage Amplification (dBr)
+0
RL = 4Ω
-1.436
PO = 1WRMS
-1.606-2
-4
-6
-8
-10
10 18.220 50 100 200 500 1k 2k 5k 10k 17.8875k
20k 50k 80k
Frequency (Hz)
dx=-2.9880 kHz dy=+3.205 dB

+10 FIGURE 10 – NOISE FLOOR FFT
+0
-10
-20
-30
-40
-50
VIN = 15V
dBV
-60
-70
RL = 4Ω
-80 10Hz – 22kHz Bandwidth
-90 A-weighted
-94.916
-100
-98.12
GRAPHS
-110
-120
-130
-140
-150
20 50 100 200 500 .973932k
1k 2k 3.96192k 5k 10k 20k
Frequency (Hz)

Rev. 1.1,2003-06-10
P RODUCTION
dx=-2.9880 kHz dy=-1.969 dB
+10
FIGURE 11 – NOISE FLOOR FFT
+0
-10
-20
-30
-40
-50
-60
VIN = 25V
RL = 4Ω
dBV
-70
-80
10Hz – 22kHz Bandwidth
-90
-94.11
-96.079
-100
A-Weighted
-110
-120
-130
-140
-150
20 50 100 200 500 .973932k
1k 2k 3.96192k5k 10k 20k
Frequency (Hz)
90% FIGURE 12 – EFFICIENCY VS. OUTPUT

POWER
85%
80%
75%
Efficency (%)
70% VIN = 15V

65% fIN = 1kHz
60%
55%
50%
45%
0 5 10 15 20 25 30
Output Power (W)
8Ω 4Ω 2Ω
Power Supply Rejection Ratio (PSRR) FIGURE 13 – POWER SUPPLY REJECTION

RATIO (PSSR)
0
-10
-20
-30
Amplitude (dB)
-40 PO = 1WRMS
-50 RL = 4Ω
GRAPHS
-60
-70
-80
-90
-100
10 100 1000 10000 100000
Frequency (Hz)
15V+1,Left 15V+1,Right 15V-1,Left 15V-1,Right

Rev. 1.1,2003-06-10
P RODUCTION
APPLICATION
LISN
R16
Q1
LFBK+
R8
24.3K 1% C25
220pF
5.1/1W
JP1
Vcc Vcc Vcc L1
2 Vcc Vcc
1 OUTL+
PGND + C1 R6 LISN
Teminal 2 1000µF C2 0.020/1W
PGND 25V 0.1uF/25V R9 15uH
R20
Q2 C29 15/1W
5.1/1W 0.68uF/50V
LFBK- PGND
LFBK+
Q3
R10
U1 Vcc
R1 10k C30
1 44 C15 5.1/1W 0.68uF/50V C31
C7 100pF LFAOUT LFBK- 10uF/25V 0.47uF/50V
2 43 C16 +
CPWM LFBK+ 0.1uF/25V L2
3 42 PGND
RPWM LISN OUTL-
C9 18pF
R5 34.8k 1% 4 41
_LMUTE VDD C17 4.7uF/25V,TANT 15uH
5 40 Vcc R17
GND
LEAOUT CN C18 R11

LFBK-
R2 56.2k 1% C10 150pF 6 39 +47uF/25V
LEAIN PVDD C19
7 38 0.1uF/25V PGND Q4 24.3K 1% C26
VREF PGND 5.1/1W 220pF
+
C13 1uF/10V,TANT 8 37 LN+

CLOCK LN+
9 36 LP+
C14 0.1uF/25V GND LP+
10 35 LP-
C3 0.47uF V25 LP-
LIN+ 11 34 LN-
LIN+ LIN+ LN-
LIN- 12 33 RN-
LIN- LIN- RN-
C4 0.47uF 13 32 RP- R18
C5 0.47uF LAMPOUT RP- Q5
RIN+ 14 31 RP+ RFBK-
RIN+ RIN+ RP+ R12
RIN- 15 30 RN+ 24.3K 1% C27
RIN- RIN- RN+ 220pF
C6 0.47uF 16 29 PGND
RAMPOUT PGND C20 4.7uF/25V,TANT 5.1/1W
17 28
SLEEP SLEEP CP C21 L3
+
18 27 47uF/25V
STATUS PVDD OUTR-
C22
19 26 0.1uF/25V
_MUTE _RMUTE NC R13 15uH
+
20 25 Vcc
R4 56.2k 1% C12150pF REAIN RISN R21
21 24 Q6 C32 15/1W
REAOUT RFBK+ 5.1/1W 0.68uF/50V
22 23
RFAOUT RFBK-
C11 18pF
PGND
LX1721-01CDB
R3 10k
Q7
R14
RFBK+
RFBK-
C33
5.1/1W 0.68uF/50V C34
0.47uF/50V
L4
OUTR+
Vcc 15uH
Vcc R19
APPLICATION
R15
RISN RFBK+
R7
0.020/1W
Q8 24.3K 1% C28
5.1/1W 220pF
RISN
GND PGND
FIGURE 14 – TYPICAL CLASS-D STEREO SWITCHING AMPLIFIER CIRCUIT APPLICATION

Rev. 1.1,2003-06-10
P RODUCTION
MECHANICAL DIMINSIONS
DB 44-Pin Quarter Size Outline Package (QSOP)
MILLIMETERS INCHES
44 23 Dim
MIN MAX MIN MAX
A 2.44 2.64 0.096 0.104
B 0.28 0.51 0.011 0.020
R C 0.23 0.32 0.091 0.0125
E P D 17.73 17.93 0.698 0.706
E 7.40 7.60 0.291 0.299
F 0.80 BSC 0.0315 BSC
G 0.10 0.30 0.004 0.012
1 22
L 0.40 1.27 0.016 0.050
M 0° 8° 0° 8°
P 10.11 10.51 0.396 0.414
B F
R 0.63 0.89 0.025 0.035
ZD
ZD 0.51 REF 0.033 REF
D *LC - 0.10 - 0.004
E
* Lead Coplanarity
A
C
G L
M
Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.15mm (.006”) on any side. Lead dimension shall not include
solder coverage.
MECHANICALS

Rev. 1.1,2003-06-10
P RODUCTION
NOTES
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and

is current as of publication date. This document may not be modified in any way without the
express written consent of Microsemi. Product processing does not necessarily include testing of
all parameters. Microsemi reserves the right to change the configuration and performance of the
product and to discontinue product at any time.

Rev. 1.1,2003-06-10
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

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AudioMAX™ LX1721 / 1722

I N T E G R A T E D P R O D U C T S Class-D Stereo Power Amplifier Controller

DESCRIPTION KEY FEATURES

PACKAGE ORDER INFO

VDD Plastic QSOP

Copyright  2001 Microsemi Page 1

THERMAL DATA PACKAGE PIN OUT

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 50°C/W RPWM LISN

Junction Temperature Calculation: TJ = TA + (PD x θJA).

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FUNCTIONAL PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (PVDD, VDD) ............................................................................................................................. -0.3V to 30V

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ELECTRICAL CHARACTERISTICS (CONTINUED)

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RPW M 3 OSC CLK

FIGURE 1 – LX1721 / 22 SIMPLIFIED BLOCK DIAGRAM (LEFT CHANNEL CIRCUIT SHOWN)

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Output Power (W)

Output Power (W)

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CHARACTERISTIC CURVES (CONTINUED)

dx=-4.8988 kHz dy=-0.17080 %

dx=-4.8988 kHz dy=-0.11937 %

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CHARACTERISTIC CURVES (CONTINUED)

dx=-17.869 kHz dy=+0.170 dB

dx=-2.9880 kHz dy=+3.205 dB

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CHARACTERISTIC CURVES (CONTINUED)

90% FIGURE 12 – EFFICIENCY VS. OUTPUT

70% VIN = 15V

Power Supply Rejection Ratio (PSRR) FIGURE 13 – POWER SUPPLY REJECTION

15V+1,Left 15V+1,Right 15V-1,Left 15V-1,Right

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LEAOUT CN C18 R11

C13 1uF/10V,TANT 8 37 LN+

FIGURE 14 – TYPICAL CLASS-D STEREO SWITCHING AMPLIFIER CIRCUIT APPLICATION

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PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and

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Datasheets for electronics components.

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