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11, NOVEMBER 2000

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SPICE Models for Flicker Noise in n-MOSFETs from Subthreshold to Strong Inversion
Dingming Xie, Mengzhang Cheng, and Leonard Forbes

AbstractThe two main sources of low-frequency flicker noise are mobility fluctuations and number fluctuations. Our experiments on NMOS noise measurements were done from subthreshold to saturation region of operation for both long-channel (5 m) and short-channel (as small as 0.6 m) NMOS transistors. The results suggest that for both types that in the saturation region, the flicker noise is due to the surface state effect and the noise equations, NLEV 2 and 3, in SPICE, HSPICE, and PSPICE are most appropriate. For short-channel devices, due to the effects of velocity saturation and the resulting nonlinear transconductance ( ) variation with gate bias voltage, the input-referred voltage noise increases as the gate-source voltage increases instead of staying constant as it does for long-channel devices. In the subthreshold region, the input-referred voltage noise decreases drastically as the gate-source voltage increases for both long-channel and short-channel NMOS devices. Simulations have been done using PSPICE and HSPICE, with noise level (NLEV) 3 and device model level 3 and BSIM 3.2 and 3.3. The results from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICE level 3 compare favorably with the measured noise phenomena for the short-channel and long-channel NMOS devices, respectively.

Index TermsBSIM 3.3, drain current noise, HSPICE, input-referred noise, measurement, NMOSFET, 1/ noise, PSPICE, saturation, simulation, subthreshold.

I. INTRODUCTION LICKER noise is also known as 1/ noise, because the noise spectral density is inversely proportional to frequency. It is a major noise source in silicon MOSFETs, especially in the low-frequency range, so in order to improve the MOS circuits dynamic range and get better circuit performance, a circuit designer must be able to understand the physical origin and model the behavior of the flicker noise. Unfortunately, there is no universally accepted theory for the source of the flicker noise although a lot of work has been done since 1957 [1][4] including that of our previous companion paper [42]. The carrier density fluctuation model, also called McWhorter number fluctuation model, attributes that the flicker noise to the tunnelling of free-charge carriers into oxide traps close to the Si-SiO interface. The input referred voltage noise is independent of the gate bias voltage and the magnitude of the noise spectra is proportional to the interface trap density. This assumes and is of course only true if the density of inter-

face/oxide traps is constant with the Fermi level position. Experimental data reveals that the slope of the 1/ noise spectra varies from 0.7 to 1.2, instead of being exactly one. The mobility fluctuation model, also called Hooge mobility fluctuation model, postulates that the stochastic nature of carrier scattering events cause the low-frequency noise. It has a gate bias voltage dependence of the input-referred voltage noise. Inconsistent experiment results have been published for both NMOS and PMOS devices. Different models have thus been introduced into different versions of SPICE (SPICE, HSPICE, and PSPICE) for the 1/ noise of MOSFETs. There is also no suggestion as to which equation is more appropriate for either NMOS or PMOS devices, nor under what kind of condition it is appropriate to use, the long-channel or short-channel models. Our previous paper has simply showed that in saturation region, the flicker noise in the short-channel (0.6 m) NMOS transistors is due to the McWhorter number fluctuation model, and a good match between the SPICE simulations with the NLEV 2 and 3 noise equation and the measurements had been achieved. In this work we try to more carefully ascertain which model is most appropriate for both long-channel (5 m) and shortchannel (1.2- m and 0.6 m) NMOS transistors under both subthreshold and saturation operating conditions. Section II explains how we experimentally measure the flicker noise. Section III shows the PSPICE simulation for the flicker noise by using a model based on the experimental results. Sections IV and V give the results and conclusions, respectively.

II.

-MOSFET NOISE MEASUREMENT

Manuscript received March 15, 2000; revised May 18, 2000. This paper was recommended by Associate Editor W. Schoenmaker. The authors are with the Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331-3211 USA. Publisher Item Identifier S 0278-0070(00)09152-1.

The work was initially addressed at large micrometer size NMOS devices (5- m channel length) experimentally and by simulation in saturation region, then moved on to the more difficult problems of sub-micrometer devices (0.6- m and 1.2- m channel length) and subthreshold models. The experimental measurement setup has been described in our previous paper. The flicker noise at 1 Hz measured using an automated system and the noise measured at 1 kHz by an analog system have been compared to check the accuracy of the measurements. Please refer to [42] for details. The NMOS transistors to be measured are: 1) long-channel transistors with 120 m, 5 m, VTO 1.4 V and 1050 ; 2) short-channel transistors, including 1.2 m ones with 30.8 m, 1.2 m, VTO 0.7 V and 100 , and 0.6 m ones with 30.8 m, 0.6 m, VTO 0.7 V and 100 .

02780070/00$10.00 2000 IEEE

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Fig. 1.

Measured and simulated dc characteristics of the 5-m NMOS transistors. SPICE level 3 to simulate when T

= 1050 and KP = 22 A/V .

Fig. 2. Measured and simulated dc characteristics of the 0.6-m NMOS transistors. PSPICE level 7 (BSIM 3.3) to simulate when T A/V .

= 95 and KP = 50

III.

-MOSFET NOISE SIMULATION

IV. RESULTS AND DISCUSSIONS Both long-channel ( 5.0 m) and short-channel devices 1.2 m and 0.6 m) have been measured in both the satu( ration and the subthreshold regions of operation. Part of the results and explanation can be referred to Figs. 2, 3 in [42]. The SPICE simulations show that the device model level 3 is more appropriate for the long-channel transistors (see Fig. 1), while level 7 in PSPICE version 8.0, i.e., BSIM 3.3 is most appropriate to model the dc characteristics of the shortchannel devices (shown in Fig. 2 for 0.6- m NMOS only). The 1050 and 22 A/V for parameters used are: 95 and 50 A/V 5- m NMOS devices; and for both 1.2- m and 0.6- m NMOS devices. As we will see later, the measured input-referred noise results shows that the

Device model levels, level 3, BSIM3.2 (i.e., level 6 in PSPICE and level 47 in HSPICE) and BSIM 3.3 (i.e., level 7 in PSPICE) are tried for long-channel and short-channel devices, respectively, to fit their experimental dc characteristics, including the , and the transconductance, . The paramedrain current, , and the ters in the models, such as the oxide thickness, , are adjusted for the intrinsic transconductance parameter, best match. Once the appropriate model is found for each individual device, the noise characteristics can be simulated according to the noise experimental results using the appropriate noise equation selector (NLEV, or NOIMOD), flicker noise exponent (AF) and coefficient (KF) in SPICE (see Appendix for details about the device models and noise models).

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Fig. 3. Simulated and measured NMOS drain current noise versus absolute gate-source voltage in the saturation region. L f 1 Hz.

= 5.0, 1.2, and 0.6 m, respectively.

Fig. 4. Simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage in the saturation region. respectively. f 1 Hz.

L = 5.0, 1.2, and 0.6 m,

noise model, NLEV 3 with AF 1 in SPICE simulation is most appropriate. Thus, the measured noise results have been compared to the surface state model for noise in SPICE, NLEV 3 with AF 1, using the device model level 3 for the long-channel, 5- m devices, and the BSIM 3.3 (level 7 in PSPICE version 8.0) for the short-channel, 1.2- m and 0.6- m devices. The KF value is 1.05 -23 V F for the 5- m NMOS devices, and 1.0 -24 V F for the 1.2- m and 0.6- m NMOS devices. Within the same process and technology, in our case for the 0.6 and 1.2 micrometer devices the average noise increases for smaller device lengths.

Fig. 3 shows the simulated and measured NMOS drain current noise versus absolute gate-source voltage in the saturation region for 5.0, 1.2, and 0.6 m, respectively, at frequency of 1.0 Hz. It shows that the shorter the NMOS transistor channel, the larger the drain current noise. Fig. 4 shows the corresponding simulated and measured NMOS input-referred voltage noise in the saturation region. For the simple case of long-channel devices, the transconductance is a linear function of gate voltage and so the input referred noise stays constant. For short-channel devices, however, due to the velocity saturation of carriers in the channel, the transconductance does not increase linearly with gate voltage bias.

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Fig. 5.

Short-channel effect on 0.6 m-NMOSFET transconductance.

Fig. 6. Different SPICE models used to simulated the drain current noise for the 0.6-m short-channel NMOS transistors in the saturation region. f

= 1 Hz.

Considering the presence of velocity saturation effects, the drain current of MOSFET working in situation region is (1)

, ( , electric field) and has the dimension where . It can be shown that the transconductance under shortchannel effects is

(2)

So, the transconductance, , is no longer linear with the gate . voltage, Fig. 5 shows the transconductance values obtained by simulation, measurement and analytical calculation for 0.6 m-NMOS devices over a range of gate bias, which demonstrates that the transconductances increase more slowly with increasing gate bias. This nonlinearity of the transconductance causes the input referred voltage noise at the gate to increase with increasing gate bias in the saturation region. Note that HSPICE level 49 does not use the BSIM 3.3 noise model, for input referred noise voltage. It appears to be calculated using a transconductance which changes linearly with gate voltage even for submicrometer devices. Figs. 6 and 7 show that the HSPICE BSIM 3.2 (level 47) and PSPICE BSIM 3.2 (level 6) give almost the same results as that of HSPICE (level 49). Although they can approximately

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Fig. 7. 1 Hz.

Different SPICE models used to simulated the input-referred voltage noise for the 0.6-m short-channel NMOS transistors in the saturation region. f

Fig. 8.

Analog measured 1.2-m NMOS noise to determine channel width effect. W

=30.8 m and W = 2 3 30.8 m, at 1 KHz in saturation region.

simulate the measured drain current noises shown in Fig. 6, they can not show that the input referred gate voltage noise increases proportionally with increasing gate bias as shown in Fig. 7. Fig. 8 shows some analog measurements of the input-referred 1.2 m) at 1 kHz in voltage noise of NMOS transistors ( the saturation region to determine the-channel width effect. The tendency of noise to decrease with width, , is consistent with the NLEV 2 and 3 or surface state model. So, in conclusion, for NMOS devices in saturation region, the flicker noise is due to the number fluctuation model, and the NLEV 2 and 3 equation seems to be the most appropriate noise model to simulate the flicker noise for both long-channel and short-channel devices.

When in the subthreshold region (also called weak inversion), the gate potential applied in MOSFET ( ) is less than the threshold voltage ( ), the channel charge and the depletion region charge in the MOSFET device are both affected by the applied gate voltage [17]. The MOSFET transistor can thus work similar to a bipolar transistor because the electrons in the source region of an NMOS transistor can surmount the potential barrier to the -type substrate and get into the channel region. Its characteristics can be defined as

(3)

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Fig. 9. Simulated and measured NMOS drain current noise versus absolute gate-source voltage in the subthreshold region. L f 1 Hz.

= 5.0, 1.2, and 0.6 m, respectively.

Fig. 10. Simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage in the subthreshold region. L respectively. f 1 Hz.

= 5.0, 1.2, and 0.6 m,

So, the transconductance, , is an exponential function of , in subthreshold region, this will be reflected gate voltage, in the input referred voltage noise. Fig. 9 shows the simulated and measured NMOS drain current noise versus absolute gate-source voltage in the sub5.0, 1.2, and 0.6 m, respectively. threshold region for Fig. 10 shows the corresponding simulated and measured NMOS input-referred voltage noise in the subthreshold region. The input referred voltage noise at the gate increases sharply as , is the gate voltage decreases since the transconductance, an exponential function of gate voltage in subthreshold region. The level-3 model does not have an appropriate subthreshold

model for long-channel transistors, and the BSIM 3.3 model also does not work for long-channel devices, so no simulation can be done for 5- m-long-channel devices. In conclusion, for NMOS devices in subthreshold region, the input referred voltage noise is larger than that of saturation region, and it decreases drastically when increasing the gate bias voltage. It seems that the NLEV 2 and 3 equation can still predict the noise tendency well for the short-channel NMOS devices. Figs. 11 and 12 give a summary of the results for both the input referred mean square noise voltage at the gate and the mean square drain current noise for both regions of operation and both types of devices.

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Fig. 11. Summary of simulated and measured NMOS drain current noise versus absolute gate-source voltage from subthreshold to saturation region. L 1.2, and 0.6 m, respectively. f 1 Hz.

= 5.0,

Fig. 12. Summary of simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage from subthreshold to saturation region. L 5.0, 1.2, and 0.6 m, respectively. f 1 Hz.

V. CONCLUSION For long-channel NMOS ( 5 m), the input-referred gate) is independent of gate bias ( ), which voltage noise ( shows the surface state model and the noise model (NLEV 2 and 3) in SPICE is more appropriate. SPICE (level 3) can predict the long-channel NMOS noise performance very well in saturation region, but not in subthreshold region, and also cannot be used to simulated the short-channel NMOS noise performance. 0.6 and 1.2 m), the For short-channel NMOS devices ( ) is dependent on gateinput-referred gate-voltage noise (

source voltage ( ), increasing proportionally as increase, which is due to the nonlinearity of the transconductance ( ) variation with gate bias. These devices can be modeled with the BSIM 3.3 model (level 7 in PSPICE version 8.0) and the same noise model (noimod 1 which is approximately the same as NLEV 2 and 3 in SPICE) is also appropriate. BSIM 3.3 in PSPICE version 8.0 can predict the short-channel NMOS noise performance in both the saturation and the subthreshold region, but does not work for long-channel NMOS devices. HSPICE level 49 does not use the BSIM 3.3 noise equations. Note that PSPICE ver 8.0 and ver 9.1 have completely different 1, only the one in PSPICE ver 8.0 equations for noimod

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TABLE I SPICE EXPRESSIONS FOR MOSFET FLICKER NOISE SIMULATION

which is similar to NLEV 2 or 3 is relevant to NMOS devices. NMOS devices are best described by the NLEV 2 or 3 models. These models are applicable only to NMOS and not to PMOS devices, the latter appear to be described by a different model which will be described in another manuscript. APPENDIX A. Detailed Explanation for Table I 1) The HSPICE Manual Problem for the Default Noise Model in Level 49 (BIM 3.3): The HSPICE manual indicates

that the default noise model in level 49 (BSIM 3.3) is NLEV 2. We think it should be NLEV 0 according to the simulation results as follows: For example, using the same dc and noise parameters in HSPICE level 49 for the NMOS flicker noise simula95 m, VTO 0.7 V, 50 , tion, , 0.6 m, 30.8 m, if in setting , to be 3.0 V, when we define NLEV 2, the the gate bias, simulated mean square current noise ( ) is A Hz

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when we define NLEV ) is noise (

0, the simulated mean square current

A Hz

when we do not define NLEV, the simulated mean square current noise ( ) is A Hz

Here, we can see that the current noise obtained from the default noise model is the same as the current noise obtained from the noise model, NLEV 0. The default noise model is NLEV 0 for HSPICE level 49 (BSIM 3.3). 2) The BSIM 3.3 Manual Problem for the Expression in PSPICE ver 8.0 Level 7: The BSIM 3.3 manual refers the noise equation selector, NOIMOD 1, to the noise equation, 0. We think the NOIMOD 1 should refer to the NLEV noise equation, NLEV 2 and 3. The detailed explanation is as following: For example, if the parameters for the 0.6- m NMOS transistor used in the PSPICE version 8.0 level 7 simulation are: m, , 0.6 m, 30.8 m. When 2.0 V, the simulated dc characteristics are - A - Siemens

NLEV 0. PSPICE ver 9.1 level 7 (BSIM 3.3) does in fact use the NLEV 0 equation for NOIMOD 1. 3) Confirmation of the Default Expression in the Standard Noise Model in SPICE: The HSPICE level 3 and level 47 (BSIM 3.2), and PSPICE level 3 and level 6 (BSIM 3.2) all use the standard noise model for flicker noise simulations, and all the default expressions in them are referred to NLEV 2. The following gives confirmation of the NELV 2 default model in PSPICE level 6. The parameters for the 0.6- m NMOS transistor used in 95 -10 m, the PSPICE level 6 simulation are: 1.0 -24, 0.6 m, 30.8 m. We also assume that the ) and the effective channel length effective channel width ( ) are about same to the channel width ( ) and the channel ( length ( ), respectively. 1.0 V, the simulated dc characteristics are as a) When follows: - A - Siemens

At frequency of 1.0 Hz, the simulated drain current 7.96 -17 A /Hz. For NLEV 2 and 3 noise is:

A Hz b) When follows: -

At frequency of 1.0 Hz, the simulated drain current noise, 1, is: upon setting the noise equation selector, NOIMOD A /Hz. ) and Now let us assume that the effective channel width ( ) are about same as the channel the effective channel length ( width ( ) and the channel length ( ), respectively, and approximately calculate the mean square drain current noise using the noise equations provided in SPICE, NELV 0 and NELV 2 and 3: For NLEV 0 A Hz For NLEV 2 and 3 A Hz

A Hz

2.0 V, the simulated dc characteristics are as

- A

- Siemens

At frequency of 1.0 Hz, the simulated drain current noise 2.55 -16 A /Hz. For NLEV 2 and 3 is:

A Hz -

A Hz

A Hz -

A Hz

c) When follows:

4.0 V, the simulated dc characteristics are as

- A

- Siemens

So, by comparing with these three drain current noise values, we find that the drain current noise simulated by PSPICE version 8.0 level 7 (BSIM 3.3) with NOIMOD 1 is closest to the one calculated by using the NLEV 2 and 3 noise equation, and they are both much smaller than that one calculated from the noise equation, NLEV 0. In other words, NOIMOD 1 in PSPICE ver 8.0 (BSIM 3.3) more likely refers to the noise equation, NLEV 2 and 3, not

At frequency of 1.0 Hz, the simulated drain current noise 4.02 -16 A /Hz. For NLEV 2 and 3 is:

A Hz -

A Hz

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COMPARISON OF PSPICE LEVEL 6 WITH NLEV

= 2 SIMULATIONS OF FLICKER NOISE (NMOS: T = 95e-10 m, KF = 1.0e-24, L = 0.6 m, W = 30.8 m)

TABLE II

All the above flicker noise results are included in Table II for convenience. From it, we can see clearly that the default expression in the standard noise model in PSPICE level 6 is 2. The same conclusion applies to HSPICE level 3 NLEV and level 47, and PSPICE level 3. REFERENCES
[1] A. L. McWhorter, 1/f noise and germanium surface properties, in Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia, PA: Univ. Pennsylvania Press, 1957, pp. 207228. [2] F. N. Hooge, 1/f noise is no surface effect, Phys. Lett., vol. A-29, pp. 139140, 1969. , 1/d noise, Physica, vol. 83B, pp. 1423, 1976. [3] [4] L. K. J. Vandamme and H. M. M. Werd, 1/f noise model for MOSTs biased in nonohmic region, Solid-State Electron., vol. 23, pp. 325329, 1980. [5] H. S. Park, A. Van Der Ziel, and S. T. Liu, Comparison of two 1/f noise models in MOSFETs, Solid-State Electron., vol. 25, no. 3, pp. 213217, 1982. [6] G. Reimbold, Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion-influence of interface states, IEEE Trans. Electron Devices, vol. ED-31, pp. 11901198, Sept. 1984. [7] G. Nicollini, D. Pancini, and S. Pernici, Simulation-oriented noise model for MOS devices, IEEE J. Solid-State Circuits, vol. SC-22, pp. 12091212, Dec. 1987. [8] Y. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw Hill, 1987, p. 340. [9] A. van der Ziel, Unified presentation of 1/f noise in electronic devices: Fundamental 1/f noise sources, Proc. IEEE, vol. 76, pp. 233258, Mar. 1988. [10] K. K. Hung and P. K. Ko, A unified model for the flicker noise in metal-oxide semiconductor field-effect transistors, IEEE Trans. Electron Devices, vol. 37, pp. 654664, Mar. 1990. [11] T. Elewa and B. Boukriss, Low-frequency noise in depletion-mode DIMOX MOS transistors, IEEE Trans. Electron Devices, vol. 38, pp. 323327, Feb. 1991. [12] J. T. Hsu and J. Wang, Flicker noise in thin film depleted SOI MOSFETS, in Proc. IEEE Device Res. Conf., 1991, pp. 3031. [13] S. Fang and J. P. McVittie, Thin-oxide damage from gate charging during plasma processing, IEEE Electron Device Lett., vol. 13, pp. 288290, May 1992. [14] C. H. Cheng and C. Surya, The effect of hot-electron injection on the properties of flicker noise in n-channel MOSFETs, Solid-State Electron., vol. 36, no. 3, pp. 475479, 1993. [15] D. M. Fleetwood and P. S. Winokur, Effects of oxide traps, interface traps, and border traps on metal-oxide-semiconductor devices, J. Appl. Phys., vol. 73, no. 10, pp. 50585072, May 15 1993. [16] M. Tsai and T. Ma, 1/f noise in hot-carrier damaged MOSFETs: Effects of oxide charge and interface traps, IEEE Electron Device Lett., vol. 14, no. 5, May 1993. [17] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 1993. [18] D. M. Fleetwood, T. L. Meisenheimer, and J. H. Scofield, 1/f noise and radiation effects in MOS devices, IEEE Trans. Electron Devices, vol. 41, pp. 19531964, Nov. 1994. [19] J. Chang, A. A. Abidi, and C. R. Viswanathan, Flicker noise in CMOS transistors from subthresholds to strong inversion at various temperatures, IEEE Trans. Electron Devices, vol. 41, pp. 19651971, Nov. 1994. [20] J. H. Scofield and N. Borland, Reconciliation of different gate-voltage dependencies of 1/f noise in n-MOS and p-MOS transistors, IEEE Trans. Electron Devices, vol. 41, pp. 19461952, Nov. 1994.

[21] L. K. J. Vandamme, X. Li, and D. Rigaud, 1/f noise in MOS devices, mobility or number fluctuations, IEEE Trans. Electron Devices, vol. 41, pp. 19361944, Nov. 1994. [22] C. Hu and G. P. Li, Low-frequency noise considerations for MOSFET analog circuits, in Abst. IEEE Device Res. Conf., Charlottesville, VA, 1995, pp. 1617. [23] C. Hu, J. Zhao, G. P. Li, P. Liu, E. Worley, J. White, and R. Kjar, The effects of plasma etching induced gate oxide degradation on MOSFETs 1/f noise, IEEE Electron Device Lett., vol. 16, pp. 6163, Feb. 1995. [24] E. Simoen and C. Claeys, Correlation between the low-frequency noise spectral density and the static device parameters of silicon-on-insulator MOSFETs, IEEE Trans. Electron Devices, vol. 42, pp. 14671472, Aug. 1995. [25] M. Aoki and M. Kato, Hole-induced 1/f noise increase in MOS transistors, IEEE Electron Device Lett., vol. 17, pp. 118120, Mar. 1996. [26] J. A. Babcock, W. M. Huang, J. M. Ford, D. Ngo, D. J. Sponsor, and S. Cheng, Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-model applications, Proc. IEEE Int. Electron Device Meet., pp. 133136, 1996. [27] N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, and C. Claeys, Back and front interface related generation-recombination noise in buried-channel SOI p-MOSFETs, IEEE Trans. Electron Devices, vol. 43, pp. 417423, Mar. 1996. [28] S. S. Chen and S. C. Lin, Kink effect on subthreshold current conduction mechanism for n-channel metal-oxide-silicon devices, J. Appl. Phys., vol. 80, no. 10, pp. 58215827, Nov. 15 1996. [29] C. Hu, G. P. Li, E. Worley, and J. White, Consideration of low-frequency noise in MOSFETs for analog performance, IEEE Electron Device Lett., vol. 17, pp. 552554, Dec. 1996. [30] E. Simoen and C. Claeys, The low-frequency noise behavior of silicon-on-insulator technologies, Solid-State Electron., vol. 39, no. 7, pp. 949960, 1996. [31] HSPICE Users Manual, Meta-Software, Inc., Campbell, CA, 1996. [32] J. A. Babcock, C. E. Gill, J. M. Ford, D. Ngo, E. Spears, J. Ma, H. Liang, D. J. Spooner, and S. Cheng, 1/f noise in graded-channel MOSFETs for low-power low-cost RFICs, in Abst. IEEE Device Res. Conf., Fort Collins, CO, 1997, pp. 122123. [33] T. Boutchacha, G. Ghibando, G. Guegan, and T. Skotnicki, Low-frequency noise characterization of 0.18 m Si CMOS transistors, Microelectron Reliab., vol. 37, no. 10/11, pp. 15991602, 1997. [34] T. Boutchacha, G. Ghibando, G. Guegan, and M. Haond, Low-frequency noise characterization of 0.25 m Si CMOS transistors, J. NonCrystalline Solids, vol. 216, pp. 192197, 1997. [35] M. J. Chen and J. S. Ho, A three-parameter-only MOSFET subthreshold current CAD model considerinb back-gate bias and process variation, IEEE Trans. Computer-Aided Design, vol. 16, pp. 343352, Apr. 1997. [36] D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice. Englewood Cliffs, NJ: Prentice-Hall, 1997. [37] C. T. Liu, D. Misra, K. P. Cheung, G. B. Alers, C. P. Chang, J. I. Colonell, W. Lai, C. S. Pai, R. Liu, and J. T. Clemens, Reduced 1/f noise and gm degradation for sub-0.25 m MOSFETs with 25 50 gate oxides grown on nitrogen implanted silicon substrates, in Abst. IEEE Device Res. Conf., Fort Collins, CO, 1997, pp. 124125. [38] PSPICE Manual, Version 8.0, MicroSim Corporation, Irvine, CA, June 1997. [39] J. A. Babcock, D. K. Schroder, and Y. Tseng, Low-frequency noise in nearly-fully-depleted TFSOI MOSFETs, IEEE Electron Device Lett., vol. 19, pp. 4043, Feb. 1998. [40] C. Jakobson, I. Bloom, and Y. Nemirovsky, 1/f noise in CMOS transistors for analog applications from subthreshold to saturation, Solid-State Electron., vol. 42, no. 10, pp. 18071817, 1998. [41] T. Wang and L. P. Chiang, Characterization of various stress-induced oxide traps in MOSFETs by using a subthreshold transient current technique, IEEE Trans. Electron Devices, vol. 45, pp. 17911796, Aug. 1998. [42] D. Xie and L. Forbes, Phase noise on a 2-GHz CMOS LC Oscillator, IEEE Trans. Computer-Aided Design, vol. 19, pp. 773778, July 2000.

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Dingming Xie was born in Gaoan, China, in 1971. He received the B.S. degree in chemical engineering from Nanjing Forestry University, China, in 1992 and two M.S. degrees in electrical engineering and forest products from Oregon State University, Corvallis, in 1999 and 1998, respectively. He is now an Analog Design Engineer with Qualcomm, Inc., San Diego, CA.

Mengzhang Cheng was born in JiangSu, China, in 1956. He received the B.S. degree in automatic control engineering from Northeast Engineering University, China, in 1982 and M.S. degree in computer science in 1987. Since 1999, he has been working on the M.S. degree in electrical engineering from Oregon State University, Corvallis.

Leonard Forbes was born in Grande Prairie, AB, Canada, in 1940. He received the B.Sc. degree with distinction in engineering physics from the University of Alberta, Edmonton, AB, Canada, and received the Ph.D. degree in electrical engineering from the University of Illinois, Urbana, in 1970. He has 30 years of experience in the semiconductor industry working as an engineer, teaching and/or doing research. He is currently a Professor at Oregon State University, Corvallis, and an Adjunct Research Fellow of the Micron Advanced Research Institute, Boise, ID. He has previously taught at the University of California at Davis, the University of Arkansas, Fayetteville, and was an IBM Professor at Howard University, Washington, DC.