Technische Universitt Darmstadt FB Elektrotechnik und Informationstechnik FG Integrierte Elektronische Systeme Prof. Dr.-Ing.
Klaus Hofmann
Examination within the lecture
Circuit Building Blocks for Communication Systems
WS 2011/2012 February 23 2012
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Problem Maximum Achieved
1 25
2 25
3 24
4 26
100
Grade
Time allowed: 90min Script allowed, calculator, plus writing material All sheets of this exam must be returned
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Problem 1: Voltage regulators and converters
Given are the following circuits:
Fig 1: Circuit A
Fig. 2: Circuit B
Fig. 3: Circuit C CBBC Exam WS 2011/2012 February 23rd 2012 2/16
1-1 (5P): Name the circuits according to Fig. 1 3 . Describe the possible output voltage range w.r.t. the input voltage for each of the three circuits.
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1-2 (5P): Now look at Circuit A according to Fig. 1 and sketch the possible waveforms.
1-3 (4P): Derive a formula for the output voltage of circuit A (Fig. 1) w.r.t. Ton, T, Vdc ,
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1-4 (4P): Now take circuit C (Fig. 3) into account. Draw the equivalent circuits for the on and off case.
1-5 (4P): Derive the voltage ratio Vout/Vs and current ratio Iout/I_in_ave for the circuit according to Fig 3 (circuit C).
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1-6 (3P): Assume circuit C (Fig. 3). Further assume that the switch and the elements (inductor, capacitor, diode, transistor) are lossless / ideal. What is the power efficiency Pout/Pin for this circuit?
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Problem 2: PLL An integer-N PLL as shown in Figure 4 is used for frequency synthesis. The output frequency must range from 300MHz to 400MHz with 10MHz channel spacings. Note that there is no charge pump, the output of the phase detector is a voltage which is filtered before being applied to the VCO.
Fig. 4: Integer-N PLL
2-1 (6P): What is an appropriate choice for the reference frequency fref?
2-2 (5P): What is the range of divide values N that will be used for this choice of reference frequency?
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2-3 (7P): Derive expressions for the damping factor () and the natural frequency n of the characteristic equation of the PLL.
2-4 (7P): Based on the constraints that there must be no peaking in the frequency response (assume that this is the case for 1/2) and that n must be minimized, choose a value for the product RC. Assume hereby that KPD = 1V/rad and KVCO=150000rad/Vs.
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Problem 3: Memory Consider a DRAM chip organized as 16Mx4 with following information. This DRAM chip needs 24 address bits, whereby 11 of which are used for the columns and 13 of which are used for rows. The following timings are given: A single-word access from an already opened page takes 40 ns (cycle time) The first access on a closed page takes 110ns
3-1 (6P): Suppose a processor needs 8192x8192 (8k*8k) element array of 32 bit word, how many DRAM chips (as configured above) do we need to meet the processor requirement?
3-2 (6P): What is the peak and average bandwidth of single DRAM chip in pagemode?
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3-3 (6P): What is the total time to read the whole array elements in pagemode?
3-4 (6P): Somebody claims that the larger the row size for a DRAM is, the more alike are average and peak bandwidth (which is good, because bandwidth variation is low). What are the major disadvantages of a large row size? Name minimum two disadvantages.
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Problem 4: Miscellaneous questions
Question 4-1 4-7 (14P): Read the statements below and check the corresponding box if you think the statement is true or false. If you do not know the answer, leave the corresponding boxes unchecked. An equal penalty applies for wrong answers. Minimum achievable points for this section are 0P. Question TRUE FALSE Statement 4-1 Comparing parallel and serial data transmission protocols and systems, serial transmission suffers even more from ISI (Inter-Symbol-Interference) than parallel transmission ones. 4-2 4-3 4-4 4-5 4-6 4-7 CML (current mode logic), compared to voltage-mode CMOS is also well suited for low power applications DLL (Delay Locked Loops) or PLLs (Phase Locked Loops) can usually be switched off at very low clock frequencies. The lock time of a DLL specifies the lower limit of a waiting period before data transmission between sender and receiver is safe. Both DLLs and PLLs are sensitive to a change of the input phase. Line termination for spacially close differential wires can never be done perfectly High-Speed Integrated Circuits should always aim at the maximum possible slew rate, since the shorter the rise/fall time of the signal is, the quicker the data will arrive at the receiver side.
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4-8 (2P): Describe what is meant with the term process variation in the context of CMOS fabrication.
4-9 (2P): Have process variations gone worse with the new advanced CMOS technologies with smaller dimensions? Why or why not?
4-10 (3P): If you buy an ASIC which has a regulated power supply, what is implemented in this chip (e.g. compared to an unregulated ASIC)?
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4-11 (3P): Why do Multi-Sync Clock Delay Synchronizer circuits need a conflict detection? Why do asynchronous transmission protocols not need this? What measures should be taken to make data transmission even safer for high data rates?
4-12 (2P): Recently we have seen stacked-ASIC whereby more than 1000 TSVs (Through silicon via-Technology) have been used, even if only 100-150 pins needed to be connected between the different ASICs. Try to guess why more TSVs than really needed are in use.
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