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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO.
12, DECEMBER 2007
1367
2007 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 15
This index covers all technical items papers, correspondence, reviews, etc. that appeared in this periodical during 2007, and items from previous years that were commented upon or corrected in 2007. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the rst authors name. The primary entry includes the coauthors names, the title of the paper or other item, and its location, specied by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the rst authors name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. AUTHOR INDEX Azizi, N., Khellah, M. M., De, V. K., and Najm, F. N., Variations-Aware LowPower Design and Block Clustering With Voltage Scaling; TVLSI July 2007 746-757 B Baas, B. M., see Apperson, R. W., TVLSI Oct. 2007 1125-1134 Bahukudumbi, S., and Chakrabarty, K., Wafer-Level Modular Testing of CoreBased SoCs; TVLSI Oct. 2007 1144-1154 Bakkaloglu, B., see Li, Y., TVLSI Jan. 2007 90-103 Balasa, F., Zhu, H., and Luican, I. I., Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications; TVLSI April 2007 447-460 Banerjee, P., see Mittal, G., TVLSI Nov. 2007 1177-1190 Barcenas, R. A., see Zhao, P., TVLSI March 2007 338-345 Bashirullah, R., see Zhang, L., TVLSI Feb. 2007 231-236 Bayat-Sarmadi, S., and Hasan, M. A., On Concurrent Detection of Errors in Polynomial Basis Multiplication; TVLSI April 2007 413-426 Bayoumi, M. A., see Zhao, P., TVLSI March 2007 338-345 Benini, L., see Murali, S., TVLSI Aug. 2007 869-880 Bermak, A., see Shoushun, C., TVLSI March 2007 346-357 Bhaskaran, B., see Satagopan, V., TVLSI Oct. 2007 1155-1159 Bhunia, S., see Agarwal, A., TVLSI June 2007 660-671 Bian, S., see Saldana, M., TVLSI Aug. 2007 948-951 Brown, R., see Agarwal, K., TVLSI June 2007 613-623 Brown, S. D., see Manohararajah, V., TVLSI Aug. 2007 895-903 Burleson, W., see Maheshwari, A., TVLSI Nov. 2007 1239-1244 Bushnell, M. L., see Rao, L., TVLSI Nov. 2007 1245-1255 Bystrov, A., see Shang, D., TVLSI June 2007 720-724 C Cao, A., see Lu, R., TVLSI Jan. 2007 69-79 Cao, K., Hu, J., and Cheng, M., Wire Sizing and Spacing for Lithographic Printability and Timing Optimization; TVLSI Dec. 2007 1332-1340 Cardarilli, G. C., Pontarelli, S., Re, M., and Salsano, A., Concurrent Error Detection in ReedSolomon Encoders and Decoders; TVLSI July 2007 842-846 Carta, S., see Murali, S., TVLSI Aug. 2007 869-880 Castillo, E., Meyer-Baese, U., Garcia, A., Parrilla, L., and Lloris, A., IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores; TVLSI May 2007 578-591 Catthoor, F., see Guo, J., TVLSI Aug. 2007 941-944 Chakrabarti, C., see Li, Y., TVLSI Jan. 2007 90-103 Chakrabarty, K., see Bahukudumbi, S., TVLSI Oct. 2007 1144-1154 Chakradhar, S. T., see Arora, D., TVLSI June 2007 699-710 Champac, V., see Zenteno Ramirez, A., TVLSI May 2007 572-577 Chandra, A., see Han, Y., TVLSI May 2007 531-540 Chandrasekaran, S., see Amira, A., TVLSI March 2007 286-295 Chang, M.-C. F., see Kim, J., TVLSI Aug. 2007 881-894 Chang, S.-C., see Lin, C.-H., TVLSI Dec. 2007 1303-1310 Chang, Y.-J., and Lan, M.-F., Two New Techniques Integrated for EnergyEfcient TLB Design; TVLSI Jan. 2007 13-23 Chen, C.-H., Wei, C.-K., Lu, T.-H., and Gao, H.-W., Software-Based SelfTesting With Multiple-Level Abstractions for Soft Processor Cores; TVLSI May 2007 505-517 Chen, J.-E., see Lin, S.-P., TVLSI July 2007 767-776 Chen, J.-J., see Lin, S.-P., TVLSI July 2007 767-776 Chen, K.-H., and Chu, Y.-S., A Low-Power Multiplier With the Spurious Power Suppression Technique; TVLSI July 2007 846-850 Chen, S., Zhang, T., and Xin, Y., Relaxed K -Best MIMO Signal Detector Design and VLSI Implementation; TVLSI March 2007 328-337 Chen, T. W., see Gregg, J., TVLSI March 2007 366-376 Chen, W.-Z., and Lin, D.-S., A 90-dB
10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology; TVLSI March 2007 358-365 Chen, X., and Hsiao, M. S., An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection; TVLSI April 2007 404-412 Cheng, K.-L., see Lo, C.-Y., TVLSI May 2007 541-545
A Aaraj, N., Ravi, S., Raghunathan, A., and Jha, N. K., Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems; TVLSI March 2007 296-308 Abdollahi, A., Fallah, F., and Pedram, M., A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design; TVLSI Jan. 2007 80-89 Abramovici, M., see Emmert, J. M., TVLSI Feb. 2007 216-226 Acar, E., see Li, P., TVLSI Nov. 2007 1205-1214 Acar, E., and Ozev, S., Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup; TVLSI Jan. 2007 37-47 Achar, R., see Saraswat, D., TVLSI Jan. 2007 48-59 Afzali-Kusha, A., see Amirabadi, A., TVLSI Feb. 2007 125-134 Agarwal, A., Kang, K., Bhunia, S., Gallagher, J. D., and Roy, K., Device-Aware Yield-Centric Dual-V Design Under Parameter Variations in Nanoscale Technologies; TVLSI June 2007 660-671 Agarwal, K., see Singh, H., TVLSI Nov. 2007 1215-1224 Agarwal, K., Rao, R., Sylvester, D., and Brown, R., Parametric Yield Analysis and Optimization in Leakage Dominated Technologies; TVLSI June 2007 613-623 Agrawal, V. D., see Rao, L., TVLSI Nov. 2007 1245-1255 Ahmad, S., and Mahapatra, R. N., An Efcient Approach to On-Chip Logic Minimization; TVLSI Sept. 2007 1040-1050 Ahonen, T., see Wang, X., TVLSI Oct. 2007 1091-1100 Aitken, R. C., see Gizopoulos, D., TVLSI May 2007 493-494 Al Hashimi, B. M., see Andrei, A., TVLSI March 2007 262-275 Al-Assadi, W. K., see Satagopan, V., TVLSI Oct. 2007 1155-1159 Amira, A., and Chandrasekaran, S., Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing; TVLSI March 2007 286-295 Amirabadi, A., Afzali-Kusha, A., Mortazavi, Y., and Nourani, M., Clock Delayed Domino Logic With Efcient Variable Threshold Voltage Keeper; TVLSI Feb. 2007 125-134 Andrei, A., Eles, P., Peng, Z., Schmitz, M. T., and Al Hashimi, B. M., Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection; TVLSI March 2007 262-275 Apostolakis, A., Psarakis, M., Gizopoulos, D., and Paschalis, A., Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip; TVLSI Aug. 2007 971-975 Apperson, R. W., Yu, Z., Meeuwsen, M. J., Mohsenin, T., and Baas, B. M., A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains; TVLSI Oct. 2007 1125-1134 Arora, D., Raghunathan, A., Ravi, S., Sankaradass, M., Jha, N. K., and Chakradhar, S. T., Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC; TVLSI June 2007 699-710 Arora, D., Ravi, S., Raghunathan, A., and Jha, N. K., Architectural Support for Run-Time Validation of Program Data Properties; TVLSI May 2007 546-559 Asada, K., see Iizuka, T., TVLSI June 2007 716-720 Asadi, H., and Tahoori, M. B., Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs; TVLSI Dec. 2007 1320-1331 Asanovic, K., see Heo, S., TVLSI Sept. 2007 1060-1064 Atienza, D., see Murali, S., TVLSI Aug. 2007 869-880
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007
Cheng, M., see Cao, K., TVLSI Dec. 2007 1332-1340 Cheung, P. Y. K., see Sedcole, P., TVLSI Sept. 2007 1003-1016 Cheung, R. C. C., see Lee, D.-U., TVLSI April 2007 474-478 Cheung, R. C. C., Lee, D.-U., Luk, W., and Villasenor, J. D., Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method; TVLSI Aug. 2007 952-962 Chi, J. C., Lee, H. H., Tsai, S. H., and Chi, M. C., Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint; TVLSI June 2007 637-648 Chi, M. C., see Chi, J. C., TVLSI June 2007 637-648 Chiu, G. R., see Manohararajah, V., TVLSI Aug. 2007 895-903 Choi, J. Y., see Shin, Y., TVLSI July 2007 758-766 Choi, P., see Seo, H.-M., TVLSI Feb. 2007 227-231 Chow, P., see Shannon, L., TVLSI April 2007 377-390 Chow, P., see Saldana, M., TVLSI Aug. 2007 948-951 Chu, M., see You, C., TVLSI Sept. 2007 1051-1054 Chu, Y.-S., see Chen, K.-H., TVLSI July 2007 846-850 Clouqueur, T., see Nakamura, Y., TVLSI July 2007 790-800 Constantinides, G. A., see Sedcole, P., TVLSI Sept. 2007 1003-1016 Craig, J., see Saldana, M., TVLSI Aug. 2007 948-951 Cui, Z., see Wang, Z., TVLSI Jan. 2007 104-114 Cui, Z., see Wang, Z., TVLSI April 2007 483-488 D Dambre, J., see O'Connor, I., TVLSI Aug. 2007 927-940 Dambre, J., and Hutton, M., Guest Editorial System-Level Interconnect Prediction; TVLSI Aug. 2007 853-854 Davis, J. A., see Yamamoto, H., TVLSI June 2007 649-659 Davis, J. A., see Joshi, A. J., TVLSI Sept. 2007 990-1002 De Micheli, G., see Rosing, T. S., TVLSI April 2007 391-403 De Micheli, G., see Murali, S., TVLSI Aug. 2007 869-880 De Wilde, M., see O'Connor, I., TVLSI Aug. 2007 927-940 De, V. K., see Azizi, N., TVLSI July 2007 746-757 Dike, C. E., see Kinniment, D. J., TVLSI Sept. 2007 1028-1039 Dimitrakopoulos, G., Mavrokefalidis, C., Galanopoulos, K., and Nikolos, D., Sorter Based Permutation Units for Media-Enhanced Microprocessors; TVLSI June 2007 711-715 Dimitroulakos, G., see Galanis, M. D., TVLSI Dec. 2007 1362-1366 Doboli, A., see Kallakuri, S. S., TVLSI Feb. 2007 240-245 E Efstathiou, C., see Haniotakis, T., TVLSI April 2007 461-465 Eisley, N., see Soteriou, V., TVLSI Aug. 2007 855-868 Eles, P., see Andrei, A., TVLSI March 2007 262-275 Elgebaly, M., and Sachdev, M., Variation-Aware Adaptive Voltage Scaling System; TVLSI May 2007 560-571 Emmert, J. M., Stroud, C. E., and Abramovici, M., Online Fault Tolerance for FPGA Logic Blocks; TVLSI Feb. 2007 216-226 Endo, M., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Eom, H., see Kim, T.-H., TVLSI July 2007 821-829 Espinosa, G., see Zenteno Ramirez, A., TVLSI May 2007 572-577 F Fallah, F., see Abdollahi, A., TVLSI Jan. 2007 80-89 Feng, W., and Greene, J. W., Post-Placement Interconnect Entropy; TVLSI Aug. 2007 945-948 Feng, Z., see Li, P., TVLSI Nov. 2007 1205-1214 Foster, T. J., Lastor, D. L., and Singh, P., First Silicon Functional Validation and Debug of Multicore Microprocessors; TVLSI May 2007 495-504 Franzon, P. D., see Zhang, L., TVLSI Feb. 2007 231-236 Friedman, E. G., see Rosenfeld, J., TVLSI Feb. 2007 135-148 Friedman, E. G., see Pavlidis, V. F., TVLSI Oct. 2007 1081-1090 Fujiwara, H., see Nakamura, Y., TVLSI July 2007 790-800 G
Gallagher, J. D., see Agarwal, A., TVLSI June 2007 660-671 Gao, H.-W., see Chen, C.-H., TVLSI May 2007 505-517 Garcia, A., see Castillo, E., TVLSI May 2007 578-591 Gizopoulos, D., see Apostolakis, A., TVLSI Aug. 2007 971-975 Gizopoulos, D., Aitken, R. C., and Kundu, S., Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems; TVLSI May 2007 493-494 Glesner, M., see Pandey, S., TVLSI Oct. 2007 1111-1124 Goda, B., see You, C., TVLSI Sept. 2007 1051-1054 Golconda, P., see Zhao, P., TVLSI March 2007 338-345 Gope, D., Ruehli, A. E., and Jandhyala, V., Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm; TVLSI Jan. 2007 60-68 Goutis, C. E., see Galanis, M. D., TVLSI Dec. 2007 1362-1366 Greene, J. W., see Feng, W., TVLSI Aug. 2007 945-948 Gregg, J., and Chen, T. W., Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing; TVLSI March 2007 366-376 Gross, W. J., Kschischang, F. R., and Gulak, P. G., Architecture and Implementation of an Interpolation Processor for Soft-Decision ReedSolomon Decoding; TVLSI March 2007 309-318 Gulak, P. G., see Gross, W. J., TVLSI March 2007 309-318 Guo, J.-R., see You, C., TVLSI Sept. 2007 1051-1054 Guo, J., Papanikolaou, A., Zhang, H., and Catthoor, F., Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture; TVLSI Aug. 2007 941-944 Gupta, N., see Gupta, N., TVLSI Sept. 2007 981-989 Gupta, N., and Gupta, N., A VLSI Architecture for Image Registration in Real Time; TVLSI Sept. 2007 981-989 Gupta, P., Jha, N. K., and Lingappan, L., A Test Generation Framework for Quantum Cellular Automata Circuits; TVLSI Jan. 2007 24-36 H Han, Y., Hu, Y., Li, X., Li, H., and Chandra, A., Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit; TVLSI May 2007 531-540 Haniotakis, T., see Kagaris, D., TVLSI April 2007 488-492 Haniotakis, T., Tsiatouhas, Y., Nikolos, D., and Efstathiou, C., Testable Designs of Multiple Precharged Domino Circuits; TVLSI April 2007 461-465 Hasan, M. A., see Bayat-Sarmadi, S., TVLSI April 2007 413-426 Hatcher, G., see Lee, J., TVLSI Sept. 2007 1017-1027 He, L., see Long, C., TVLSI July 2007 830-841 Hemmert, K. S., and Underwood, K. D., Floating-Point Divider Design for FPGAs; TVLSI Jan. 2007 115-118 Heo, S., see Shin, Y., TVLSI July 2007 758-766 Heo, S., Krashinsky, R., and Asanovic, K., Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy; TVLSI Sept. 2007 1060-1064 Heron, K., see Kinniment, D. J., TVLSI Sept. 2007 1028-1039 Hobson, R. F., A New Single-Ended SRAM Cell With Write-Assist; TVLSI Feb. 2007 173-181 Hong, H.-C., A Design-for-Digital-Testability Circuit Structure for - Modulators; TVLSI Dec. 2007 1341-1350 Hsia, S.-C., and Wang, S.-H., Shift-Register-Based Data Transposition for CostEffective Discrete Cosine Transform; TVLSI June 2007 725-728 Hsiao, M. S., see Chen, X., TVLSI April 2007 404-412 Hu, J., see Venkataraman, G., TVLSI Feb. 2007 149-158 Hu, J., see Hu, S., TVLSI Oct. 2007 1067-1080 Hu, J., see Cao, K., TVLSI Dec. 2007 1332-1340 Hu, S., Li, Q., Hu, J., and Li, P., Utilizing Redundancy for Timing Critical Interconnect; TVLSI Oct. 2007 1067-1080 Hu, Y., see Han, Y., TVLSI May 2007 531-540 Huang, C.-D., Li, J.-F., and Tseng, T.-W., ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips; TVLSI Oct. 2007 1135-1143 Huang, C.-T., see Lin, C.-H., TVLSI Dec. 2007 1303-1310 Huang, C., Ravi, S., Raghunathan, A., and Jha, N. K., Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis; TVLSI Nov. 2007 1191-1204 Huang, J.-R., see Lo, C.-Y., TVLSI May 2007 541-545 Huang, W., see Lu, Z., TVLSI Feb. 2007 159-172 Hutton, M., see Dambre, J., TVLSI Aug. 2007 853-854
61
I Gafot, F., see O'Connor, I., TVLSI Aug. 2007 927-940 Galanis, M. D., Dimitroulakos, G., and Goutis, C. E., Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Recongurable System; TVLSI Dec. 2007 1362-1366 Galanopoulos, K., see Dimitrakopoulos, G., TVLSI June 2007 711-715 + Check author entry for coauthors Iizuka, T., Ikeda, M., and Asada, K., Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization; TVLSI June 2007 716-720 Ikeda, M., see Iizuka, T., TVLSI June 2007 716-720
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Ikeda, M., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Ismail, Y., see Ku, J. C., TVLSI May 2007 592-604 Ismail, Y., see Ku, J. C., TVLSI Aug. 2007 963-970 Iwasaki, H., Naganuma, J., Nitta, K., Nakamura, K., Yoshitome, T., Ogura, M., Nakajima, Y., Tashiro, Y., Onishi, T., Ikeda, M., Minami, T., Endo, M., and Yashima, Y., Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level; TVLSI Sept. 2007 1055-1059 J Jandhyala, V., see Gope, D., TVLSI Jan. 2007 60-68 Jasionowski, B. J., Lay, M. K., and Margala, M., A Processor-In-Memory Architecture for Multimedia Compression; TVLSI April 2007 478-483 Jayakumar, N., and Khatri, S. P., A Predictably Low-Leakage ASIC Design Style; TVLSI March 2007 276-285 Jha, N. K., see Gupta, P., TVLSI Jan. 2007 24-36 Jha, N. K., Editorial; TVLSI March 2007 249-261 Jha, N. K., see Aaraj, N., TVLSI March 2007 296-308 Jha, N. K., see Luo, J., TVLSI April 2007 427-437 Jha, N. K., see Potlapally, N. R., TVLSI April 2007 465-470 Jha, N. K., see Lingappan, L., TVLSI May 2007 518-530 Jha, N. K., see Potlapally, N. R., TVLSI May 2007 605-609 Jha, N. K., see Arora, D., TVLSI May 2007 546-559 Jha, N. K., see Arora, D., TVLSI June 2007 699-710 Jha, N. K., see Huang, C., TVLSI Nov. 2007 1191-1204 Jiang, C.-P., see Lin, C.-H., TVLSI Dec. 2007 1303-1310 Jiang, Y.-C., and Wang, J.-F., Temporal Partitioning Data Flow Graphs for Dynamically Recongurable Computing; TVLSI Dec. 2007 1351-1361 Jin, J., and Tsui, C., Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition; TVLSI Oct. 2007 11721176 Joshi, A. J., Lopez, G. G., and Davis, J. A., Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing; TVLSI Sept. 2007 990-1002 K Kagaris, D., and Haniotakis, T., A Methodology for Transistor-Efcient Supergate Design; TVLSI April 2007 488-492 Kahng, A. B., Liu, B., and Wang, Q., Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement; TVLSI Aug. 2007 904-912 Kakarla, S., see Satagopan, V., TVLSI Oct. 2007 1155-1159 Kallakuri, S. S., and Doboli, A., Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes; TVLSI Feb. 2007 240-245 Kang, K., see Agarwal, A., TVLSI June 2007 660-671 Keane, J., see Kim, T.-H., TVLSI July 2007 821-829 Keung, K.-M., Manne, V, and Tyagi, A., A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump; TVLSI July 2007 733-745 Khandelwal, V., and Srivastava, A., A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations; TVLSI Feb. 2007 206-215 Khatri, S. P., see Jayakumar, N., TVLSI March 2007 276-285 Khellah, M. M., see Azizi, N., TVLSI July 2007 746-757 Kim, C. H., see Kim, T.-H., TVLSI July 2007 821-829 Kim, D., see Seo, H.-M., TVLSI Feb. 2007 227-231 Kim, D.-S., see Seo, H.-M., TVLSI Feb. 2007 227-231 Kim, H.-O., see Shin, Y., TVLSI July 2007 758-766 Kim, J., Verbauwhede, I., and Chang, M.-C. F., Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication; TVLSI Aug. 2007 881-894 Kim, S.-D., see Seo, H.-M., TVLSI Feb. 2007 227-231 Kim, T.-H., Keane, J., Eom, H., and Kim, C. H., Utilizing Reverse ShortChannel Effect for Optimal Subthreshold Circuit Design; TVLSI July 2007 821-829 Kinniment, D. J., Dike, C. E., Heron, K., Russell, G., and Yakovlev, A. V., Measuring Deep Metastability and Its Effect on Synchronizer Performance; TVLSI Sept. 2007 1028-1039 Klumperink, E. A. M., see Mensink, E., TVLSI April 2007 438-446 Kocan, F., see Meyer, J., TVLSI Feb. 2007 182-195 Koelmans, A., see Shang, D., TVLSI June 2007 720-724 Koh, C.-K., see Lu, R., TVLSI Jan. 2007 69-79 Kraft, R. P., see You, C., TVLSI Sept. 2007 1051-1054 Krashinsky, R., see Heo, S., TVLSI Sept. 2007 1060-1064 Kschischang, F. R., see Gross, W. J., TVLSI March 2007 309-318 + Check author entry for coauthors
Ku, J. C., and Ismail, Y., Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits; TVLSI Aug. 2007 963-970 Ku, J. C., Ozdemir, S., Memik, G., and Ismail, Y., Thermal Management of On-Chip Caches Through Power Density Minimization; TVLSI May 2007 592-604 Kuang, W., see Zhao, P., TVLSI March 2007 338-345 Kumar, P. R., and Sridharan, K., VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment; TVLSI Jan. 2007 118-123 Kundu, S., see Gizopoulos, D., TVLSI May 2007 493-494 Kursun, V., see Liu, Z., TVLSI Dec. 2007 1311-1319 L Lach, J., see Lu, Z., TVLSI Feb. 2007 159-172 Lai, J.-T., Wu, A.-Y., and Lee, C.-H., Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs; TVLSI February 2007 236-240 Lan, M.-F., see Chang, Y.-J., TVLSI Jan. 2007 13-23 Lastor, D. L., see Foster, T. J., TVLSI May 2007 495-504 Lay, M. K., see Jasionowski, B. J., TVLSI April 2007 478-483 Lee, C.-H., see Lai, J.-T., TVLSI February 2007 236-240 Lee, C.-L., see Lin, S.-P., TVLSI July 2007 767-776 Lee, D.-U., see Cheung, R. C. C., TVLSI Aug. 2007 952-962 Lee, D.-U., Cheung, R. C. C., and Villasenor, J. D., A Flexible Architecture for Precise Gamma Correction; TVLSI April 2007 474-478 Lee, H. H., see Chi, J. C., TVLSI June 2007 637-648 Lee, J., Hatcher, G., Vandenberghe, L., and Yang, C.-K. K., Evaluation of FullyIntegrated Switching Regulators for CMOS Process Technologies; TVLSI Sept. 2007 1017-1027 Lee, R. B., see Potlapally, N. R., TVLSI April 2007 465-470 Lee, R. B., see Potlapally, N. R., TVLSI May 2007 605-609 Lee, Y.-S., see Seo, H.-M., TVLSI Feb. 2007 227-231 Lekatsas, H., see Xie, Y., TVLSI Aug. 2007 975-980 Li, B., see Soteriou, V., TVLSI Aug. 2007 855-868 Li, H., see Han, Y., TVLSI May 2007 531-540 Li, J.-F., see Huang, C.-D., TVLSI Oct. 2007 1135-1143 Li, P., see Ye, X., TVLSI Aug. 2007 913-926 Li, P., see Hu, S., TVLSI Oct. 2007 1067-1080 Li, P., Feng, Z., and Acar, E., Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis; TVLSI Nov. 2007 1205-1214 Li, Q., see Hu, S., TVLSI Oct. 2007 1067-1080 Li, X., see Han, Y., TVLSI May 2007 531-540 Li, Y., Bakkaloglu, B., and Chakrabarti, C., A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends; TVLSI Jan. 2007 90-103 Liao, W., see Long, C., TVLSI July 2007 830-841 Lin, C. H., Xie, Y., and Wolf, W., Code Compression for VLIW Embedded Systems Using a Self-Generating Table; TVLSI Oct. 2007 1160-1171 Lin, C.-H., Huang, C.-T., Jiang, C.-P., and Chang, S.-C., Optimization of Pattern Matching Circuits for Regular Expression on FPGA; TVLSI Dec. 2007 1303-1310 Lin, D.-S., see Chen, W.-Z., TVLSI March 2007 358-365 Lin, S.-P., Lee, C.-L., Chen, J.-E., Chen, J.-J., Luo, K.-L., and Wu, W.-C., A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design; TVLSI July 2007 767-776 Lingappan, L., see Gupta, P., TVLSI Jan. 2007 24-36 Lingappan, L., and Jha, N. K., Satisability-Based Automatic Test Program Generation and Design for Testability for Microprocessors; TVLSI May 2007 518-530 Liu, B., see Kahng, A. B., TVLSI Aug. 2007 904-912 Liu, B., and Tan, S. X.-D., Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs; TVLSI Nov. 2007 1284-1287 Liu, F., see Venkataraman, G., TVLSI Feb. 2007 149-158 Liu, F. Y., see Ye, X., TVLSI Aug. 2007 913-926 Liu, X., see Yu, Z., TVLSI Jan. 2007 5-12 Liu, Z., and Kursun, V., PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies; TVLSI Dec. 2007 13111319 Lloris, A., see Castillo, E., TVLSI May 2007 578-591 Lo, C.-Y., Wang, C.-H., Cheng, K.-L., Huang, J.-R., Wang, C.-W., Wang, S.-M., and Wu, C.-W., STEAC: A Platform for Automatic SOC Test Integration; TVLSI May 2007 541-545 Long, C., Simonson, L. J., Liao, W., and He, L., Microarchitecture Congurations and Floorplanning Co-Optimization; TVLSI July 2007 830-841 Lopez, G. G., see Joshi, A. J., TVLSI Sept. 2007 990-1002
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Lu, R., Cao, A., and Koh, C.-K., SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips; TVLSI Jan. 2007 69-79 Lu, T.-H., see Chen, C.-H., TVLSI May 2007 505-517 Lu, Z., Huang, W., Stan, M. R., Skadron, K., and Lach, J., Interconnect Lifetime Prediction for Reliability-Aware Systems; TVLSI Feb. 2007 159-172 Luican, I. I., see Balasa, F., TVLSI April 2007 447-460 Luk, W., see Cheung, R. C. C., TVLSI Aug. 2007 952-962 Luk, W., see Sedcole, P., TVLSI Sept. 2007 1003-1016 Luo, J., Jha, N. K., and Peh, L.-S., Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems; TVLSI April 2007 427-437 Luo, K.-L., see Lin, S.-P., TVLSI July 2007 767-776 Luo, L., see Zhang, L., TVLSI Feb. 2007 231-236
O O'Connor, I., Tissa-Drissi, F., Gafot, F., Dambre, J., De Wilde, M., Van Campenhout, J., Van Thourhout, D., Van Campenhout, J., and Stroobandt, D., Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect; TVLSI Aug. 2007 927-940 Ogura, M., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Onishi, T., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Ozdemir, S., see Ku, J. C., TVLSI May 2007 592-604 Ozev, S., see Acar, E., TVLSI Jan. 2007 37-47 P Pandey, S., and Glesner, M., Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc; TVLSI Oct. 2007 1111-1124 Papanikolaou, A., see Guo, J., TVLSI Aug. 2007 941-944 Park, I.-C., see Shin, M.-C., TVLSI July 2007 801-810 Park, Y.-K., see Seo, H.-M., TVLSI Feb. 2007 227-231 Parrilla, L., see Castillo, E., TVLSI May 2007 578-591 Paschalis, A., see Apostolakis, A., TVLSI Aug. 2007 971-975 Pavlidis, V. F., and Friedman, E. G., 3-D Topologies for Networks-on-Chip; TVLSI Oct. 2007 1081-1090 Pedram, M., see Abdollahi, A., TVLSI Jan. 2007 80-89 Peh, L.-S., see Luo, J., TVLSI April 2007 427-437 Peh, L.-S., see Soteriou, V., TVLSI Aug. 2007 855-868 Peng, Z., see Andrei, A., TVLSI March 2007 262-275 Pontarelli, S., see Cardarilli, G. C., TVLSI July 2007 842-846 Poon, A. S. Y., An Energy-Efcient Recongurable Baseband Processor for Wireless Communications; TVLSI March 2007 319-327 Potlapally, N. R., Raghunathan, A., Ravi, S., Jha, N. K., and Lee, R. B., Aiding Side-Channel Attacks on Cryptographic Software With Satisability-Based Analysis; TVLSI April 2007 465-470 Potlapally, N. R., Ravi, S., Raghunathan, A., Lee, R. B., and Jha, N. K., Conguration and Extension of Embedded Processors to Optimize IPSec Protocol Execution; TVLSI May 2007 605-609 Psarakis, M., see Apostolakis, A., TVLSI Aug. 2007 971-975 R Raffo, L., see Murali, S., TVLSI Aug. 2007 869-880 Raghunathan, A., see Aaraj, N., TVLSI March 2007 296-308 Raghunathan, A., see Potlapally, N. R., TVLSI April 2007 465-470 Raghunathan, A., see Potlapally, N. R., TVLSI May 2007 605-609 Raghunathan, A., see Arora, D., TVLSI May 2007 546-559 Raghunathan, A., see Arora, D., TVLSI June 2007 699-710 Raghunathan, A., see Huang, C., TVLSI Nov. 2007 1191-1204 Ranganathan, N., A Reection on the TVLSI Editorial Process and the Announcement of a New Editor-In-Chief; TVLSI Jan. 2007 1-4 Rao, L., Bushnell, M. L., and Agrawal, V. D., Graphical I Signatures Reduce Defect Level and Yield Loss; TVLSI Nov. 2007 1245-1255 Rao, R., see Agarwal, K., TVLSI June 2007 613-623 Ravi, S., see Aaraj, N., TVLSI March 2007 296-308 Ravi, S., see Potlapally, N. R., TVLSI April 2007 465-470 Ravi, S., see Potlapally, N. R., TVLSI May 2007 605-609 Ravi, S., see Arora, D., TVLSI May 2007 546-559 Ravi, S., see Arora, D., TVLSI June 2007 699-710 Ravi, S., see Huang, C., TVLSI Nov. 2007 1191-1204 Re, M., see Cardarilli, G. C., TVLSI July 2007 842-846 Rosenfeld, J., and Friedman, E. G., Design Methodology for Global Resonant H-Tree Clock Distribution Networks; TVLSI Feb. 2007 135-148 Rosing, T. S., Mihic, K., and De Micheli, G., Power and Reliability Management of SoCs; TVLSI April 2007 391-403 Roy, K., see Agarwal, A., TVLSI June 2007 660-671 Ruehli, A. E., see Gope, D., TVLSI Jan. 2007 60-68 Russell, G., see Kinniment, D. J., TVLSI Sept. 2007 1028-1039 S Sachdev, M., see Sharifkhani, M., TVLSI Feb. 2007 196-205 Sachdev, M., see Elgebaly, M., TVLSI May 2007 560-571 Saldana, M., Shannon, L., Yue, J. S., Bian, S., Craig, J., and Chow, P., Routability of Network Topologies in FPGAs; TVLSI Aug. 2007 948-951 Salsano, A., see Cardarilli, G. C., TVLSI July 2007 842-846 Saluja, K. K., see Nakamura, Y., TVLSI July 2007 790-800 Sankaradass, M., see Arora, D., TVLSI June 2007 699-710
M Ma, J., Vardy, A., and Wang, Z., Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes; TVLSI Nov. 2007 1225-1238 Mahapatra, R. N., see Ahmad, S., TVLSI Sept. 2007 1040-1050 Maheshwari, A., and Burleson, W., Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects; TVLSI Nov. 2007 1239-1244 Manne, V, see Keung, K.-M., TVLSI July 2007 733-745 Manohararajah, V., Chiu, G. R., Singh, D. P., and Brown, S. D., Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow; TVLSI Aug. 2007 895-903 Margala, M., see Jasionowski, B. J., TVLSI April 2007 478-483 Marshall, A., see Secareanu, R. M., TVLSI Oct. 2007 1065-1066 Mavrokefalidis, C., see Dimitrakopoulos, G., TVLSI June 2007 711-715 Mazumder, P., see Xu, Q., TVLSI Dec. 2007 1289-1302 McDonald, J. F., see You, C., TVLSI Sept. 2007 1051-1054 McNeely, J., see Zhao, P., TVLSI March 2007 338-345 Meeuwsen, M. J., see Apperson, R. W., TVLSI Oct. 2007 1125-1134 Meloni, P., see Murali, S., TVLSI Aug. 2007 869-880 Memik, G., see Ku, J. C., TVLSI May 2007 592-604 Mensink, E., Schinkel, D., Klumperink, E. A. M., van Tuijl, E., and Nauta, B., Optimal Positions of Twists in Global On-Chip Differential Interconnects; TVLSI April 2007 438-446 Meyer, J., and Kocan, F., Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs; TVLSI Feb. 2007 182-195 Meyer-Baese, U., see Castillo, E., TVLSI May 2007 578-591 Mihic, K., see Rosing, T. S., TVLSI April 2007 391-403 Minami, T., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Mittal, G., Zaretsky, D., Tang, X., and Banerjee, P., An Overview of a Compiler for Mapping Software Binaries to Hardware; TVLSI Nov. 2007 1177-1190 Mohsenin, T., see Apperson, R. W., TVLSI Oct. 2007 1125-1134 Moon, Y., see Seo, H.-M., TVLSI Feb. 2007 227-231 Mortazavi, Y., see Amirabadi, A., TVLSI Feb. 2007 125-134 Murali, S., Atienza, D., Meloni, P., Carta, S., Benini, L., De Micheli, G., and Raffo, L., Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors; TVLSI Aug. 2007 869-880
N Naganuma, J., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Nagata, M., see Noguchi, K., TVLSI Oct. 2007 1101-1110 Najm, F. N., see Azizi, N., TVLSI July 2007 746-757 Nakajima, Y., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Nakamura, K., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Nakamura, Y., Clouqueur, T., Saluja, K. K., and Fujiwara, H., Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester; TVLSI July 2007 790-800 Nakhla, M. S., see Saraswat, D., TVLSI Jan. 2007 48-59 Nauta, B., see Mensink, E., TVLSI April 2007 438-446 Nikolos, D., see Haniotakis, T., TVLSI April 2007 461-465 Nikolos, D., see Dimitrakopoulos, G., TVLSI June 2007 711-715 Nitta, K., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Noguchi, K., and Nagata, M., An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration; TVLSI Oct. 2007 1101-1110 Nourani, M., see Amirabadi, A., TVLSI Feb. 2007 125-134 Nowick, S. M., see Singh, M., TVLSI June 2007 684-698 Nowick, S. M., see Singh, M., TVLSI Nov. 2007 1256-1269 Nowick, S. M., see Singh, M., TVLSI Nov. 2007 1270-1283 Nowka, K. J., see Singh, H., TVLSI Nov. 2007 1215-1224 Nurmi, J., see Wang, X., TVLSI Oct. 2007 1091-1100 + Check author entry for coauthors
1371
Sapatnekar, S. S., see Zhang, T., TVLSI June 2007 624-636 Saraswat, D., Achar, R., and Nakhla, M. S., Fast Passivity Verication and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels; TVLSI Jan. 2007 48-59 Satagopan, V., Bhaskaran, B., Al-Assadi, W. K., Smith, S. C., and Kakarla, S., DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits; TVLSI Oct. 2007 1155-1159 Schinkel, D., see Mensink, E., TVLSI April 2007 438-446 Schmitz, M. T., see Andrei, A., TVLSI March 2007 262-275 Secareanu, R. M., and Marshall, A., Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications; TVLSI Oct. 2007 1065-1066 Sedcole, P., Cheung, P. Y. K., Constantinides, G. A., and Luk, W., Run-Time Integration of Recongurable Video Processing Systems; TVLSI Sept. 2007 1003-1016 Seo, H.-M., Moon, Y., Park, Y.-K., Kim, D., Kim, D.-S., Lee, Y.-S., Won, K.-H., Kim, S.-D., and Choi, P., A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks; TVLSI Feb. 2007 227-231 Shang, D., Yakovlev, A., Koelmans, A., Sokolov, D., and Bystrov, A., Registers for Phase Difference Based Logic; TVLSI June 2007 720-724 Shannon, L., see Saldana, M., TVLSI Aug. 2007 948-951 Shannon, L., and Chow, P., SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse; TVLSI April 2007 377-390 Sharifkhani, M., and Sachdev, M., Segmented Virtual Ground Architecture for Low-Power Embedded SRAM; TVLSI Feb. 2007 196-205 Shin, M.-C., and Park, I.-C., SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards; TVLSI July 2007 801-810 Shin, Y., Heo, S., Kim, H.-O., and Choi, J. Y., Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits; TVLSI July 2007 758-766 Shoushun, C., and Bermak, A., Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization; TVLSI March 2007 346-357 Simonson, L. J., see Long, C., TVLSI July 2007 830-841 Singh, D. P., see Manohararajah, V., TVLSI Aug. 2007 895-903 Singh, H., Agarwal, K., Sylvester, D., and Nowka, K. J., Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating; TVLSI Nov. 2007 1215-1224 Singh, M., and Nowick, S. M., MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines; TVLSI June 2007 684-698 Singh, M., and Nowick, S. M., The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style; TVLSI Nov. 2007 1256-1269 Singh, M., and Nowick, S. M., The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style; TVLSI Nov. 2007 1270-1283 Singh, P., see Foster, T. J., TVLSI May 2007 495-504 Skadron, K., see Lu, Z., TVLSI Feb. 2007 159-172 Smith, S. C., see Satagopan, V., TVLSI Oct. 2007 1155-1159 Smith, S. C., Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits; TVLSI June 2007 672-683 Sokolov, D., see Shang, D., TVLSI June 2007 720-724 Soteriou, V., Eisley, N., Wang, H., Li, B., and Peh, L.-S., Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks; TVLSI Aug. 2007 855-868 Sridharan, K., see Kumar, P. R., TVLSI Jan. 2007 118-123 Srivastava, A., see Khandelwal, V., TVLSI Feb. 2007 206-215 Stan, M. R., see Lu, Z., TVLSI Feb. 2007 159-172 Stroobandt, D., see O'Connor, I., TVLSI Aug. 2007 927-940 Stroud, C. E., see Emmert, J. M., TVLSI Feb. 2007 216-226 Sylvester, D., see Agarwal, K., TVLSI June 2007 613-623 Sylvester, D., see Singh, H., TVLSI Nov. 2007 1215-1224 T Tahoori, M. B., see Asadi, H., TVLSI Dec. 2007 1320-1331 Tan, S. X.-D., see Liu, B., TVLSI Nov. 2007 1284-1287 Tang, X., see Mittal, G., TVLSI Nov. 2007 1177-1190 Tashiro, Y., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Tissa-Drissi, F., see O'Connor, I., TVLSI Aug. 2007 927-940 Tsai, S. H., see Chi, J. C., TVLSI June 2007 637-648 Tseng, T.-W., see Huang, C.-D., TVLSI Oct. 2007 1135-1143 Tsiatouhas, Y., see Haniotakis, T., TVLSI April 2007 461-465 Tsui, C., see Jin, J., TVLSI Oct. 2007 1172-1176 Tyagi, A., see Keung, K.-M., TVLSI July 2007 733-745 U Underwood, K. D., see Hemmert, K. S., TVLSI Jan. 2007 115-118 + Check author entry for coauthors
V Van Campenhout, J., see O'Connor, I., TVLSI Aug. 2007 927-940 Van Campenhout, J., see O'Connor, I., TVLSI Aug. 2007 927-940 Van Thourhout, D., see O'Connor, I., TVLSI Aug. 2007 927-940 Vandenberghe, L., see Lee, J., TVLSI Sept. 2007 1017-1027 van Tuijl, E., see Mensink, E., TVLSI April 2007 438-446 Vardy, A., see Ma, J., TVLSI Nov. 2007 1225-1238 Venkataraman, G., Hu, J., and Liu, F., Integrated Placement and Skew Optimization for Rotary Clocking; TVLSI Feb. 2007 149-158 Verbauwhede, I., see Kim, J., TVLSI Aug. 2007 881-894 Villasenor, J. D., see Lee, D.-U., TVLSI April 2007 474-478 Villasenor, J. D., see Cheung, R. C. C., TVLSI Aug. 2007 952-962
W Wang, C.-H., see Lo, C.-Y., TVLSI May 2007 541-545 Wang, C.-W., see Lo, C.-Y., TVLSI May 2007 541-545 Wang, H., see Soteriou, V., TVLSI Aug. 2007 855-868 Wang, J.-F., see Jiang, Y.-C., TVLSI Dec. 2007 1351-1361 Wang, Q., see Kahng, A. B., TVLSI Aug. 2007 904-912 Wang, S.-H., see Hsia, S.-C., TVLSI June 2007 725-728 Wang, S.-M., see Lo, C.-Y., TVLSI May 2007 541-545 Wang, S., A BIST TPG for Low Power Dissipation and High Fault Coverage; TVLSI July 2007 777-789 Wang, X., Ahonen, T., and Nurmi, J., Applying CDMA Technique to Network-on-Chip; TVLSI Oct. 2007 1091-1100 Wang, Z., see Ma, J., TVLSI Nov. 2007 1225-1238 Wang, Z., High-Speed Recursion Architectures for MAP-Based Turbo Decoders; TVLSI April 2007 470-474 Wang, Z., and Cui, Z., A Memory Efcient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes; TVLSI April 2007 483-488 Wang, Z., and Cui, Z., Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes; TVLSI Jan. 2007 104-114 Wei, C.-K., see Chen, C.-H., TVLSI May 2007 505-517 Wilson, J. M., see Zhang, L., TVLSI Feb. 2007 231-236 Wolf, W., see Xie, Y., TVLSI Aug. 2007 975-980 Wolf, W., see Lin, C. H., TVLSI Oct. 2007 1160-1171 Won, K.-H., see Seo, H.-M., TVLSI Feb. 2007 227-231 Wu, A.-Y., see Lai, J.-T., TVLSI February 2007 236-240 Wu, C.-W., see Lo, C.-Y., TVLSI May 2007 541-545 Wu, W.-C., see Lin, S.-P., TVLSI July 2007 767-776
X Xie, Y., see Lin, C. H., TVLSI Oct. 2007 1160-1171 Xie, Y., Wolf, W., and Lekatsas, H., Code Decompression Unit Design for VLIW Embedded Processors; TVLSI Aug. 2007 975-980 Xin, Y., see Chen, S., TVLSI March 2007 328-337 Xu, J., see Zhang, L., TVLSI Feb. 2007 231-236 Xu, Q., and Mazumder, P., Efcient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method; TVLSI Dec. 2007 1289-1302
Y Yakovlev, A., see Shang, D., TVLSI June 2007 720-724 Yakovlev, A. V., see Kinniment, D. J., TVLSI Sept. 2007 1028-1039 Yamamoto, H., and Davis, J. A., Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation; TVLSI June 2007 649-659 Yang, C.-K. K., see Lee, J., TVLSI Sept. 2007 1017-1027 Yashima, Y., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 Ye, X., Liu, F. Y., and Li, P., Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models; TVLSI Aug. 2007 913-926 Yoshitome, T., see Iwasaki, H., TVLSI Sept. 2007 1055-1059 You, C., Guo, J.-R., Kraft, R. P., Chu, M., Goda, B., and McDonald, J. F., A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits; TVLSI Sept. 2007 1051-1054 Yu, Z., see Apperson, R. W., TVLSI Oct. 2007 1125-1134 Yu, Z., and Liu, X., Low-Power Rotary Clock Array Design; TVLSI Jan. 2007 5-12 Yue, J. S., see Saldana, M., TVLSI Aug. 2007 948-951
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Z Zaretsky, D., see Mittal, G., TVLSI Nov. 2007 1177-1190 Zenteno Ramirez, A., Espinosa, G., and Champac, V., Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops; TVLSI May 2007 572-577 Zhang, H., see Guo, J., TVLSI Aug. 2007 941-944 Zhang, L., Wilson, J. M., Bashirullah, R., Luo, L., Xu, J., and Franzon, P. D., Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses; TVLSI Feb. 2007 231-236 Zhang, T., see Chen, S., TVLSI March 2007 328-337 Zhang, T., and Sapatnekar, S. S., Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing; TVLSI June 2007 624-636 Zhang, X., Further Exploring the Strength of Prediction in the Factorization of Soft-Decision ReedSolomon Decoding; TVLSI July 2007 811-820 Zhao, P., McNeely, J., Golconda, P., Bayoumi, M. A., Barcenas, R. A., and Kuang, W., Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop; TVLSI March 2007 338-345 Zhu, H., see Balasa, F., TVLSI April 2007 447-460 SUBJECT INDEX 1/f Noise A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. Li, Y., +, TVLSI Jan. 2007 90-103 3G Mobile Communication SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 A AC-DC power converters A Design-for-Digital-Testability Circuit Structure for - Modulators. Hong, H.-C., TVLSI Dec. 2007 1341-1350 Adaptation model Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Adaptive systems Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 Algorithm design and analysis Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. Chi, J. C., +, TVLSI June 2007 637-648 Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Ampliers A 90-dB 10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology. Chen, W.-Z., +, TVLSI March 2007 358-365 Analytical models 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 Application specic integrated circuits A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285 IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591 Routability of Network Topologies in FPGAs. Saldana, M., +, TVLSI Aug. 2007 948-951 Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Arithmetic codes Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846
61
Arrays Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 Assembly An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Asynchronous circuits Registers for Phase Difference Based Logic. Shang, D., +, TVLSI June 2007 720-724 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 Automatic gain control Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. Lai, J.-T., +, TVLSI February 2007 236-240 A 90-dB 10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology. Chen, W.-Z., +, TVLSI March 2007 358-365 Automatic test equipment Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. Han, Y., +, TVLSI May 2007 531-540 Satisability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. Lingappan, L., +, TVLSI May 2007 518-530 Automatic test pattern generation Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47 A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. Lin, S.-P., +, TVLSI July 2007 767-776 A Test Generation Framework for Quantum Cellular Automata Circuits. Gupta, P., +, TVLSI Jan. 2007 24-36 DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. Han, Y., +, TVLSI May 2007 531-540 Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 Automatic test software Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 First Silicon Functional Validation and Debug of Multicore Microprocessors. Foster, T. J., +, TVLSI May 2007 495-504 Satisability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. Lingappan, L., +, TVLSI May 2007 518-530 Automatic testing Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems. Gizopoulos, D., +, TVLSI May 2007 493-494 Awards activities The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269
B Biometrics (access control) Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Block codes SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 Boolean functions An Efcient Approach to On-Chip Logic Minimization. Ahmad, S., +, TVLSI Sept. 2007 1040-1050 Buffer circuits Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. Kallakuri, S. S., +, TVLSI Feb. 2007 240-245 Buffer storage Two New Techniques Integrated for Energy-Efcient TLB Design. Chang, Y.-J., +, TVLSI Jan. 2007 13-23 Built-in self test Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. Nakamura, Y., +, TVLSI July 2007 790-800
+ Check author entry for coauthors
1373
A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 C CMOS digital integrated circuits Variation-Aware Adaptive Voltage Scaling System. Elgebaly, M., +, TVLSI May 2007 560-571 A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 CMOS image sensors Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization. Shoushun, C., +, TVLSI March 2007 346-357 CMOS integrated circuits A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. Abdollahi, A., +, TVLSI Jan. 2007 80-89 A 90-dB
10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology. Chen, W.-Z., +, TVLSI March 2007 358-365 A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285 A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. Li, Y., +, TVLSI Jan. 2007 90-103 An Energy-Efcient Recongurable Baseband Processor for Wireless Communications. Poon, A. S. Y., TVLSI March 2007 319-327 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Zenteno Ramirez, A., +, TVLSI May 2007 572-577 Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. Lee, J., +, TVLSI Sept. 2007 1017-1027 Optimal Positions of Twists in Global On-Chip Differential Interconnects. Mensink, E., +, TVLSI April 2007 438-446 Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Agarwal, K., +, TVLSI June 2007 613-623 Relaxed K -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766 Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236 CMOS logic circuits Clock Delayed Domino Logic With Efcient Variable Threshold Voltage Keeper. Amirabadi, A., +, TVLSI Feb. 2007 125-134 A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. Smith, S. C., TVLSI June 2007 672-683 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. Liu, Z., +, TVLSI Dec. 2007 1311-1319 Testable Designs of Multiple Precharged Domino Circuits. Haniotakis, T., +, TVLSI April 2007 461-465 CMOS memory circuits A New Single-Ended SRAM Cell With Write-Assist. Hobson, R. F., TVLSI Feb. 2007 173-181 Cache storage Thermal Management of On-Chip Caches Through Power Density Minimization. Ku, J. C., +, TVLSI May 2007 592-604 Capacitance Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 Capacitors Design Methodology for Global Resonant -Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 Cellular automata A Test Generation Framework for Quantum Cellular Automata Circuits. Gupta, P., +, TVLSI Jan. 2007 24-36 Circuit CAD Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. Manohararajah, V., +, TVLSI Aug. 2007 895-903 Circuit analysis computing A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 Circuit faults DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 Circuit layout Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. Cao, K., +, TVLSI Dec. 2007 1332-1340 Circuit layout CAD Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912 Circuit optimisation Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Microarchitecture Congurations and Floorplanning Co-Optimization. Long, C., +, TVLSI July 2007 830-841 Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Agarwal, K., +, TVLSI June 2007 613-623 Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Circuit reliability Measuring Deep Metastability and Its Effect on Synchronizer Performance. Kinniment, D. J., +, TVLSI Sept. 2007 1028-1039 Circuit simulation A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 Circuit testing A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. Lin, S.-P., +, TVLSI July 2007 767-776 A Design-for-Digital-Testability Circuit Structure for - Modulators. Hong, H.-C., TVLSI Dec. 2007 1341-1350 Circuit tuning Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 Clocks Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 Clock Delayed Domino Logic With Efcient Variable Threshold Voltage Keeper. Amirabadi, A., +, TVLSI Feb. 2007 125-134 Design Methodology for Global Resonant -Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. Zhao, P., +, TVLSI March 2007 338-345 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Code division multiple access A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. Li, Y., +, TVLSI Jan. 2007 90-103 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 Combinational circuits Clock Delayed Domino Logic With Efcient Variable Threshold Voltage Keeper. Amirabadi, A., +, TVLSI Feb. 2007 125-134 A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285
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Communication channels 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Complexity theory Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Computability Aiding Side-Channel Attacks on Cryptographic Software With Satisability-Based Analysis. Potlapally, N. R., +, TVLSI April 2007 465-470 Computational modeling Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 Computer architecture Architectural Support for Run-Time Validation of Program Data Properties. Arora, D., +, TVLSI May 2007 546-559 A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 STEAC: A Platform for Automatic SOC Test Integration. Lo, C.-Y., +, TVLSI May 2007 541-545 Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 Conferences Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. Secareanu, R. M., +, TVLSI Oct. 2007 1065-1066 Construction industry Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 Coprocessors Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Correlation methods Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Crosstalk Optimal Positions of Twists in Global On-Chip Differential Interconnects. Mensink, E., +, TVLSI April 2007 438-446 Cryptographic protocols Conguration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. Potlapally, N. R., +, TVLSI May 2007 605-609 Cryptography Aiding Side-Channel Attacks on Cryptographic Software With Satisability-Based Analysis. Potlapally, N. R., +, TVLSI April 2007 465-470 Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. Arora, D., +, TVLSI June 2007 699-710 Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Current measurement Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 Cyclic codes Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 A Memory Efcient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI April 2007 483-488
D Data compression A Processor-In-Memory Architecture for Multimedia Compression. Jasionowski, B. J., +, TVLSI April 2007 478-483 + Check author entry for coauthors
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. Lin, S.-P., +, TVLSI July 2007 767-776 Code Decompression Unit Design for VLIW Embedded Processors. Xie, Y., +, TVLSI Aug. 2007 975-980 Data ow computing A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Data ow graphs Temporal Partitioning Data Flow Graphs for Dynamically Recongurable Computing. Jiang, Y.-C., +, TVLSI Dec. 2007 1351-1361 Data security Architectural Support for Run-Time Validation of Program Data Properties. Arora, D., +, TVLSI May 2007 546-559 Decoding Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 Degradation Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Delay Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 Delay estimation Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Delays Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. Manohararajah, V., +, TVLSI Aug. 2007 895-903 Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 Demultiplexing equipment A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. You, C., +, TVLSI Sept. 2007 1051-1054 Design for manufacture Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. Cao, K., +, TVLSI Dec. 2007 1332-1340 Design for testability Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47 A Design-for-Digital-Testability Circuit Structure for - Modulators. Hong, H.-C., TVLSI Dec. 2007 1341-1350 Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Zenteno Ramirez, A., +, TVLSI May 2007 572-577 Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems. Gizopoulos, D., +, TVLSI May 2007 493-494 Satisability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. Lingappan, L., +, TVLSI May 2007 518-530 Testable Designs of Multiple Precharged Domino Circuits. Haniotakis, T., +, TVLSI April 2007 461-465 Design methodology IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591
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Dies Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Digital arithmetic On Concurrent Detection of Errors in Polynomial Basis Multiplication. Bayat-Sarmadi, S., +, TVLSI April 2007 413-426 Code Decompression Unit Design for VLIW Embedded Processors. Xie, Y., +, TVLSI Aug. 2007 975-980 Digital signal processing chips A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Digital signatures IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591 Discrete Fourier transforms DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 Discrete cosine transforms Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 Distributed arithmetic Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 Distributed databases Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 Dividing circuits Floating-Point Divider Design for FPGAs. Hemmert, K. S., +, TVLSI Jan. 2007 115-118 Driver circuits Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214
Earthing Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 Eigenvalues and eigenfunctions Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Electric charge A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 Electric potential Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Electromagnetic interference Efcient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method. Xu, Q., +, TVLSI Dec. 2007 1289-1302 Electromagnetic shielding Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. Zhang, T., +, TVLSI June 2007 624-636 Electromigration Interconnect Lifetime Prediction for Reliability-Aware Systems. Lu, Z., +, TVLSI Feb. 2007 159-172 Electronic engineering computing Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. Apostolakis, A., +, TVLSI Aug. 2007 971-975 Embedded system Architectural Support for Run-Time Validation of Program Data Properties. Arora, D., +, TVLSI May 2007 546-559 Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Embedded systems Two New Techniques Integrated for Energy-Efcient TLB Design. Chang, Y.-J., +, TVLSI Jan. 2007 13-23 Code Decompression Unit Design for VLIW Embedded Processors. Xie, Y., +, TVLSI Aug. 2007 975-980 Conguration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. Potlapally, N. R., +, TVLSI May 2007 605-609 Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. Smith, S. C., TVLSI June 2007 672-683 + Check author entry for coauthors
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. Han, Y., +, TVLSI May 2007 531-540 Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. Arora, D., +, TVLSI June 2007 699-710 Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Power and Reliability Management of SoCs. Rosing, T. S., +, TVLSI April 2007 391-403 Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. Luo, J., +, TVLSI April 2007 427-437 Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Recongurable System. Galanis, M. D., +, TVLSI Dec. 2007 1362-1366 Encoding Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Entropy Post-Placement Interconnect Entropy. Feng, W., +, TVLSI Aug. 2007 945-948 Equations Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Equivalent circuits Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. Gope, D., +, TVLSI Jan. 2007 60-68 Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 Error analysis Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. Nakamura, Y., +, TVLSI July 2007 790-800 Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. Cheung, R. C. C., +, TVLSI Aug. 2007 952-962 Error correction codes Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 A Memory Efcient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI April 2007 483-488 Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding. Gross, W. J., +, TVLSI March 2007 309-318 Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Further Exploring the Strength of Prediction in the Factorization of SoftDecision ReedSolomon Decoding. Zhang, X., TVLSI July 2007 811-820 Error detection On Concurrent Detection of Errors in Polynomial Basis Multiplication. Bayat-Sarmadi, S., +, TVLSI April 2007 413-426 Error detection codes Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Error statistics A 90-dB
10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology. Chen, W.-Z., +, TVLSI March 2007 358-365 F Face recognition Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Fault diagnosis A Test Generation Framework for Quantum Cellular Automata Circuits. Gupta, P., +, TVLSI Jan. 2007 24-36 A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Chen, X., +, TVLSI April 2007 404-412
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Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. Nakamura, Y., +, TVLSI July 2007 790-800 Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 Testable Designs of Multiple Precharged Domino Circuits. Haniotakis, T., +, TVLSI April 2007 461-465 Fault tolerance Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Field programmable gate arrays Floating-Point Divider Design for FPGAs. Hemmert, K. S., +, TVLSI Jan. 2007 115-118 A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. You, C., +, TVLSI Sept. 2007 1051-1054 A Flexible Architecture for Precise Gamma Correction. Lee, D.-U., +, TVLSI April 2007 474-478 An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. Asadi, H., +, TVLSI Dec. 2007 1320-1331 Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding. Gross, W. J., +, TVLSI March 2007 309-318 Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. Smith, S. C., TVLSI June 2007 672-683 Guest Editorial System-Level Interconnect Prediction. Dambre, J., +, TVLSI Aug. 2007 853-854 Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. Cheung, R. C. C., +, TVLSI Aug. 2007 952-962 IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591 Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 Optimization of Pattern Matching Circuits for Regular Expression on FPGA. Lin, C.-H., +, TVLSI Dec. 2007 1303-1310 Post-Placement Interconnect Entropy. Feng, W., +, TVLSI Aug. 2007 945-948 Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. Manohararajah, V., +, TVLSI Aug. 2007 895-903 Routability of Network Topologies in FPGAs. Saldana, M., +, TVLSI Aug. 2007 948-951 Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. Shannon, L., +, TVLSI April 2007 377-390 Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. Meyer, J., +, TVLSI Feb. 2007 182-195 Temporal Partitioning Data Flow Graphs for Dynamically Recongurable Computing. Jiang, Y.-C., +, TVLSI Dec. 2007 1351-1361 VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. Kumar, P. R., +, TVLSI Jan. 2007 118-123 Filters Two New Techniques Integrated for Energy-Efcient TLB Design. Chang, Y.-J., +, TVLSI Jan. 2007 13-23 Finite automata Optimization of Pattern Matching Circuits for Regular Expression on FPGA. Lin, C.-H., +, TVLSI Dec. 2007 1303-1310 Finite difference methods Efcient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method. Xu, Q., +, TVLSI Dec. 2007 1289-1302 Finite impulse response lter The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 Fixed point arithmetic Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Flip-ops Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Chen, X., +, TVLSI April 2007 404-412 Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Zenteno Ramirez, A., +, TVLSI May 2007 572-577 Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. Zhao, P., +, TVLSI March 2007 338-345 Registers for Phase Difference Based Logic. Shang, D., +, TVLSI June 2007 720-724 Floating point arithmetic Floating-Point Divider Design for FPGAs. Hemmert, K. S., +, TVLSI Jan. 2007 115-118 Frequency shift keying Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47 Frequency synchronization A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 Frequency synthesizers A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 G Galois elds Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Gamma distribution A Flexible Architecture for Precise Gamma Correction. Lee, D.-U., +, TVLSI April 2007 474-478 Ge-Si alloys A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. You, C., +, TVLSI Sept. 2007 1051-1054 Geometric programming Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. Lee, J., +, TVLSI Sept. 2007 1017-1027 H Hadamard transforms Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 High denition television Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 High level languages An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 High level synthesis Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 High-speed integrated circuits High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. You, C., +, TVLSI Sept. 2007 1051-1054 I IEEE standards A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 STEAC: A Platform for Automatic SOC Test Integration. Lo, C.-Y., +, TVLSI May 2007 541-545 Image registration A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989
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Inductance Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. Gope, D., +, TVLSI Jan. 2007 60-68 Inductors Design Methodology for Global Resonant H-Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 Industrial property Power and Reliability Management of SoCs. Rosing, T. S., +, TVLSI April 2007 391-403 SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. Shannon, L., +, TVLSI April 2007 377-390 Integer programming Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. Andrei, A., +, TVLSI March 2007 262-275 Integrated circuit design A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. Abdollahi, A., +, TVLSI Jan. 2007 80-89 A Methodology for Transistor-Efcient Supergate Design. Kagaris, D., +, TVLSI April 2007 488-492 A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285 An Energy-Efcient Recongurable Baseband Processor for Wireless Communications. Poon, A. S. Y., TVLSI March 2007 319-327 Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. Kallakuri, S. S., +, TVLSI Feb. 2007 240-245 Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Joshi, A. J., +, TVLSI Sept. 2007 990-1002 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Device-Aware Yield-Centric Dual-V Design Under Parameter Variations in Nanoscale Technologies. Agarwal, A., +, TVLSI June 2007 660-671 Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. Gregg, J., +, TVLSI March 2007 366-376 SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. Shannon, L., +, TVLSI April 2007 377-390 Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912 Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766 Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. Azizi, N., +, TVLSI July 2007 746-757 Integrated circuit interconnections Fast Passivity Verication and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. Saraswat, D., +, TVLSI Jan. 2007 48-59 Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Joshi, A. J., +, TVLSI Sept. 2007 990-1002 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 Guest Editorial System-Level Interconnect Prediction. Dambre, J., +, TVLSI Aug. 2007 853-854 Interconnect Lifetime Prediction for Reliability-Aware Systems. Lu, Z., +, TVLSI Feb. 2007 159-172 Microarchitecture Congurations and Floorplanning Co-Optimization. Long, C., +, TVLSI July 2007 830-841 Optimal Positions of Twists in Global On-Chip Differential Interconnects. Mensink, E., +, TVLSI April 2007 438-446 Post-Placement Interconnect Entropy. Feng, W., +, TVLSI Aug. 2007 945-948 Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. Manohararajah, V., +, TVLSI Aug. 2007 895-903
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. Zhang, T., +, TVLSI June 2007 624-636 Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. Ku, J. C., +, TVLSI Aug. 2007 963-970 Variation-Aware Adaptive Voltage Scaling System. Elgebaly, M., +, TVLSI May 2007 560-571 Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236 Integrated circuit layout Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. Guo, J., +, TVLSI Aug. 2007 941-944 Microarchitecture Congurations and Floorplanning Co-Optimization. Long, C., +, TVLSI July 2007 830-841 Integrated circuit manufacture A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. Nakamura, Y., +, TVLSI July 2007 790-800 Integrated circuit modeling Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 Integrated circuit modelling Fast Passivity Verication and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. Saraswat, D., +, TVLSI Jan. 2007 48-59 A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. Khandelwal, V., +, TVLSI Feb. 2007 206-215 Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 Interconnect Lifetime Prediction for Reliability-Aware Systems. Lu, Z., +, TVLSI Feb. 2007 159-172 Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 Variation-Aware Adaptive Voltage Scaling System. Elgebaly, M., +, TVLSI May 2007 560-571 Integrated circuit noise Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 Integrated circuit packaging A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 Integrated circuit reliability Interconnect Lifetime Prediction for Reliability-Aware Systems. Lu, Z., +, TVLSI Feb. 2007 159-172 Power and Reliability Management of SoCs. Rosing, T. S., +, TVLSI April 2007 391-403 Integrated circuit testing A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. Li, Y., +, TVLSI Jan. 2007 90-103 A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. Nakamura, Y., +, TVLSI July 2007 790-800 Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. Apostolakis, A., +, TVLSI Aug. 2007 971-975 Power and Reliability Management of SoCs. Rosing, T. S., +, TVLSI April 2007 391-403 Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 Testable Designs of Multiple Precharged Domino Circuits. Haniotakis, T., +, TVLSI April 2007 461-465 Integrated circuit yield Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. Gregg, J., +, TVLSI March 2007 366-376 Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Agarwal, K., +, TVLSI June 2007 613-623 Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Integrated logic circuits High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 Integrated optics Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. O'Connor, I., +, TVLSI Aug. 2007 927-940
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Intellectual property IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591 Interference suppression Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. Zhang, T., +, TVLSI June 2007 624-636 Interleaved codes SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 Interpolation Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Iterative decoding High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 Further Exploring the Strength of Prediction in the Factorization of SoftDecision ReedSolomon Decoding. Zhang, X., TVLSI July 2007 811-820 J Jitter Design Methodology for Global Resonant H-Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 L Large scale integration Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Latches Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Zenteno Ramirez, A., +, TVLSI May 2007 572-577 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 Leakage current Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Leakage currents A New Single-Ended SRAM Cell With Write-Assist. Hobson, R. F., TVLSI Feb. 2007 173-181 A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285 PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. Liu, Z., +, TVLSI Dec. 2007 1311-1319 Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766 Linear programming Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. Andrei, A., +, TVLSI March 2007 262-275 Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Load modeling Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 Logic CAD Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. Guo, J., +, TVLSI Aug. 2007 941-944 Logic circuits Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Logic design Floating-Point Divider Design for FPGAs. Hemmert, K. S., +, TVLSI Jan. 2007 115-118
An Efcient Approach to On-Chip Logic Minimization. Ahmad, S., +, TVLSI Sept. 2007 1040-1050 Clock Delayed Domino Logic With Efcient Variable Threshold Voltage Keeper. Amirabadi, A., +, TVLSI Feb. 2007 125-134 Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. Kallakuri, S. S., +, TVLSI Feb. 2007 240-245 Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 Design Methodology for Global Resonant H-Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 Post-Placement Interconnect Entropy. Feng, W., +, TVLSI Aug. 2007 945-948 Registers for Phase Difference Based Logic. Shang, D., +, TVLSI June 2007 720-724 Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. Meyer, J., +, TVLSI Feb. 2007 182-195 Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 Logic gates A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Logic testing A Test Generation Framework for Quantum Cellular Automata Circuits. Gupta, P., +, TVLSI Jan. 2007 24-36 An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Chen, X., +, TVLSI April 2007 404-412 On Concurrent Detection of Errors in Polynomial Basis Multiplication. Bayat-Sarmadi, S., +, TVLSI April 2007 413-426 Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 STEAC: A Platform for Automatic SOC Test Integration. Lo, C.-Y., +, TVLSI May 2007 541-545 Testable Designs of Multiple Precharged Domino Circuits. Haniotakis, T., +, TVLSI April 2007 461-465 Low power electronics Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. Chi, J. C., +, TVLSI June 2007 637-648 Low-power electronics Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 A New Single-Ended SRAM Cell With Write-Assist. Hobson, R. F., TVLSI Feb. 2007 173-181 An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Chen, X., +, TVLSI April 2007 404-412 Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization. Shoushun, C., +, TVLSI March 2007 346-357 Design Methodology for Global Resonant H-Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. Lee, J., +, TVLSI Sept. 2007 1017-1027 Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. Zhao, P., +, TVLSI March 2007 338-345
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Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. Meyer, J., +, TVLSI Feb. 2007 182-195 Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766 Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. Ku, J. C., +, TVLSI Aug. 2007 963-970 Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. Kim, T.-H., +, TVLSI July 2007 821-829 Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. Azizi, N., +, TVLSI July 2007 746-757 Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236
M MIMO communication Relaxed -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 MOS devices Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Zenteno Ramirez, A., +, TVLSI May 2007 572-577 Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Magnetic cores ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Maintenance engineering ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Markov processes Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. Kallakuri, S. S., +, TVLSI Feb. 2007 240-245 Maximum likelihood decoding Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 Maximum likelihood estimation High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 Mean square error methods A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Media Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Memory architecture Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications. Balasa, F., +, TVLSI April 2007 447-460 A Processor-In-Memory Architecture for Multimedia Compression. Jasionowski, B. J., +, TVLSI April 2007 478-483 Memory management Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 Microprocessor chips Two New Techniques Integrated for Energy-Efcient TLB Design. Chang, Y.-J., +, TVLSI Jan. 2007 13-23 A Processor-In-Memory Architecture for Multimedia Compression. Jasionowski, B. J., +, TVLSI April 2007 478-483 An Energy-Efcient Recongurable Baseband Processor for Wireless Communications. Poon, A. S. Y., TVLSI March 2007 319-327 Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding. Gross, W. J., +, TVLSI March 2007 309-318 Code Decompression Unit Design for VLIW Embedded Processors. Xie, Y., +, TVLSI Aug. 2007 975-980 Conguration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. Potlapally, N. R., +, TVLSI May 2007 605-609 Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 First Silicon Functional Validation and Debug of Multicore Microprocessors. Foster, T. J., +, TVLSI May 2007 495-504
Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems. Gizopoulos, D., +, TVLSI May 2007 493-494 Satisability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. Lingappan, L., +, TVLSI May 2007 518-530 Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. Luo, J., +, TVLSI April 2007 427-437 Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. Chen, C.-H., +, TVLSI May 2007 505-517 Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. Azizi, N., +, TVLSI July 2007 746-757 Microprocessors STEAC: A Platform for Automatic SOC Test Integration. Lo, C.-Y., +, TVLSI May 2007 541-545 Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 Minimisation Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Minimisation of switching nets An Efcient Approach to On-Chip Logic Minimization. Ahmad, S., +, TVLSI Sept. 2007 1040-1050 Mobile robots VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. Kumar, P. R., +, TVLSI Jan. 2007 118-123 Monitoring An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 Monte Carlo methods Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Agarwal, K., +, TVLSI June 2007 613-623 Multiaccess communication Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Multichip modules Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Multidimensional signal processing Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications. Balasa, F., +, TVLSI April 2007 447-460 Multimedia systems Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Multiplying circuits On Concurrent Detection of Errors in Polynomial Basis Multiplication. Bayat-Sarmadi, S., +, TVLSI April 2007 413-426 A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 Multiprocessing systems Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Code Decompression Unit Design for VLIW Embedded Processors. Xie, Y., +, TVLSI Aug. 2007 975-980 Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. Andrei, A., +, TVLSI March 2007 262-275 Multiprocessor interconnection networks Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. Soteriou, V., +, TVLSI Aug. 2007 855-868
N Nanoelectronics Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766 Nanotechnology Device-Aware Yield-Centric Dual- Design Under Parameter Variations in Nanoscale Technologies. Agarwal, A., +, TVLSI June 2007 660-671
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Network routing Routability of Network Topologies in FPGAs. Saldana, M., +, TVLSI Aug. 2007 948-951 An Efcient Approach to On-Chip Logic Minimization. Ahmad, S., +, TVLSI Sept. 2007 1040-1050 Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Joshi, A. J., +, TVLSI Sept. 2007 990-1002 Network synthesis Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. Kim, T.-H., +, TVLSI July 2007 821-829 Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. O'Connor, I., +, TVLSI Aug. 2007 927-940 Network topology Routability of Network Topologies in FPGAs. Saldana, M., +, TVLSI Aug. 2007 948-951 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Network-on-chip Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Murali, S., +, TVLSI Aug. 2007 869-880 Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Joshi, A. J., +, TVLSI Sept. 2007 990-1002 Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. Soteriou, V., +, TVLSI Aug. 2007 855-868 Routability of Network Topologies in FPGAs. Saldana, M., +, TVLSI Aug. 2007 948-951 Noise An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. Li, P., +, TVLSI Nov. 2007 1205-1214 Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 O Optical interconnections Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. O'Connor, I., +, TVLSI Aug. 2007 927-940 Optical receivers A 90-dB
10-Gb/s Optical Receiver Analog Front-End in a 0.18-m CMOS Technology. Chen, W.-Z., +, TVLSI March 2007 358-365 Optimisation Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912 Optimization Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Organizations Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 P Parallel architectures Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 A Memory Efcient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI April 2007 483-488 Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding. Gross, W. J., +, TVLSI March 2007 309-318 Parallel processing VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. Kumar, P. R., +, TVLSI Jan. 2007 118-123 Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 + Check author entry for coauthors
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 Parity check codes Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 A Memory Efcient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI April 2007 483-488 Pattern matching Optimization of Pattern Matching Circuits for Regular Expression on FPGA. Lin, C.-H., +, TVLSI Dec. 2007 1303-1310 Performance evaluation Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Recongurable System. Galanis, M. D., +, TVLSI Dec. 2007 1362-1366 Piecewise linear techniques A Flexible Architecture for Precise Gamma Correction. Lee, D.-U., +, TVLSI April 2007 474-478 Piecewise polynomial techniques A Flexible Architecture for Precise Gamma Correction. Lee, D.-U., +, TVLSI April 2007 474-478 Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. Cheung, R. C. C., +, TVLSI Aug. 2007 952-962 Pipeline processing Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Pipelines DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Polynomials On Concurrent Detection of Errors in Polynomial Basis Multiplication. Bayat-Sarmadi, S., +, TVLSI April 2007 413-426 Further Exploring the Strength of Prediction in the Factorization of SoftDecision ReedSolomon Decoding. Zhang, X., TVLSI July 2007 811-820 Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Portable computers Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. Arora, D., +, TVLSI June 2007 699-710 Power consumption Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. Kim, T.-H., +, TVLSI July 2007 821-829 Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236 Power demand Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. Chi, J. C., +, TVLSI June 2007 637-648 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 Power dissipation Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Power supplies An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 Power supply circuits A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Shin, Y., +, TVLSI July 2007 758-766
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Power transmission lines Efcient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method. Xu, Q., +, TVLSI Dec. 2007 1289-1302 Prediction theory Further Exploring the Strength of Prediction in the Factorization of SoftDecision ReedSolomon Decoding. Zhang, X., TVLSI July 2007 811-820 Predictive models Guest Editorial System-Level Interconnect Prediction. Dambre, J., +, TVLSI Aug. 2007 853-854 Printed circuit layout Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. Cao, K., +, TVLSI Dec. 2007 1332-1340 Probability Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Processor scheduling Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. Luo, J., +, TVLSI April 2007 427-437 Production testing Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47 Program debugging First Silicon Functional Validation and Debug of Multicore Microprocessors. Foster, T. J., +, TVLSI May 2007 495-504 Program processors Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Programmable circuits A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Programmable controllers SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. Shannon, L., +, TVLSI April 2007 377-390 Programmable logic devices Post-Placement Interconnect Entropy. Feng, W., +, TVLSI Aug. 2007 945-948 Programming Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidenite and Linear Programs. Liu, B., +, TVLSI Nov. 2007 1284-1287 Protocols Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 Q Quadrature amplitude modulation Relaxed -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Quantisation (signal) Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Wang, Z., +, TVLSI Jan. 2007 104-114 Quantum gates A Test Generation Framework for Quantum Cellular Automata Circuits. Gupta, P., +, TVLSI Jan. 2007 24-36
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Random number generation Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. Cheung, R. C. C., +, TVLSI Aug. 2007 952-962 Random sequences A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 Real time systems Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 Real-time systems A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Receivers Relaxed -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Recongurable architectures Online Fault Tolerance for FPGA Logic Blocks. Emmert, J. M., +, TVLSI Feb. 2007 216-226 An Energy-Efcient Recongurable Baseband Processor for Wireless Communications. Poon, A. S. Y., TVLSI March 2007 319-327 Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Recongurable System. Galanis, M. D., +, TVLSI Dec. 2007 1362-1366 Temporal Partitioning Data Flow Graphs for Dynamically Recongurable Computing. Jiang, Y.-C., +, TVLSI Dec. 2007 1351-1361 Reduced instruction set computing Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Redundancy ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Reed-Solomon codes Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding. Gross, W. J., +, TVLSI March 2007 309-318 Concurrent Error Detection in ReedSolomon Encoders and Decoders. Cardarilli, G. C., +, TVLSI July 2007 842-846 Further Exploring the Strength of Prediction in the Factorization of SoftDecision ReedSolomon Decoding. Zhang, X., TVLSI July 2007 811-820 Registers DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. Satagopan, V., +, TVLSI Oct. 2007 1155-1159 Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of ReedSolomon Codes. Ma, J., +, TVLSI Nov. 2007 1225-1238 Reliability Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. Asadi, H., +, TVLSI Dec. 2007 1320-1331 Repeaters Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236 Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Resistance Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 Routing Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080
R S Radiofrequency integrated circuits A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 Rails Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Random access memory Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 + Check author entry for coauthors S-parameters Fast Passivity Verication and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. Saraswat, D., +, TVLSI Jan. 2007 48-59 SPICE Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. Gope, D., +, TVLSI Jan. 2007 60-68
1382
A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. Keung, K.-M., +, TVLSI July 2007 733-745 MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. Singh, M., +, TVLSI June 2007 684-698 Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Agarwal, K., +, TVLSI June 2007 613-623 Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912 SRAM chips A New Single-Ended SRAM Cell With Write-Assist. Hobson, R. F., TVLSI Feb. 2007 173-181 Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. Sharifkhani, M., +, TVLSI Feb. 2007 196-205 Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. Meyer, J., +, TVLSI Feb. 2007 182-195 Scheduling Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Semiconductor device measurement Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 Semiconductor device modeling Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Sensitivity analysis Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 Sensors Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Sequential circuits A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 Shift registers Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 Registers for Phase Difference Based Logic. Shang, D., +, TVLSI June 2007 720-724 Sigma-delta modulation A Design-for-Digital-Testability Circuit Structure for - Modulators. Hong, H.-C., TVLSI Dec. 2007 1341-1350 Signal detection Relaxed K -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Silicon First Silicon Functional Validation and Debug of Multicore Microprocessors. Foster, T. J., +, TVLSI May 2007 495-504 Software Code Compression for VLIW Embedded Systems Using a Self-Generating Table. Lin, C. H., +, TVLSI Oct. 2007 1160-1171 Software tools Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 An Overview of a Compiler for Mapping Software Binaries to Hardware. Mittal, G., +, TVLSI Nov. 2007 1177-1190 Solid modeling 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Sorting Sorter Based Permutation Units for Media-Enhanced Microprocessors. Dimitrakopoulos, G., +, TVLSI June 2007 711-715 Sparse matrices Power Modeling and Efcient FPGA Implementation of FHT for Signal Processing. Amira, A., +, TVLSI March 2007 286-295 Special issues and sections Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems. Gizopoulos, D., +, TVLSI May 2007 493-494 Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. Secareanu, R. M., +, TVLSI Oct. 2007 1065-1066 Statistical analysis A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. Khandelwal, V., +, TVLSI Feb. 2007 206-215 Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 Stochastic processes Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912
61
Storage allocation Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications. Balasa, F., +, TVLSI April 2007 447-460 Substrates An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 Switches Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Switching circuits Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 Applying CDMA Technique to Network-on-Chip. Wang, X., +, TVLSI Oct. 2007 1091-1100 Switching functions A Methodology for Transistor-Efcient Supergate Design. Kagaris, D., +, TVLSI April 2007 488-492 Synchronisation Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 Measuring Deep Metastability and Its Effect on Synchronizer Performance. Kinniment, D. J., +, TVLSI Sept. 2007 1028-1039 Synchronization A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. Huang, C., +, TVLSI Nov. 2007 1191-1204 The Design of High-Performance Dynamic Asynchronous Pipelines: HighCapacity Style. Singh, M., +, TVLSI Nov. 2007 1270-1283 System buses SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. Lu, R., +, TVLSI Jan. 2007 69-79 System recovery Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. Asadi, H., +, TVLSI Dec. 2007 1320-1331 System-on-a-chip STEAC: A Platform for Automatic SOC Test Integration. Lo, C.-Y., +, TVLSI May 2007 541-545 An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. Huang, C.-D., +, TVLSI Oct. 2007 1135-1143 Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 System-on-chip SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. Lu, R., +, TVLSI Jan. 2007 69-79 Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. Andrei, A., +, TVLSI March 2007 262-275 Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. Guo, J., +, TVLSI Aug. 2007 941-944 Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. Lee, J., +, TVLSI Sept. 2007 1017-1027 Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. Arora, D., +, TVLSI June 2007 699-710 Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. Apostolakis, A., +, TVLSI Aug. 2007 971-975 Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. Secareanu, R. M., +, TVLSI Oct. 2007 1065-1066 Hybrid Architectures for Efcient and Secure Face Authentication in Embedded Systems. Aaraj, N., +, TVLSI March 2007 296-308 Measuring Deep Metastability and Its Effect on Synchronizer Performance. Kinniment, D. J., +, TVLSI Sept. 2007 1028-1039 Optimal Positions of Twists in Global On-Chip Differential Interconnects. Mensink, E., +, TVLSI April 2007 438-446 Power and Reliability Management of SoCs. Rosing, T. S., +, TVLSI April 2007 391-403 SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. Shannon, L., +, TVLSI April 2007 377-390 Thermal Management of On-Chip Caches Through Power Density Minimization. Ku, J. C., +, TVLSI May 2007 592-604
1383
T Table lookup Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. Meyer, J., +, TVLSI Feb. 2007 182-195 Telecommunication channels Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 Telecommunication standards SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810 Testing Wafer-Level Modular Testing of Core-Based SoCs. Bahukudumbi, S., +, TVLSI Oct. 2007 1144-1154 Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 Thermal analysis Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. Ku, J. C., +, TVLSI Aug. 2007 963-970 Thermal management (packaging) Interconnect Lifetime Prediction for Reliability-Aware Systems. Lu, Z., +, TVLSI Feb. 2007 159-172 Thermal Management of On-Chip Caches Through Power Density Minimization. Ku, J. C., +, TVLSI May 2007 592-604 Threshold voltage Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Singh, H., +, TVLSI Nov. 2007 1215-1224 Time division multiplexing Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. Kim, J., +, TVLSI Aug. 2007 881-894 Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 Time frequency analysis A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 Timing Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. Chi, J. C., +, TVLSI June 2007 637-648 Timing circuits Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Heo, S., +, TVLSI Sept. 2007 1060-1064 A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. Apperson, R. W., +, TVLSI Oct. 2007 1125-1134 An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110 Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. Manohararajah, V., +, TVLSI Aug. 2007 895-903 Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Singh, M., +, TVLSI Nov. 2007 1256-1269 Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 Topology Utilizing Redundancy for Timing Critical Interconnect. Hu, S., +, TVLSI Oct. 2007 1067-1080 3-D Topologies for Networks-on-Chip. Pavlidis, V. F., +, TVLSI Oct. 2007 1081-1090 Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Trafc. Pandey, S., +, TVLSI Oct. 2007 1111-1124 Transceivers Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47 A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. Li, Y., +, TVLSI Jan. 2007 90-103 Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. Lai, J.-T., +, TVLSI February 2007 236-240 Transistors A Methodology for Transistor-Efcient Supergate Design. Kagaris, D., +, TVLSI April 2007 488-492 Signatures Reduce Defect Level and Yield Loss. Rao, L., Graphical I +, TVLSI Nov. 2007 1245-1255 Transmission lines Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 + Check author entry for coauthors
Tree data structures An Efcient Approach to On-Chip Logic Minimization. Ahmad, S., +, TVLSI Sept. 2007 1040-1050 Tree searching Relaxed K -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Trees (mathematics) Design Methodology for Global Resonant H-Tree Clock Distribution Networks. Rosenfeld, J., +, TVLSI Feb. 2007 135-148 Tunneling PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. Liu, Z., +, TVLSI Dec. 2007 1311-1319 Turbo codes High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. Shin, M.-C., +, TVLSI July 2007 801-810
U Ultrasonic equipment VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. Kumar, P. R., +, TVLSI Jan. 2007 118-123
V VLSI VLSI-Efcient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. Kumar, P. R., +, TVLSI Jan. 2007 118-123 A BIST TPG for Low Power Dissipation and High Fault Coverage. Wang, S., TVLSI July 2007 777-789 A Methodology for Transistor-Efcient Supergate Design. Kagaris, D., +, TVLSI April 2007 488-492 A Predictably Low-Leakage ASIC Design Style. Jayakumar, N., +, TVLSI March 2007 276-285 A VLSI Architecture for Image Registration in Real Time. Gupta, N., +, TVLSI Sept. 2007 981-989 Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Yamamoto, H., +, TVLSI June 2007 649-659 Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Joshi, A. J., +, TVLSI Sept. 2007 990-1002 Fast Passivity Verication and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. Saraswat, D., +, TVLSI Jan. 2007 48-59 High-Speed Recursion Architectures for MAP-Based Turbo Decoders. Wang, Z., TVLSI April 2007 470-474 Integrated Placement and Skew Optimization for Rotary Clocking. Venkataraman, G., +, TVLSI Feb. 2007 149-158 Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. Lai, J.-T., +, TVLSI February 2007 236-240 Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. Gregg, J., +, TVLSI March 2007 366-376 Relaxed K -Best MIMO Signal Detector Design and VLSI Implementation. Chen, S., +, TVLSI March 2007 328-337 Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. Zhang, T., +, TVLSI June 2007 624-636 Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. Kahng, A. B., +, TVLSI Aug. 2007 904-912 Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. Ku, J. C., +, TVLSI Aug. 2007 963-970 Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Iizuka, T., +, TVLSI June 2007 716-720 Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. Kim, T.-H., +, TVLSI July 2007 821-829 Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. Zhang, L., +, TVLSI Feb. 2007 231-236 Variational techniques Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. Ye, X., +, TVLSI Aug. 2007 913-926 Vector processor systems Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. Han, Y., +, TVLSI May 2007 531-540
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Video codecs Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Video coding Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. Hsia, S.-C., +, TVLSI June 2007 725-728 A Low-Power Multiplier With the Spurious Power Suppression Technique. Chen, K.-H., +, TVLSI July 2007 846-850 Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Conguration for Large Scale Processing Beyond HDTV Level. Iwasaki, H., +, TVLSI Sept. 2007 1055-1059 Video signal processing Run-Time Integration of Recongurable Video Processing Systems. Sedcole, P., +, TVLSI Sept. 2007 1003-1016 Viterbi algorithm Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 Voltage control Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. Chi, J. C., +, TVLSI June 2007 637-648 Voltage regulators Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. Lee, J., +, TVLSI Sept. 2007 1017-1027 Voltage-controlled oscillators Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. Acar, E., +, TVLSI Jan. 2007 37-47
A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231
W Watermarking IPP@HDL: Efcient Intellectual Property Protection Scheme for IP Cores. Castillo, E., +, TVLSI May 2007 578-591 Wave propagation Low-Power Rotary Clock Array Design. Yu, Z., +, TVLSI Jan. 2007 5-12 Wire Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. Maheshwari, A., +, TVLSI Nov. 2007 1239-1244 Wireless LAN An Energy-Efcient Recongurable Baseband Processor for Wireless Communications. Poon, A. S. Y., TVLSI March 2007 319-327 Wireless communication Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. Jin, J., +, TVLSI Oct. 2007 1172-1176 Wireless sensor networks A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. Seo, H.-M., +, TVLSI Feb. 2007 227-231 Wiring An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. Noguchi, K., +, TVLSI Oct. 2007 1101-1110

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO.

12, DECEMBER 2007

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