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nolo"y A#$% The main aim of the project is to design &Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm ec!nolo"y'( AB) *AC % An overview of performance analysis and compression between various parameters of a low power high speed conventional 1-bit full adder has been presented here. The work elucidated here gives a quantitative comparison of the adder cell performance. This paper shows the advancement over active power, leakage current and delay. The comparative study based on a new logic approach, which reduces power consumption. ith power supply of !."#, we have achieved and propagation delay of reduction in active power consumption of $%.&%n
!."'"ns, which makes this circuit highly energy efficient. (n this circuit we have reduced leakage current of 1').$nA. The designs have been carried out by virtuoso tool of cadence at *)nm technology.
B+OC, D#A-*A$%
The power consumption of the circuit is reduced to $%.&n *)nm and reduces further on reduction of the supply voltage.
for !."# at
5elay has also been improved and reduced to !."'" ns at !."# at *)nm technology. The comparison shows that the implementation of the full adder would be better at *)nm technology as compared to 1%!nm. *0F0*0.C0)% 6. /. 7abaey, 5igital (ntegrated .ircuits, A 5esign 8erspective, 8rentice 9all, 3nglewood .liffs, :6. 6. ;yemura, ./0- <ogic .ircuit 5esign, (-=: !-"$&'-%*)&-! >luwer. <. 6unming, -. ?an, <. @henghui and . <ing, AAA novel 1!-transistor low-
power high-speed full adder cellBB, (333 4th(nternational .onference -olidstate and (ntegrated.ircuit Technology, vol. &, pp. 11))-11)%. >. :avi, 0. >avehie, /. 7ouholamini, A. -ahafi and -. /ehrabi, AAA novel ./0- full adderBB, &!th (nternational .onference on #<-( 5esign held jointly with 4th (nternational .onference on 3mbedded -ystems C#<-(5B!"D, pp. '!'-'!", (ndia. :. este, >. 3shragian, 8rinciples of ./0- #<-( 5esign, A -ystems