Global Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel esting

!IM" The main aim of the project is to design Global Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel esting.

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3D integration is a promising technology that provides high memory bandwidth, reduced power, shortened latency, and smaller form factor. Among many issues in 3D ! design and production, testing remains one of the major challenges. This paper introduces a new design"for"test techni#ue called 3D"$%&', an efficient (uilt" n"&elf )epair *( &)+ algorithm to fulfill the test and reliability needs for 3D"stac,ed memories. nstead of the local testing and redundancy allocation method as most current ( &) techni#ues employed, we introduce a global 3D ( &) scheme, which not only enables redundancy sharing, but also paralleli-es the ( &) procedure among all the stac,ed layers of a 3D memory. .ur simulation results show that our proposed techni#ue will significantly increase the memory repair rate and reduce the test time similar speedup with at least /01 %D' reduction across all data activities !d&antage" 3D"$%&', is a real $lobal ( &) techni#ue, which enables the global redundancy sharing and parallel testing. The e2perimental results showed that our 3D"$%&' scheme can achieve 34.051 higher repair rate compared to the local ( &), and 6.371 over another global algorithm 8%&'. n addition, our scheme only re#uires
K.Aravind Reddy (Director) 9652926926, 9640648 Cell No:

59n testing time compared with the traditional ( &) procedure, where n is the number of stac,ed layers of 3D memories. Therefore, our scheme will significantly improve the manufacturing yield, repair rate, and testing throughput of 3D die" stac,ed memories. B'($) DI!GR!M"

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K.Aravind Reddy (Director) 9652926926, 9640648 Cell No:

R*+*R*,$*" @5A&. (ahl. A &harable (uilt"in &elf"repair for &emiconductor 8emories with 3"D )edundancy &cheme. n 33nd %%% nternational &ymposium on Defect and Bault Tolerance in C<& &ystems, pages 335D33>, 3004. @3A (. (lac, and et al. Die &tac,ing *3D+ 8icro architecture. n 'roc. of the nternational &ymposium on 8icro architecture, 3007. @3A E."B. !hou, D."8. Fwai, and !."G. Gu. 8emory )epair by Die &tac,ing with Through &ilicon Cias. n %%% nternational Gor,shop on 8emory Technology, Design, and Testing, pages /3D/6, 300>. @?A 8. Healy, F. Athi,ulwongse, ). $oel, 8. Hossain, D. Fim, E. "I. <ee, D. <ewis, T."G. <in, !. <iu, 8. Iung, (. .uellette, 8. 'atha,, H. &ane, $. &hen, D. H. Goo, ;. Jhao, $. <oh, H."H. &. <ee, and &. F. <im. Design and Analysis of 3D"8A'&: A 8any"!ore 3D 'rocessor with &tac,ed 8emory. n %%% !ustom ntegrated !ircuits !onference,3050. @/A A."!. Hsieh, T."T. Hwang, 8."T. !hang, 8."H. Tsai, !."8. Tseng, and H."!. <i. T&C )edundancy: Architecture and Design ssues in 3D !. n 'roceedings of the !onference on Design Automation and Test in %urope, pages 577D545, 3050.

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No:

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No: