Low-Complexity Reliability-Based Message-Passing Decoder Architectures for on-Binary LDPC Codes

A!M" The main aim of the project is to design #Low-Complexity ReliabilityBased Message-Passing Decoder Architectures for on-Binary LDPC Codes$% AB&'RAC'" Non-binary low-density parity-check (NB-LDPC codes can achie!e better error-correcting performance than their binary co"nterparts at the cost of higher decoding comple#ity when the codeword length is moderate$ The recently de!eloped iterati!e reliability-based majority-logic NB-LDPC decoding has better performance-comple#ity tradeoffs than pre!io"s algorithms$ This paper first proposes enhancement schemes to the iterati!e hard reliability-based majoritylogic decoding (%&'B-(L)D $ Compared to the %&'B algorithm* o"r enhanced (+- %&'B algorithm can achie!e significant coding gain with small hardware o!erhead$ Then low-comple#ity partial-parallel NB-LDPC decoder architect"res are de!eloped based on these two algorithms$ (any e#isting NB-LDPC code constr"ction methods lead to ,"asi-cyclic or cyclic codes$ Both types of codes are considered in o"r design$ (oreo!er* no!el schemes are de!eloped to keep a small proportion of messages in order to red"ce the memory re,"irement witho"t ca"sing noticeable performance loss$ %n addition* a shift-message str"ct"re is proposed by "sing memories concatenated with !ariable node "nits to enable efficient partialparallel decoding for cyclic NB-LDPC codes$ Compared to pre!io"s designs based

K.Aravind Reddy (Director) 9652926926, 9640648

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on the (in-ma# decoding algorithm* o"r proposed decoders ha!e at least tens of times lower comple#ity with moderate coding gain loss$ BL(C) D!A*RAM"

-ig. /N0 architect"re when

messages are kept$

'((L&" 1ilin# %2+ 3$4 % and (odel2im 5$6c$

APPL!CA'!( AD+A 'A*,&" 7ith moderate performance loss* the proposed decoders can achie!e at least tens of times higher efficiency compared to pre!io"s designs based on the (in-ma# algorithm$

K.Aravind Reddy (Director) 9652926926, 9640648

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 -"t"re work will be de!oted to f"rther impro!ing the performance and red"cing the hardware comple#ity of (L)D-based algorithms for NBLDPC decoding$

R,-,R, C,&" L$ Barna"lt and D$ Declerc,* 8-ast decoding algorithm for LDPC o!er *9 in Proc$ %nf$ Theory 7orkshop* 4::;* pp$ <:=<;$ &$ 7ymeersch* &$ 2teendam* and ($ (oeneclaey* 8Log-domain decoding of LDPC codes o!er *9 in Proc$%+++%nt$Conf$ Comm"n$* 4::6* pp$ <<4=<<5$ C$2pagnol*+$Popo!ici*and7$(arnane*8&ardwareimplementation of LDPC decoders*9%+++Trans$Circ"its2yst$%*'eg$Papers* !ol$ >5* no$ ?4* pp$ 45:3= 454:$ D$ Declerc, and ($ -ossorier* 8Decoding algorithms for nonbinary LDPC codes o!er *9 %+++ Trans$ Comm"n$* !ol$ >>* no$ 6* pp$ 5;;=56;* @pr$ 4::<$ /$2a!in*8(in-(a#decodingfornonbinaryLDPCcodes*9inProc$ 2ymp$ %nf$ Theory* 4::A* pp$ 35:=356$ %+++ %nt$

K.Aravind Reddy (Director) 9652926926, 9640648

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