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VARDAMAN: The Road to Recovery
Optimizing
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Soldering
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Clive Ashmore
22 More than Just a Look
SPI market leader Koh Young is shrugging off the recession and taking Europe head on.
CIRCUITS ASSEMBLY visits the OEM to learn why now, and to get an in-depth look at its new 3-D
16 Better Manufacturing AOI machine.
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Jeff Knight
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24 Wave Soldering
Optimizing the wave process is no simple feat. Fluid Dynamic Simulation for Cool Designs
Dr. Ursula Marquez de Tino Computational fluid dynamics-based simulations that examine temperature and heat flux can
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26 Tech Tips By Robin Bornoff
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Market
WATCH Edited by Chelsey Drysdale
A/V Up
Trends in the U.S. electronics equipment market (shipments only). 2010 Recovery for Equipment
------------- % Change --------------
April Aprilr April* YTD
Production
Computers and electronics products -1.0 3.0 -1.9 -14.5 LOS ALTOS, CA – The dismal picture for global equipment produc-
Computers -9.1 3.3 -1.8 -20.4 tion should brighten considerably next year as worldwide equip-
Storage devices 10.7 -0.7 -2.7 -21.9 ment production is predicted to expand 5.4% in 2010 and 8.4% in
Other peripheral equipment 4.9 -7.3 0.5 -11.3
2011, says research firm Henderson Ventures (hendersonventures.
Nondefense communications equipment 3.0 -4.5 -2.6 -23.5
com).
Defense communications equipment -15.0 10.5 -9.1 13.9
A/V equipment 2.0 -7.1 15.1 -30.6
The rebound is a dramatic improvement over the 12.3% decline
Semiconductors -3.7 40.4 -9.0 -30.9 Henderson forecasts for this year. While each region is forecast
Components1 -1.1 -1.9 -1.6 -19.6 to see a drop in 2009, China will take the smallest hit, at 6.6%.
Nondefense search and navigation equipment -4.5 -6.6 0.4 -13.2 Japan’s output is forecast to drop 21.3%, slammed by investment
Defense search and navigation equipment 0.4 -0.6 0.8 -2.7 retrenchments and plant closings. The US is forecast to drop 10.1%
Medical, measurement and control 0.0 -0.8 0.7 3.8
this year, then rebound to 3.3% growth in 2010.
rRevised.
*Preliminary. 1Includes semiconductors. Seasonally adjusted. Source: U.S. Department of
Commerce Census Bureau, July 2, 2009
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On the
Forefront The Backend Will Feel the Bumps
For many package subcontractors, the road to recovery won’t be smooth.
S
emiconductor industry infrastructure? A typical assem- merge with larger ones, and the
analysts argue that the bly line for a wire-bonded pack- equipment infrastructure will be
worst is behind us. In the age consists of systems for dicing, maintained. For example, ESEC
second quarter, wafer shipment cleaning, die attach, wire bond, is now a part of BESI, and ESI has
growth is tracking at over 50% epoxy mold and curing. If the purchased the assets of XSiL. In
quarter-over-quarter at TSMC, package is a BGA or CSP, equip- some sad cases, operations will
UMC, SMIC and Chartered. ASE, ment for solder ball attach, reflow simply cease to exist. Agilent, for
Amkor and SPIL reported posi- and cleaning are also needed. If the instance, announced the closures
tive revenue growth during the package is a leadframe, some lead of its AOI and AXI business units.
period, and are optimistic about forming and excise equipment will Is this of concern, or is this just
the third quarter. Yet, while each be part of the process. Inspection another part of the semiconductor
quarter may be better than the systems also are used at the final supply chain that will contract?
last, the road to recovery for the part of the assembly process. If the Fewer material choices? Materi-
backend equipment OEMs and package has flip chip instead of als such as substrates, leadframes,
material suppliers may be a bit wire bond, the die attach and wire bonding wire, mold compounds,
bumpy. bond will most likely be replaced underfill materials, dielectrics,
Advanced packages, comprised by a pick-and-place system for plating solutions, solder balls,
of ball grid arrays and chip-scale mounting the flip-chip die on the thermal interface materials, and
packages, are the source of much substrate, underfill dispense, and a variety of other products are
of the unit and revenue growth cure system. Test sockets, burn-in also part of the infrastructure.
in the semiconductor packaging ovens, test handlers, and testers The materials sector has already
and assembly sector. While BGA are all part of the backend infra- seen consolidation (Henkel’s
and CSP shipments will improve structure, not to mention dic- acquisition of National Starch's
quarter-over-quarter, unit vol- ing blades, wire bond capillary Ablestik and Emerson & Cum-
umes will not return to 2008 lev- tools, bonder heads, nozzles and ing business; Dow Chemical’s
els until 2011. Wafer-level pack- a host of other components used acquisition of Rohm and Haas.)
aging seems a bright spot, with in the assembly process. While In Taiwan, substrate suppliers
many companies favoring use of some equipment suppliers are part PPT and Unimicron will merge.
WLPs instead of some conven- of large organizations, many of Will this result in few choices of
tional packages because of their the companies that make up this suppliers, and shortages? In Tai-
smaller form factor and lower infrastructure are relatively small wan, Chipbond reports the LCD
profile. With this year’s capital in size and revenue, and would driver IC backend assembly busi-
expenditures for the top four IC feel a prolonged period of slow ness is experiencing a shortage
package subcontract assembly sales. What does this mean for of substrates (tape in the form
and test operations expected to our industry’s future? As Business of chip-on-flex). Will prices rise
be less than half the dollar value Week noted in June, tech compa- over time? Will material suppli-
in 2008, many backend assembly nies have seen the deepest cuts ers be healthier in the future and
E. Jan Vardaman equipment makers may face hard in global capital spending, down therefore able to invest resourc-
is president of times over the next 18 months 28% year-over-year. This much is es in materials to meet future
TechSearch Interna- (Figure 1). The key question then certain: Even if these companies industry needs? These questions
tional, (techsearchinc. is, Are these companies strong survive, few will be able to afford remain.
com); jan@techsearch enough to survive such a pro- to devote resources to R&D for the Future shock. Semicon West
inc.com. Her column tracted dry spell? Even if they next generation of packages. In this year had fewer companies
appears bimonthly. are, can we expect any advances some cases, these companies will for the semiconductor backend
in assembly technology over the assembly sector, and part of the
next two years? What level of Table 1. Capex Spending, Top 4 Package reason certainly was the down-
orders will sustain R&D activities Subcontractors turn. The question remains, after
for the development of future Year Capital Expenditures the recovery, will these companies
equipment (and materials)? 2008 $1,263 million return, or will empty halls echo
2009 $530 million
Feeling the pinch. What makes with the sounds of ghosts from
Source: TechSearch International, Inc., adapt-
up backend assembly equipment ed from Goldman Sachs our industry’s past? n
M
ost would consider screen printing a single our AOI results and analysis turned up some strange
process: the first step in the assembly line. trends. When we evaluated the stencils in question,
However, understencil cleaning is a process we found lint contamination. In most instances, we
itself: a screen-printing sub-process. Not only must were finding low paste volumes, which were directly
the production engineer be adept at printing tech- attributable to lint blockage of the apertures. In one
niques, but cleaning parameters and routines as well. case, a lint particle had become drenched in paste, and
Understanding software features such as cleaning the inspection system actually viewed it as a bridged
rates (how often should you clean) and modes (wet, deposit. Keep in mind the lint issue is primarily a
dry, vacuum and their various combinations) is criti- problem for the dry cycle, but the fabric selection
cal and, of course, highly application-dependent. The impacts wet and vacuum cycles too.
industry default mode is generally wet/dry/vac – not Ever tried to breathe through a paper towel? How
that it is necessarily the right choice always, but that about a piece of printer paper? I’d argue the former
is what most operators are used to. Aside from deter- is more beneficial for your oxygen intake. The same
mining rates and modes, cleaning materials selection theory holds true for the vacuum on the printer’s
is also tantamount to a robust cleaning process. The understencil cleaning system. You’re trying to pull
understencil fabric and solvents used to remove solder vacuum through the fabric to clean out the apertures
paste from today’s ever-smaller apertures play a large and, hopefully, dislodge and then capture all the
part in the success of the cleaning sub-process, and residual paste into the open weave of the fabric. If the
the overall print process. weave is too dense, you are blocking the vacuum, thus
As an example, let’s take a look at the fabric. Obvi- compromising its power and your cleaning process.
ously, the main goal with any cleaning fabric – even You want a fabric constructed of porous material that
those used at home – is to clean the object free of permits air flow, yet captures material into the pores
debris at the end of the process. Unfortunately, quite of the fabric.
a few understencil cleaning materials don’t do that. Then, of course, there is the wet bit. The solvent
Instead, they put lint back onto the stencil, which may selected can most certainly have an impact on print
in turn block apertures. I’ve heard many engineers performance (a topic for another column). Consider
debunk the lint effect, arguing a 10 µm thread would the importance of how the fabric wicks the solvent
have little to no impact. That may have been true five across the exposed area of the material. The solvent
years ago when, by comparison, apertures were fairly breaks down solder paste that remains on the outer
big. Today it’s a whole new ballgame. edges of and inside the aperture walls, so a fabric that
In fact, during some recent stencil testing using absorbs the solvent uniformly is desired. This must
various understencil fabrics, our company discovered be a stable and highly repeatable process to be effec-
lint is, indeed, quite problematic. With 0.3 mm CSPs tive. The material should be fast and absorbent, and
that required aperture sizes of approximately 180 µm, should almost instantly start wicking and create one
solid bar across the fabric. What you definitely don’t
want is a quick wick that keeps on wicking all the way
DIY Fabric Tests through the paper because then, when you index the
paper along for a dry wipe, it would still be wet. A
Clive Ashmore
is global applied
Here are three easy, do-it-yourself fabric performance
good solvent process is primarily about the absorp- process engineering
tests:
tion rate of the fabric and also a little bit about the manager at DEK
• Lint: Take a piece of Scotch tape, adhere to fabric,
ability of the machine’s solvent bar to dispense the (dek.com);
press down and then rip it off. You will quickly see if a so-
solvent at consistent volumes. If the fabric doesn’t cashmore@dek.com.
called “lint-free” material actually lives up to its claim.
wick properly, a thorough clean is unlikely. This His column appears
• Vacuum: Simply turn the vacuum on and feel the
introduces the potential for blocked apertures and, bimonthly.
flow to sense the power and volume of the air coming
therefore, defects.
through the weave. More elaborate air-flow measure-
The bottom line: Treat the understencil cleaning
ment mechanisms can be used, but a simple “touch and
process with as much rigor and attention as the other
feel” should do the trick.
parameters of the screen-printing operation. Don’t
• Wicking: Cut a strip of fabric, place a line of solvent
skimp on the fabric because, in the end, a few more
across it with a basic dropper and evaluate the speed and
cents for a high quality material will likely save big
uniformity of the wicking.
bucks. n
T
he electronics interconnection industry is con- As readers know, defense programs have been a
tinually changing. Not only is the technology growing and profitable piece of electronics manufac-
becoming more complex, the nature of business turing over the past several years. In military programs
itself is rapidly evolving. The rise of the EMS segment specifically, suppliers have learned that in order to be
of the industry, accompanied by the swift demise of considered for production work, fabricators must be
vertically integrated OEMs, has pushed printed circuit able to provide quickturn, early user hardware/pro-
board design, fabrication, assembly and test expecta- totype boards. Customers use these boards to verify
tions of the current suppliers to their technical limits. the design, and expect their fabricators to offer advice
Today, with reduction of the new product introduction regarding design for performance and manufacturabil-
(NPI) cycle time, time-to-market is critical for busi- ity, along with delivering on time and within budget.
nesses to remain competitive. Acceptance criteria for QT and prototype products
Quickturn and prototype services make up an is another matter to consider, as they may differ from
important segment of the PCB fabrication market and the volume production requirements due to the use
it is imperative that North American suppliers offer and expectations of those products. Furthermore, dis-
this capability. However, today’s cussions defining when the clock
requirements go beyond the starts for ultimate delivery of
typical QT feature card designs
and now include new dense PCB Acceptance criteria a quickturn order and require-
ments for accepting design data
fabrication with more complex-
ity, higher layer counts and more
for QT and prototypes need to be clearly communicated
at the forefront of any project.
precise registration than previ- may vary from those Quickturn and prototype ser-
ously required. Regardless of the vices are not only an important
complexity, fast cycle time has of volume production. differentiator for North Ameri-
become an expectation, which in can PCB fabricators today, but
turn has led many suppliers to it is also an essential part of
exit the business rather than make remaining competitive and satis-
the large capital investment required for new, state- fying customer’s expectations. While there is an upside
of-the-art tools with advanced processing capabilities to providing these services – premium pricing, gaining
necessary to stay ahead of the technology curve. Those entry into potentially higher volume production and
suppliers that remain have picked up the customers new customers – huge investment is also required to
of the departed, but continual capital investment, as maintain a competitive edge. n
well as investment in the technical personnel required
to develop new processes capable of running new and
advanced materials on state-of-the-art equipment, is
required (not to mention expensive).
For the customer, the payback of QT and proto-
type services is recognized in a significant reduction
in process cycle time and process costs, which provides Stake Out
Jeff Knight is vice
president of busi-
additional capacity and gets products to market faster.
Doing so, however, means that the production fabrica- Your Territory
ness development at tor must be able to produce the same highly complex
Endicott Interconnect product as the quickturn fabricator, lest all the time and
Technologies (eitny. effort be wasted. Thus, many end-customers are looking
com). for fabricators capable of providing a rapid turn for the Learn how by calling
early user hardware or prototypes along with the ability Krista Fabian today
to supply the low volume ramp and volume production
quantities of their products. To do this, the QT/proto- at 678-589-8840.
type line must be a mirror image of the production line
with identical processes, chemistries, and techniques
implemented, plus a common set of design and data
release tools used for both production and QT.
By Tom Adams
W
hen engineers go through the task of pinning down the it is a bubble flattened by the pressure of overlying layers), while a
cause of one or more field failures, the cause often turns delamination is simply a thin horizontal gap.
out to be a damaged or failed multilayer ceramic chip Voids and delaminations can be the precursors of cracks. Cracks
capacitor. The nature of a field failure caused by a bad capacitor also can be caused by variable porosity in the dielectric layers, a
may range from total system failure to a failure of one or more condition in which irregularly distributed microscopic air bubbles
system functions, to an intermittent failure, the latter of which can weaken the ceramic.
mimic a software problem. The photo on the cover of this month's issue shows the acous-
Here, we look at the mechanical causes of failures in MLCCs tic image of an MLCC that contains a single void. In performing
from the fabrication of the capacitor through system assembly. acoustic imaging of an MLCC, the scanning ultrasonic transducer
Much of the detailed information comes from Sonoscan’s applica- of the acoustic microscope pulses ultrasound into the MLCC sev-
tions laboratories, which have imaged acoustically and analyzed eral thousand times a second as it moves back and forth across the
tens of millions of MLCCs. MLCC. A fraction of a microsecond after pulsing, it also registers
An understanding of how mechanical anomalies can cause elec- the return echoes from within the MLCC. System software typically
trical failure in MLCCs is important for three reasons: accepts return echoes from just below the top surface of the MLCC
1) End-of-line electrical testing usually does not detect a to just above the bottom surface, a technique known as bulk imag-
mechanical anomaly because the electrical signature of the anom- ing. A defect-free MLCC will send back no return echoes, but an
aly is minute or absent at this time. MLCC having any gap-type defect such as a void, delamination or
2) A mechanical anomaly may endure weeks or months of ser- crack will send back very high amplitude echoes from the defect.
vice use before it changes or expands enough to reveal itself as an (Here, the void appears red, which is highest level on the color map
electrical failure. at left, because the solid-to-air interface reflects nearly all of the
3) The number of field failures resulting from a single type of ultrasound.) The amplitude is very high because of the extreme
mechanical anomaly can be large. difference in acoustic properties between the solid material of the
Defects introduced during manufacture. MLCCs are made by laying capacitor and the air inside the defect. It is this interface between a
down alternate layers of dielectric and electrode materials, and then solid and gas that reflects virtually 100% of the pulsed ultrasound
firing the capacitors. Of the three most frequent types of internal and produces an acoustic image of the anomaly.
damage (voids, delaminations and cracks), two – voids and delami- Voids such as the one shown on the cover are important because
nations – can form during the manufacturing process. Cracks as a they can cause long-term failures in MLCCs. For example, a void
result of manufacturing processes were frequent a decade or two may be located in the middle of one layer of dielectric. This may
ago, but have been made rare by more precise control over the seem like a harmless location, and in some capacitors it is harm-
processing. Voids are most often tiny air bubbles trapped within less. But the electric field between two electrodes may cause metal
the capacitor. A void can be very much flattened – its width might to migrate and to plate the inner surface of the void. Eventually, a
be 100 times its height – but dielectric material will be missing weak current may begin to flow between the electrodes. Ultimately
from one or more layers. A delamination is simply a non-bonded – weeks or months after the beginning of field service, perhaps
area between layers, without loss of dielectric material. When an – the metal plating becomes substantial enough to cause a short.
MLCC is cross-sectioned, a void is typically lens-shaped (because Many of the MLCCs imaged in Sonoscan’s laboratory are destined
Figure 1. The acoustic image of this MLCC reveals many small voids
formed by dust particles, and a larger elongate void formed by an
organic fiber.
ceptible to moisture-related damage than plastic-packaged ICs. go through assembly and are imaged acoustically again after reflow
In theory, moisture can collect within a capacitor and fill an exist- or wave soldering, to remove those steps as causes of the cracks. The
ing void (with destructive results when the moisture flashes into panel is then separated by the same method used for the MLCCs
steam), but such events are far less common in MLCCs than they that caused field failures, and the boards examined acoustically for
are in plastic-packaged ICs. The very small dimensions of some telltale vertical cracks near the terminations. n
MLCCs also may make it harder for moisture-related damage to
occur because the much higher ratio of surface area to volume lets Tom Adams is a consultant at Sonoscan, Inc. (sonoscan.com);
moisture escape more rapidly. tom100adams@comcast.net.
Whether a damaged MLCC can be identified during end-of-line
electrical testing depends first on the extent of
the damage. A small crack or other anomaly
that has not (yet) created contact between
adjacent electrodes will not be identified, even
though it may expand and cause an electrical
failure later. An anomaly that has created a
leakage current within the MLCC might be
found if the MLCC serves an essential func-
tion within the signal path. But an MLCC in
a decoupling role can be found only by exam-
ining the noise level in the supply lines.
These constraints make acoustic imaging
of MLCCs after reflow or wave soldering an
important tool. Finding cracks in a significant
number of MLCCs, or in MLCCs at specific
locations on the board, gives the opportunity
to change process parameters and remove the
stresses generating the cracks. Acoustic imag-
ing is often carried out during R&D or during
pilot production, but also may be used peri-
odically during full production to eliminate
the possibility of field failures.
During assembly, large panels are in some
fashion separated into individual printed wir-
ing boards. Cracks can form in MLCCs during
the separation process. These cracks are most
likely induced when the panel sections are
snapped apart, but they can occur with other
methods of separation and are sometimes
more frequent near the edges of the board,
where mechanical stresses are presumably
higher. They are generally more likely when
Pb-free solders are used, because Pb-free
solders are quite rigid. SnPb solder is more
plastic and better at absorbing mechanical
stresses. Separation-related cracks are likely
to be near the terminations and are likely to
be vertical, and are most easily found with the
method for vertical crack detection developed
at Sonoscan.
When cracks caused by the panel separa-
tion process are suspected of causing field
failures, their role can be clarified by first
performing acoustic imaging on unmount-
ed MLCCs, preferably from the same lot.
Unmounted MLCCs with no internal defects
By Fred Dimock
T
he change from eutectic to Pb- and temperature uniformity of a 100 The plan was to individually vary
free solder has required new and 230 g populated surface mount each parameter (high and low) and
recipes for reflow ovens. Solder board. record its effect on the TAL, peak
paste manufacturers have developed temperature and uniformity of each
profile parameters, but it remains Experimental board. An additional run was per-
the responsibility of the assembly A Pyramax 98 N reflow oven with formed with all variables at the high
engineer to find the correct control edge rails, fine mesh belt, and closed and low settings to see the combined
settings with a limited number of loop pressure control was used for effect.
reflow oven adjustments. Additional this experiment. A recipe that pro- High and low ranges were estab-
complications exist because the liq- duced a Pb-free ramp-to-peak profile lished for each of the variables, as
uidus temperatures of the new sol- with a belt speed of 28 IPM and static outlined in Table 2. Data were gath-
ders require peak temperatures close pressure of 1.0 IWC was chosen as a ered with a SlimKIC II profiler.
to the point at which components are baseline (Table 1).
damaged. Thus, the importance of
accurate recipes and precision oven Table 1. Baseline Recipe Table 3. Board Weight Results
control is amplified. E Set Points E 100 G 250 G
Conventional reflow ovens have Z1 100 °C Peak (°C) 231.6 225.5
two adjustments for profile devel- Z2 125 °C TAL (sec.) 33.18 25.07
Figure 1. SlimKIC II profile of the 100 g board. Figure 2. SlimKIC II profile of the 230 g board.
Results lowered the peak temperature and TAL, 7). Uniformity was considerably bet-
The 100 and 230 g boards were run at and slightly decreased the temperature ter with the high oven parameters. In
the baseline operating parameters of uniformity at the peak. the case of the heavy board, the peak
28 IPM, 1.0 IWC and zone 7 set points Zone temperature. The oven was reset temperature did not reach the liquidus
of 250°C. Figures 1 and 2 show the to the baseline parameters, and the when all the settings were set low.
resultant profiles for the 100 and 230 temperatures in zones 6 and 7 were Today’s high performance reflow
g boards, respectively. Table 3 shows increased and decreased by 10°C. Peak ovens have three adjustments that per-
the peak temperature and TAL data for temperature and TAL increased with mit recipes for solder reflow profiles. A
the boards. There was a difference of the higher zone temperature settings recipe that works for one board won’t
about 5°C at the peak and 8 sec. in the and the uniformity decreased (Table necessarily work for another board if
TAL between the two boards because of 5). the weight or design is significantly
weight and board design. Static pressure. The oven was reset to different.
Belt speed. Belt speed was varied the baseline parameters and the pres- Of the three oven adjustments, the
from 24 to 32 IPM with the static pres- sure varied from 0.7 to 1.3 IWC. The zone set points have the biggest effect
sure and zone set points at the baseline increased static pressure increased the on the peak temperature and TAL.
settings. Table 4 shows the peak tem- peak temperature by about 5°C and Changing the belt speed also affects the
perature, TAL and uniformity data for TAL by about 10 sec. (Table 6). The peak temperature and TAL, to a lesser
each board. The increased belt speed uniformity at peak was significantly degree. But the static pressure not only
better with the higher static pressure. affects the peak temperature and TAL,
Table 6. Static Pressure Changes
High and low interactions. Next, the it has the biggest impact on uniformity
E 100 G 250 G
combination of all the high tempera- at peak temperature.
Pressure 0.7 1.3 0.7 1.3
ture parameters (low belt speed, high Pb-free solder’s more stringent pro-
Peak (°C) 229.2 234.0 222.0 227.3
zone set points, and high static pres- cess requirements make it important
TAL (sec.) 26.94 35.79 18.12 29.20
sure) and low temperature parameters that all three adjustments – zone tem-
Uniformity 2.3 1.7 2.3 1.5
(high belt speed, low zone set points, perature set points, belt speed and
and low static pressure) was used to static pressure – be used when develop-
Table 7. Interactions
determine the interactions on each ing recipes. n
E 100 G 250 G
board. There were significant changes
low high low high
Peak (°C) 218.4 245.7 210.6 240.2
in all the profile attributes, with about Fred Dimock is senior process engineer at BTU
TAL (sec.) 4.21 59.36 0 49.25
30°C differences in peak temperature International (btu.com); fdimock@btu.com.
Uniformity 2.7 1.6 2.6 1.5 and close to 50 sec. in TAL (Table
By Mike Buetow
O
n the subject of expansion, every since. at Vitronics-Soltec.
business case study says the best Why Europe, and why now? Its staff in place, the company was ready
time to do it is during a downturn. The stage for Koh Young’s migration to to make its move. After some discussion and
Take advantage of the market lull to grab Europe was set by Pieter Stins, a veteran of due diligence, it settled on Alzenau, which
market share, the researchers say. Vitronics-Soltec and Nutek, who saw a Koh offered ready access to the key German
Few do. It’s much safer to protect cash Young SPI machine at Productronica and, market, which still dominates electronics
and other assets than to risk failure (and though on the cusp of retirement, decided manufacturing in Western Europe, but was
one’s job). In other words, follow the herd. to buy one and build a new distribution centrally located and accessible to both the
Following the herd isn’t what Koh Young company around it. (That company, PPT, is traditional pockets in Italy and France, and
Technology (kohyoung.com) is about. The now Koh Young’s distributor in Germany, the emerging markets of Eastern Europe.
vision machine maker in May opened the Austria, Switzerland and parts of Eastern The new center has in place the full
doors on its pristine new demo and training Central Europe.) Meanwhile, in Asia, Koh range of the Koh Young platform, including
center in Alzenau, Germany, about 45 min- Young was going gangbusters, and looking the previously released 8030-2 and 8030-3
utes from Frankfurt’s international airport. to extend its reach abroad. SPI machines, on which the company built
(The event coincided with a less auspi- Having gone public on Korea’s KOS- its name and reputation; a KY-3020T, which
cious debut of its Ireland office, which will DAQ exchange in June of last year, and hit is the semiautomatic tabletop version; and
handle sales, support and administrative $35 million in sales in fiscal 2008, Dr. Koh the aSPIre-2 SPI, the four-way light projec-
functions.) embarked on a five-year plan with the goal tion system that also debuted at Apex.
The new offices are set to serve conti- to reach $150 million in annual sales, which The new site also features an Ekra screen
nental Europe, the UK and Ireland, where would make it by far the larg-
the company through May had sold 230 of est OEM of electronics assembly
its 940 installations worldwide. inspection equipment (Table 1).
In making the announcement, founder Seeking to make its mark on
and chief executive Dr. Kwangill Koh said, the West, Koh Young turned to
“Today we celebrate a significant mile- two well-known industry veter-
stone in the growth of Koh Young as a ans: Harald Eppinger and Thor-
global company. The European market a sten Niermeyer. Niermeyer, who
key growth area, and the establishment a previously worked for Agilent
strong presence here, in conjunction with and MVP, was named global sales
the introduction of our revolutionary new director, based in Ireland, while
3-D AOI technology, will fuel that growth.” Eppinger runs the Germany
That “revolutionary new 3-D AOI tech- office as European sales manager.
nology,” of course, refers to the Zenith It also brought aboard André Opening doors. With help from global sales director Thor-
machine, which debuted at Apex in April Myny as global marketing direc- sten Niermeyer, Dr. Kwangill Koh cuts the ribbon at the new
Koh Young facility in Germany. European sales manager
and has been making media waves ever tor, a role he previously handled
Harald Eppinger is in the foreground at right.
printer for hands-on process training with Table 1. KY SPI Market Share, By Year
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W
hat are the best settings for a wave solder- may be required to activate it.
ing process? The answer is not as simple as When surface mount components (i.e. chip com-
one might think. Much depends on the flux ponents) are glued to the bottom side of the board, it
type and end-product. However, adherence to some is important to ensure that the ΔT between the tem-
basic rules will ensure a robust process. A good wave perature of the components and solder temperature
process depends on establishing correct machine is between 100° and 110°C. It is important to follow
and product parameters. Fluxing, preheating, con- the supplier’s specifications for wave soldering sur-
veyor speed, solder temperature, dwell time, wave face mounted components.
height, wave type, nitrogen and exhaust are machine Conveyor speed. A typical conveyor speed setting
parameters, while board complexity, component will be in the range of 1 to 1.5 m/min. The speed
types, flux type and pallet use are product param- setting depends on board complexity. Single-sided
eters. All these parameters interact and therefore boards often can be soldered at high speed because
should be optimized to work in harmony. they often have a low thermal demand and no plat-
A wave soldering process breaks down into the ed-through barrel, and thus do not require topside
following categories: fillets. A multilayer board may have a high thermal
Fluxing. The correct amount of flux to be applied demand and 1 m/min could be too fast. To optimize
per board is based on the flux supplier’s specifica- the conveyor speed, it is also important to consider
tions. Excessive flux may interfere with the product’s the board layout at the solder side, which can be a
electrical reliability, and a moderate amount of flux decisive factor to prevent solder bridging.
may not provide sufficient tail activity to reduce Soldering temperature. The solderpot temperature
bridging and to obtain good through-hole penetra- setting depends on the type of solder, but also may
tion when the board leaves the wave. It is extremely be related to the product to be soldered (i.e., board
important to optimize fluxer settings, which are complexity, pallet use, or exposed bottom-side sur-
related to conveyor speed. Visual testing should be face mount components). In general, low tempera-
used to ensure proper overlap and penetration of ture settings are recommended to avoid board war-
flux. With alcohol-based flux, thermal fax paper page and component damage. Lower temperatures
can be used on the bottom of the assembly and create less dross, and extend the lifetime of the flux
processed through the fluxer only. A visual footprint so that it has better tail activity. During soldering,
then can be seen and areas missed by the flux pattern the topside board temperature must be below the
identified. The same is true if the paper is applied to melting point of the surface mount component
the top of an unassembled board. The paper must joints to avoid double reflow. For SnPb solders, 245°
be fixed to the assembly to avoid movement during to 250°C is a common setting. For SAC alloys, 260°
flux application. For water-based flux, pH paper can to 265°C is the recommended setting. It is important
be used. Also commercial test fixtures can be used to keep the solder bath volume constant to maintain
Ursula Marquez for flux test application. The appropriate flux type soldering temperatures.
de Tino, Ph.D. is a (i.e., alcohol- or water-based fluxes) depends on the
process and research application, board surface finish, solder resist, board
engineer at Vitron- complexity and other issues.
ics Soltec, based in Preheating. Board preheating is necessary to evap-
the Unovis SMT Lab orate flux solvents and to prepare the board and
(vitronics-soltec.com); flux for soldering. Preheating also is used to reduce
umarquez@vsww.com. thermal shock of components and to promote bet-
Her column appears ter through-hole penetration, especially for multi-
monthly. layer boards. The flux supplier specifies preheating
parameters. For the case of alcohol (i.e., isopropyl)
fluxes, the board topside temperature should be
above 82°C, and for water fluxes above 100°C. Com-
plete evaporation of the solvent is important to
reduce soldering defects such as openings, voiding,
and solder balling. Depending on the type of flux
Figure 1. One of three wave types, main wave creates a
and board thickness, higher preheat temperatures smooth wave that prevents bridging.
Cost-Effective
Networking &
Sales Solution
SMTA Expo & Tech Forums are co-sponsored by local SMTA Chapters and SMTA Headquarters
A
n inquiry led to an investiga- dewetting were noticed on resistors, the pad areas, exposed copper under
tion on the possible causes of capacitors or leaded chip devices. the HASL surface finish, and non-
printed wiring board failures, The reflow oven has four zones uniform HASL finish in certain cases.
which were becoming increasingly and short length, but no issues around XRF inspection. BGA devices and
prevalent after SMT manufacturing. reflow quality were seen as a result. bare board were analyzed using x-ray
Failures were detected by electrical The recommendation was made fluorescence to determine the alloy
testing, but the location and specif- to increase to a seven-zone oven to composition of the metal (Tables 1
ic devices causing the failures were increase profiling flexibility for vari- and 2). This is a common method
undetermined. The failures were sus- ous designs. used when the composition of the
pected to be predominantly in the Reflow profile. The reflow pro- component alloy or surface finish is
BGAs located on specific sites on this file was in the specified range for in question.
16-layer construction. Failure data the solder paste of choice (Alpha XRF summary. Components indi-
provided included high resistance WS-809). Thermocouple placement cate a eutectic or near eutectic SnPb
shorts occurring in those specified was in appropriate locations, and the composition. Analysis of the HASL
areas. The surface finish was a eutectic temperature uniformity among each finish indicated a non-uniform thick-
HASL, and the solder paste was a location reflected an even distribu- ness, and at certain locations, the fin-
water-soluble SnPb. tion of heat. The time above liquidus ish was thin enough to permit the
The diagnostic approach agreed (TAL) varied by only 6 sec. between underlying copper to overwhelm the
upon included an examination of the highest and lowest time, while alloy analysis.
both the quality of the manufactur- the peak temperature varied by 13˚ X-ray analysis. X-ray analysis was
ing process and the materials used for among locations. There was no evi- performed on a populated board at
assembly, as reviewed below. dence of hot or cold spots. the various BGA locations suspect-
SMT process. The first order of The assembly TAL averaged 90 ed as problematic. No evidence of
diagnostics, a manufacturing audit to sec., well within the vendor-recom- shorting opens or misalignment was
assess the SMT process, revealed: mended TAL range of 40-120 sec. As prevalent.
Solder paste was properly stored reflow was clearly achieved, and there Optical endoscope. The populated
and permitted to reach ambient con- was no evidence of cold solder joints, assembly was analyzed through an
ditions prior to use. The solder mesh a recommended step was to decrease endoscope to see any evidence of
was appropriate for the type of assem- the TAL from 90 to 60 sec., which incomplete collapse or other observ-
bly, and the paste was not expired. would improve wetting without a risk able phenomena such as dewetting
Stencils used for paste application of incomplete solder reflow. However, or head-in-pillow effect. No unusual
were properly proportioned with an the present reflow profile is consistent occurrences such as excessive solder
aperture size appropriate to the BGA with the recommended parameters or flux residue were visible. However,
device pitch. prescribed by the solder paste vendor. the graininess of the solder balls may
The stencil printing operation Bare board inspection. A visual indicate the start of an oxidizing sur-
revealed no flaws, and paste was assessment of the bare boards showed face. This can be due to excessive time
applied in a smooth, consistent man- evidence of solder mask overlap into in liquidus state. The solder balls seem
ner with uniform height and width. to be well collapsed and formed.
The paste reflowed uniformly and Table 1. XRF Data – Components Wetting balance. The wetting bal-
Component Area Sn (%) Pb (%)
covered leads per IPC-A-610D class 3 ance test showed significant issues with
1 1 68.01 31.99
The ACI Technologies specifications. No apparent skips or the wettability of the HASL board at
1 2 68.51 31.49
Inc. (aciusa.org) is various locations (Figure 2). J-STD-
1 3 6.13 33.87
a scientific research 003 criteria suggest time to buoyancy
2 1 68.25 31.75
corporation dedicated corrected zero, T0 (where the wetting
2 2 67.47 32.53
to the advancement force goes positive), should be less
2 3 68.32 31.68
of electronics manu-
3 1 69.65 30.35
facturing processes
3 2 69.76 30.24 Table 2. XRF Data – PWB Board Surface
and materials for the
3 3 72.11 27.89 Board Area Sn (%) Pb (%) Cu (%)
Department of Defense 4 1 65.82 34.18 1 7.77 15.02 92.75
and industry. This col- 4 2 65.99 34.01 2 39.70 35.46 24.84
Figure 1. Wetting balance curves
umn appears monthly. 4 3 64.27 35.73 3 0.0 0.0 100.0
showing T0 >5 sec.
D
ewetting is a condition that results when molten
solder coats a surface and then recedes, leaving
irregularly shaped mound(s) of solder separated
by areas that are recovered with a thin film of solder and
with the basis metal unexposed.
Non-wetting is a condition in which there is partial Figure 1. Dewetting or non-wetting usually is tied to pad
adherence of molten solder to a surface it has contacted, contamination. Paul Lotosky is global
and the basis metal remains exposed. director - customer
While we usually list in this space the primary process • Flux SP GR too low. technical support at
setup areas to check, dewetting and non-wetting typically • Conveyor speed too fast or slow. Cookson Electronics
are board-related due to pad surface contamination. • Board not seated properly. (cooksonelectronics.
Other things to look for in the process include: • Flux SP GR too high. com) plotosky@cook-
• Solder temperature too low. • Solder contamination. sonelectronics.com.
• Preheat too high or low. Other things to look for with the assembly include:
• Excess or insufficient flux blow-off. • Board or component contamination.
• Solder wave height low. • Improper board handling.
• Flux not making contact. Other things to look for with the board design
• Flux contamination. include:
• Board pallet too hot. • Oxidation.
• Flux applied unevenly. • Contamination. n
A
basic premise in Lean manufacturing principles is the The functional managers responsible for performance to
elimination of non-value added activity by minimiz- measured metrics are also responsible for defining the exter-
ing variation. However, standardizing systems while nal benchmarks relevant to their areas.
accommodating the needs of 30 or more customers can be During the gap analysis of the former Customer Survey
a significant challenge for EMS providers. Customer satisfac- System, opportunities for improvement were identified that
tion measurement is one area where standardization can could tie into the management review cycle (POR) to close
improve efficiency. Yet, the more standardized the format, the our internal loop. One such opportunity was to create a
less meaningful it may be at the customer level. working tool for use by the CFT and customer that would
Like many contract manufacturers, Epic ran a dual cus- define expectations based on the monthly survey. The rede-
tomer satisfaction system. Epic participated in its customers’ signed customer satisfaction measurement tool was named
ratings systems and conducted monthly and annual web- the Customer Expectation Worksheet. A goal for the new
based customer satisfaction surveys. However, only 8% of system was that it link to POR, showing both customer issues
customers were sending formal monthly scorecards defining and the status of corrective actions related to those issues.
their expectations. Of the remaining customers, only 20% Another goal was to link the customer satisfaction survey
were filling out monthly surveys, and the surveys tended to closely with other program management tools. One key tool
generate subjective responses that did not necessarily tie to that was developed was the CFT Tracker.
specific improvement activities or clearly defined goals. The CFT Tracker is a living diary of each customer. It is
In the fourth quarter 2007, the company’s management an Excel workbook resident on the company’s intranet that
team decided to put a new system in place that would: includes tabs for core customer team contact list, product/
• Work seamlessly across multiple facilities. part number lists, NPI planning, meeting agenda, CFT open
• Better align with each customers’ measurement criteria action items, continuous improvement team (CIT) tracker,
(expectations of Epic performance). CFT Paynter chart, customer PPM tracking, scrap analysis,
• Deliver quantitative feedback, even on softer areas of closed CFT action list and the Customer Expectation Work-
evaluation such as quality of team interaction. sheet. In short, the CFT provides the entire account history
• Ensure that both Epic’s customer focus teams (CFT) and and current status information at the fingertips of anyone
operational management had continuous visibility into within the organization.
customer issues and status of corrective actions. Because the CFT Tracker stores trends information
• Integrate with long-term objectives for account growth. related to quality and continuous improvement initiatives,
The new system was fully implemented in 2008, then re- it enables real-time analysis of customer issues identified
evaluated and fine-tuned last March. through the Customer Expectation Survey and makes it easy
System overview. We manage projects using a Customer for the CFT to respond with specific data related to issues
Focus Team model. Each CFT includes a program manager, identified by the customer.
account manager, quality engineer, product engineer, test For example, if our team has made DfM recommenda-
engineer, material analyst and inside salesperson. tions that are currently affecting manufacturing, on-time
Early in our operational strategy formulation, manage- delivery, quality, etc., then this will be tracked in the CFT
Tony Bellitto is quality ment developed a methodology for measuring and sharing Tracker through the Paynter charts. If the customer has
manager-US Opera- performance information, known as the Plant Operational opted not to adopt the recommendations, but indicates in
tions at Epic Technolo- Review (POR) system. The original version monitored its monthly survey that defects exceed predefined limits,
gies (Epictech.com); approximately 60 metrics company-wide down to the floor the CFT can look at the CIT tracker, PPM data and CFT
tony.bellitto@Epictech. level. These metrics were formally reviewed on a daily/weekly Paynter to determine what percentage of defects relate to the
com. basis by project personnel, monthly by plant managers, and unadopted DfM recommendation. With the Paynter chart,
quarterly by senior management. Over time, the system the team can show a weighted analysis of the impact of
has evolved to include the original metrics list, external adopting the proposed changes. Similarly, if the defects relate
benchmarks and longer-term performance trends. The POR to an out-of-control process, we would have the data to drive
process starts with a summary of overall company financial internal improvements. The result: a hyper-focused correc-
performance metrics, then focuses on specific productivity tive action tool. Training was conducted at all Epic facilities.
and operational performance in human resources, quality, In Mexico, training was conducted in Spanish to ensure full
manufacturing, engineering, sales, purchasing and finance. understanding among all CFT members.
Continued on pg. 29
T
he latest addition to the tion and comparison of the relative npl.co.uk), available to all Circuits
database is delamination dimensions, the plating in the hole Assembly readers, allows engineers
on the surface of a board is thin, probably less than 20 µm. to search and view countless defects
assembly. A microsection (Figure There is evidence of delamination/ and solutions, or to submit defects
1) shows a plated through-hole separation of the glass bundles at online. n
with a through-hole lead after sol- the hole-copper interface.
dering using a PbSn process. Prior Close examination of the micro- Dr. Davide Di Maio
to sectioning, the board had shown section and the rest of the board is with the National
evidence of minor delamination will be required for root cause Physical Laboratory
and measling around the pad area analysis. There are a number of Industry and Innova-
on the board subsurface. The board possible causes, and along with the tion division (npl.
was being produced in medium board examination, all the process co.uk); defectsdata-
volume for a consumer product. details would be reviewed, or even base@npl.co.uk.
Mechanical strain or damage the assembly/soldering operation
may occur during pin insertion. audited.
The soldering temperature or These are typical defects shown
the time to solder may have been in the National Physical Labora-
excessive, causing board expansion. tory’s interactive assembly and
The image in Figure 1 is not very soldering defects database. The Figure 1. Lead insertion may cause
clear, but based on the examina- database (http://defectsdatabase. delamination near thinly plated holes.
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Worldwide Headquarters • 109 Corporate Boulevard • South Plainfield, NJ 07080 • USA • +1-800-367-5460 • www.alpha.cooksonelectronics.com
European Headquarters • Forsyth Road • Sheerwater • Woking GU215RZ • United Kingdom • +44-1483-758-400
Asia-Pacific Headquarters • 1/F, Block A • 21 Tung Yuen Street • Yau Tong Bay • Kowloon, Hong Kong • +852-3190-3100
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