INDUSTRIAL AUTOMATION 1 - אוטומציה תעשייתית 1

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PART 1
INDUSTRIAL AUTOMATION
SEQUENCE CONTROL
Sensor Inputs Data Processing Output Signals
X1
LOGIC CIRCUIT Y1
X2 Fixed Automation Y2
Relays
X3 Electronic Gates Y3
Microprocessors
Y4
.....................
X4 Pneumatic Valves
Moving-Part Logic (MPL)
X5
.....................
Semi-Flexible Automation
Programmable Counters
Drum Programmers Ym
Fixed Automation
Xn Programmable Controllers (PLC)
Microprocomputers
TYPICAL OUTPUT DEVICES

Pneumatic or Hydraulic Cylinders
Pneumatic or Hydraulic Motors
Solenoid Valves
Electric Motors
- Pumps
- Conveyor Belts
- Lifting Devices
- Robot Arms
Heaters
Timers
Lamps
Audioble Signals (Bells, Buzzers, Sirens)
Numerical Displays
PART 1

Chapters 1 - 6

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List of Figures PART 1 Updated : July
27, 2003
CHAPTER 0 Introduction
0-1 Formal Infromation
0-2 Silabus Subjects List
0-3 Silabus - General
Fig. 0-1 0-4 Subject Definition
Fig. 0-2 (a-d) 0-4 Information Types
Fig. 0-3 (a-g) 0-4 Binary Switching Elements
Fig. 0-4 (a-b) 0-4 Self Correction
CHAPTER 1 Motion Actuators

Fig. 1-1 1-1 Solenoid
Fig. 1-2 1-1 Force-
Fig. 1-3 1-1 Step Motor
Fig. 1-4 1-1 Pneumatic Cylinder With Air Cushions
Fig. 1-5 (a-g) 1-1 Basic Cylinder Types
Fig. 1-6 1-1 Fifteen Ways of Using Cylinder
Fig. 1-7 1-1
Fig. 1-8 1-2 Eight Types of Pneumatic Rotary Actuators
Fig. 1-9 1-2 Air Motor
CHAPTER 2 Sensors
Fig. 2-1 (a-d) 2-1 Common Actuation Methods for Limit Switches
Fig. 2-2 2-1 Common Contacts Arrangements
Fig. 2-3 2-1 Limit Switch Symbols for Different Contact Configurations
Fig. 2-4 (a-b) 2-1 SPDT switch type BBM and MBB
Fig. 2-5 (a-c) 2-1 Three Operation Methods of Photoelectric Sensores
Fig. 2-6 (a-g) 2-2 Methods for Actuating Reed Switches
Fig. 2-7 2-2 Use of Reed Switch to Sense Piston Position
Fig. 2-8 2-2 Arc Suppression Methods for Protecting Relay Contacts
Fig. 2-9 2-2 Proximity Sensor
Fig. 2-10 2-2 Proximity Sensor Applications
Fig. 2-11 2-2 Use of Magnetic Proximity Sensor
Fig. 2-12 (a-d) 2-3 Four Basic Types of Pressure Switches
Fig. 2-13 2-3 Pressure Switch
Fig. 2-14 2-3 Level Switch
Fig. 2-15 2-3 Two Flow Switches
Fig. 2-16 2-3 Symbols for various Sensor Switches
Fig. 2-17 (a-b) 2-3 Sensor Switch with/without dead band
Fig. 2-18 2-3 Pneumatic Limit Valves And Their Fluid-Power Symbols
Fig. 2-19 2-3 Limit Valve
Fig. 2-20 2-4 Back Pressure Sensor
Fig. 2-21 2-4 Back Pressure Sensor With Overtravel Protection
Fig. 2-22 2-4 Using Back Pressure Sensor
Fig. 2-23 (a-b) 2-4 Annular Back Pressure Sensor
Fig. 2-24 2-4 Interruptable Jet Sensor
Fig. 2-27 2-4 Ultrasonic Sensor and Several Applications
Fig. 2-28 2-4 Spring Sensor
CHAPTER 3 Introduction to Switching Theory
Fig. 3-1 (a-I) 3-1 Boolean Algebra Concept
Fig. 3-2 (a-f) 3-2 Algebric Minimization 1
Fig. 3-3 (a-c) 3-2 Algebric Minimization 2
Fig. 3-4 (a-d) 3-2 Karnaugh Maps Concept
Fig. 3-5 3-3 4-Variables Karnaugh Map Example 1
Fig. 3-12 3-4 4-Variables Karnaugh Map Example 7.1
Fig. 3-14 3-4 4-Variables Karnaugh Map Example 8.1
Fig. 3-18 (a-b) 3-5 Majority Function
Fig. 3-19 (a-d) 3-5 Motor Operation Control
Fig. 3-20 (a-f) 3-5 BCD to 7-Segment
Fig. 3-21 3-6 Various Switches & Relays Types
Fig. 3-22 (a-e) 3-6 Majority Function Circuit
Fig. 3-23 (a-d) 3-6 3-To-8 Decoder Circuit
Fig. 3-24 (a-b) 3-7 3D 5-Variable Karnaugh Map, And Its Development
Fig. 3-25 3-7 Optional Method of Constructing 5-Variable Karnaugh Map
Fig. 3-26 3-7 Simplification of 5-Variable Function
Fig. 3-27 3-7 Exercise
Fig. 3-28 (a-b) 3-7 3D 6-Variable Karnaugh Map, And Its Development
Fig. 3-29 (a-c) 3-7 Simplification of 6-Variable Function
Fig. 3-30 (a-c) 3-8 Creation of 7-Variable Karnaugh Map
Fig. 3-31 (a-b) 3-8 Simplification of 7-Variable Function
Fig. 3-32 (a-b) 3-8 Creation of 8-Variable Karnaugh Map
Fig. 3-33 3-8 Simplification of 8-Variable Function
Fig. 3-34 3-8 Number of Variable Required to Define a Cell
Fig. 3-35 (a-c) 3-9 Saving Contacts and Contact Springs
Fig. 3-36 (a-b) 3-9
Fig. 3-37 3-9 Use of Relay
Fig. 3-38 3-9 Use of Logic Gate
Fig. 3-39 3-9 Logic Gate Symbols
Fig. 3-40 (a-b) 3-9 Minimize by Selecting Non-Prime Cells
Fig. 3-41 3-9 Multiple Output System
Fig. 3-42 (a-b) 3-9 Minimize by Selecting Non-Prime Cell in a Multiple Output System
CHAPTER 4 Industrial Switching Elements
Fig. 4-1 (a-k) 4-1 Typical Simple Gates Packages (SSI Small Scale Integrated)
Fig. 4-2 (a-b) 4-2 Equivalent Circuits For Function AB+CD+EF
Fig. 4-3 (a-b) 4-2
Fig. 4-4 (a-b) 4-2 Equivalent Circuits For Function ABCDEFGH
Fig. 4-5 (a-e) 4-2 Static Hazard Elimination
Fig. 4-6 (a-b) 4-2 Switch Bounce Elimination
Fig. 4-7 4-3 I/O Modules for Electronic Gates
Fig. 4-8 4-3 Optical Coupler
Fig. 4-9 : 4-3 Relay Construction
Fig. 4-10 4-3 Typical Relay Shapes
Fig. 4-11 4-3 Typical Relay Contacts
Fig. 4-12 4-3 Solenoid Valve
Fig. 4-13 (a-m) 4-4 Pneumatic Valve Gates
Fig. 4-14 (a-b) 4-5 Operation of 5/2 Spool Valve
Fig. 4-15 4-5 Shuttle Valve (OR Gate)
Fig. 4-16 4-5 Pneumatic Universal Gate (Samsomatic)
Fig. 4-17 4-5 Pneumatic Universal Gate (Dreldea)
Fig. 4-18 (a-e) 4-6 Pneumatic Gates (Telemechanique)
Fig. 4-19 4-7 Fluid Flip-Flop
Fig. 4-20 4-7 Fluid OR-NOR Gate
Fig. 4-21 4-7 Fluid NOR Gate
Fig. 4-22 4-8 Pneumatic Binary Amplifier (Single Stage)
Fig. 4-23 4-8 Pneumatic Binary Amplifier (Two Stage)
Fig. 4-24 4-9 Flow-Chart Showing Elements used in Binary Control System
Fig. 4-25 4-9 Comparison Between Switching Methods
CHAPTER 5 Electrinc Ladder Diagrams

Fig. 5-1 5-1 Ladder Diagram
Fig. 5-2 (a-c) 5-1 Set-Reset Relay Flip-Flop
Fig. 5-3 (a-b) 5-1 Flip-Flop Implementation Example
Fig. 5-4 (a-b) 5-1 Cylinder Actuation Valves
Fig. 5-5 (a-c) 5-1 Positions of Cylinder Limit-Switches
Fig. 5-6 (a-b) 5-1 Graphic Symbols of Limit-Switches
Fig. 5-7 (a-g) 5-2
Fig. 5-8 5-3 Cascade Method Target & Rules
Fig. 5-9 (a-b) 5-3 Typical Process Definition
Fig. 5-10 5-3 Typical Groups Partitioning
Fig. 5-11 5-3 Typical Initial Cascade Circuit
Fig. 5-12 (a-d) 5-4 Relays Cascade Design Process 1 (No Return Springs)
Fig. 5-13 (a-d) 5-4 Relays Cascade Design Process 1 (With Return Springs)
Fig. 5-14 (a-d) 5-5 Relays Cascade Design Process 2 (No Return Springs)
Fig. 5-15 (a-d) 5-5 Relays Cascade Design Process 2 (With Return Springs)
Fig. 5-16 (a-b) 5-6 Sequential System
Fig. 5-17 (a-b) 5-6 Stability Definition
Fig. 5-18 5-6 Huffman Method Design Steps
Fig. 5-19 5-6 Huffman/PLC Combination
Fig. 5-20 5-6 Merge Flow Lines Rules
Fig. 5-21 (a-k) 5-7 Huffman Process For Sequence A+,A- (With Return Springs)
Fig. 5-22 (a-k) 5-7 Huffman Process For Sequence A+,A- (No Return Springs)
Fig. 5-23 (a-k) 5-8 Process For Sequence A+,A-,A+,A-(With Return Springs)
Fig. 5-24 (a-k) 5-8 Process For Sequence A+,A-,A+,A-(No Return Springs)
Fig. 5-25 (a-d) 5-9 Automatic Mixing System Cascade Method
Fig. 5-26 (a-h) 5-9 Automatic Mixing System Huffman Method
Fig. 5-27 (a-b) 5-10 Full/Partial Input Streams A+,A-,A+.A-
Fig. 5-28 (a-e) 5-10 Full/Pseudo Karnaugh Maps
Fig. 5-29 (a-e) 5-10 Pseudo Map for A+,A-,A+,A-
Fig. 5-30 5-10 Pseudo Map for 2 Cylinders & 4 States
Fig. 5-31 5-10 Pseudo Map for 4 Cylinders & 8 States
Fig. 5-32 (a-h) 5-11 Pseudo Karnaugh Map Example
Fig. 5-33 5-12 GRAFSET for Automatic Mixing System of Fig. 5-36
Fig. 5-34 5-12 GRAFSET for Alternative Parallel Paths
Fig. 5-35 5-12 GRAFSET for Simultaneous Parallel Paths
Fig. 5-36 5-13 GRAFSET for Drilling Station
CHAPTER 6 Swquential Systems with Random

Inputs
Fig. 6-1 (a-m) 6-2 Thickness Detector System Design
Fig. 6-2 (a-l) 6-3 Traffic Light Control System Design
Fig. 6-3 (a-k) 6-1 Alarm System Design
Fig. 6-4 (a-j) 6-4 Motor Direction Detection System Design
Fig. 6-5 (a-i) 6-5 Combination Lock System Design
List of Figures PART 2 Updated : July
20, 2003
CHAPTER 7 Pneumatic Control Circuits

Fig. 7-1 7-1 Intuitive Design Of Sequence A+,B+,A-,B-
Fig. 7-2 7-1 Intuitive Design Of Sequence A+,B+,B-,A-
Fig. 7-3 (a-b) 7-1 Cascade Design Of Sequence A+,B+, B-, A-,C+.C-
Fig. 7-4 7-1 Cascade Design Of Sequence A+,A-,A+,A-
Fig. 7-5 7-1 Multiple Limit-Valves Replacement
Fig. 7-6 7-2 Pneumatic Cascade Basic Concept
Fig. 7-7 (a-c) 7-2 Pneumatic Cascade Group Configurations
Fig. 7-8 (a-g) 7-3,4 Pneumatic Cascade Design Process Steps
Fig. 7-9 7-5 Pneumatic Cascade Example 1
Fig. 7-11 (a-b) 7-6 Flip-Flop Valve & Steering Valve
Fig. 7-12 7-6 Two Steering Valves Providing Three Addresses
Fig. 7-13 7-6 Three Steering Valves Providing Four Addresses
Fig. 7-14 (a-e) 7-6 Design Sequence A+,A-,A+,A-,A+,A-
Fig. 7-15 (a-d) 7-6 Design Sequence A+,B+,A-,B-,(A+/B+),A-,B-
Fig. 7-16 (a-e) 7-7 Design Sequence A+,B+,B-,C+,B+,B-,C-,A-
Fig. 7-17 7-8 Simplified Input Map
Fig. 7-18 (a-d) 7-8 Design a Sequence With Passive States
Fig. 7-19 7-9 Examples of Complex Functions
Fig. 7-20 7-9 Function Tables Background
Fig. 7-21 (a-b) 7-9 Function Tables Arrangement
Fig. 7-22 (a-b) 7-9 3/2 Valve Connections yielding Single Output Function
Fig. 7-23 7-10 Valve Connections With 2 Separate Outputs, 2-Variables Input
Fig. 7-25 7-12 Valve Connections With 2 Separate Outputs, 4/5-Variables Input
Fig. 7-26 7-13 Valve Connections yielding Flip-Flop Output Functions
Fig. 7-27 7-14 Example 1
Fig. 7-28 (a-f) 7-14 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-)
Fig. 7-29 (a-h) 7-15 Solution for Sequence A+,B+,B-,A-,B+,B-
Fig. 7-30 (a-c) 7-16 Stop-Restart With Single Button & Separate Buttons
Fig. 7-31 7-16 Stop-Restart With Multiple Remote-Control Stop Buttons
Fig. 7-32 7-16 Electronic Circuit for Fig. 7-31
Fig. 7-33 7-16 Emergency Stop Modes Definition
Fig. 7-34 (a-d) 7-16 Pneumatic / Electric
Fig. 7-35 7-17
Fig. 7-36 7-17
Fig. 7-37 7-17
Fig. 7-38 7-17
Fig. 7-39 7-17
Fig. 7-40 7-17
CHAPTER 8 Miscellaneous Switching Elements &
Systems
Fig. 8-1 (a-h) 8-1 Sequence Chart for Common Timers Modes
Fig. 8-2 8-1 -
Fig. 8-3 8-1 -
Fig. 8-4 8-1 -Delay Off-
Fig. 8-5 8-1 -
Fig. 8-6 8-1 -
Fig. 8-7 (a-b) 8-1 Sequence Charts for Pulse Shaper
Fig. 8-8 8-1 Relay Pulse Shaper
Fig. 8-9 8-1 Pneumatic Pulse Shaper
Fig. 8-10 (a-c) 8-2 Basic Set-Reset Flip-Flop (SR)
Fig. 8-11 (a-b) 8-2 Toggle Flip-Flop (T)
Fig. 8-12 (a-d) 8-2 T Flip-Flop Implementation - Counters
Fig. 8-13 (a-c) 8-2 D Flip-Flop Implementation Shift Register
Fig. 8-14 8-3 10-Stage Shift Register
Fig. 8-15 8-3 Shift Register With 4 Parallel Tracks
Fig. 8-16 8-3 Schmitt-Trigger Response
Fig. 8-17 8-3 Schmitt-Trigger Response to Fuzzy Waveform
Fig. 8-18 8-3 Truth Table for Error-Checking of BCD code
Fig. 8-19 8-4 Truth Table for 2-Out-of-5 Code
Fig. 8-20 (a-d) 8-4 Use of Karnaugh Map to Obtain Cyclic Code
Fig. 8-21 8-4 Reflected Cyclic Code for Six Numbers
Fig. 8-22 8-4
Fig. 8-23 8-5 Binary 8-Section Encoder
Fig. 8-24 8-5 Typical 8-Section Encoder
Fig. 8-25 8-5 Single-Output Incremental Encoder
Fig. 8-26 8-6 Two-Output Incremental Encoder
Fig. 8-27 (a-j) 8-6 Motor Direction Detection System Design (Copy of Fig. 6-4)
Fig. 8-28 8-6 Simplified Block Diagram of a Closed-Loop NC System
Fig. 8-29 8-6 Block Diagram of Open-Loop NC System
Fig. 8-30 (a-c) 8-7 Adder for 2-Bit Numbers
Fig. 8-31 8-7 Iterative Adder Block Diagram
Fig. 8-32 (a-c) 8-7 Iterative Binary Adder Design
Fig. 8-33 (a-g) 8-8 Iterative Parity Checker
Fig. 8-34 (a-f) 8-8 Iterative 2 Out of n Checker
Fig. 8-35 (a-g) 8-9 Iterative Binary Numbers Comparator
Fig. 8-36 8-10 Comparison Between Natural-Binary & Reflected Cyclic Code
Fig. 8-37 8-10 Iterative Circuit for Translating Natural-to-Reflected Cyclic Code
Fig. 8-38 8-10 Iterative Circuit for Translating Reflected Cyclic to Natural
Fig. 8-39 8-10 Truth Table for Translating Natural-to-Reflected Cyclic Code
CHAPTER 9 Semi-Flexible Automation Hardware
Programmers
Fig. 9-1 9-1 Drum Programmer
Fig. 9-2 9-2 Drum Programmer Solution
Fig. 9-3 (a-b) 9-2 Patch Board & Matrix Board
Fig. 9-4 (a-b) 9-2
Fig. 9-5 9-2 Schematic Representation of Programmable Counter
Fig. 9-6 9-2 Programmable Counter With a Single-Cycle Start Mode
Fig. 9-7 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs
Fig. 9-8 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs
Fig. 9-9 (a-e) 9-3 Programmer Based on 1/n Code
Fig. 9-11 (a-c) 9-4 Programmable Counter Example 1
Fig. 9-13 (a-e) 9-4 2/n Stability Cases
Fig. 9-14 9-5 1/n Code Programmer for Two Simultaneous Parallel Paths
Fig. 9-15 9-5 1/n Code Programmer for Two Alternative Parallel Paths
Fig. 9-16 9-5 1/n Code Programmer With Skipped Steps Option
Fig. 9-17 9-5 1/n Code Programmer With Repeated Steps Option
Fig. 9-18 9-6 Flow Chart for Selecting System Design Method
CHAPTER 10 Flexible Automation Programmable

Controller
Fig. 10-1 10-1 Block Diagram of Programmable Controller (PLC)
Fig. 10-2 10-1 PLC Classifications According to Size
Fig. 10-3 10-1 Discrete Input Devices to PLC
Fig. 10-4 10-1 Discrete Output Devices Actuated by PLC
Fig. 10-5 10-1 Standard Discrete I/O Interface Modules
Fig. 10-6 10-1 Type of Electronic Memories
Fig. 10-7 10-1 I/O Connection Diagram
Fig. 10-8 (a-b) 10-1 PLC- Different I/O Connections Locations
Fig. 10-9 10-2 Typical PLC Memory Map
Fig. 10-10 10-2 PLC Programming Languages
Fig. 10-11 10-2 Ladder Diagram Section Appearing on Screen
Fig. 10-12 10-3 PLC Configuration
Fig. 10-13 10-3 Typical PLC Control System
Fig. 10-14 10-3 PLC Network (Macro)
Fig. 10-15 (a-e) 10-4 PLC I/O Variables Assignment
Fig. 10-16 (a-g) 10-4 PLC Motor Control System
Fig. 10-17 10-5 Forward/Reverse Circuit
Fig. 10-18 10-5 Example of Ladder Diagram Segment
Fig. 10-19 10-5 I/O Assignment for Fig. 10-18
Fig. 10-20 10-5 Ladder Diagram of Fig. 10-18 in PLC Format
Fig. 10-21 10-5 PLC Program for Fig. 10-20
Fig. 10-22 10-5 Use of LIFO Memory Stack
Fig. 10-24 (a-f) 10-6 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-)
Fig. 10-25 (a-b) 10-7 Multiple Use of LIFO Stack
Fig. 10-26 (a-b) 10-7 Rearrangement of Ladder-Diagram to Simplify Program
Fig. 10-27 (a-b) 10-7 Timer Set for 20 Sec
Fig. 10-29 (a-b) 10-7 Counter Set to Count to 25
Fig. 10-31 (a-b) 10-7 PLC Light-Flash Program
Fig. 10-32 (a-c) 10-7 PLC Up/Down Counter Program
Fig. 10-33 10-8 Two-Hand Safety Circuit Using PLC
Fig. 10-34 (a-b) 10-8 PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.D-
Fig. 10-35 (a-c) 10-8 Ladder Diagram and Program for sequence of Fig. 10-34
Fig. 10-36 (a-d) 10-9 Timers and Counters
Fig. 10-37 (a-c) 10-9
Fig. 10-38 (a-c) 10-10 Master-Control-Relay Command (MCR)
Fig. 10-39 (a-c) 10-10 Jump Command (JMP)
Fig. 10-40 (a-d) 10-10
Fig. 10-41 (a-c) 10-10 Equivalent PLC and Relay Circuits
Fig. 10-42 10-11 Effect of Scanning Action on Internal States of Relays
Fig. 10-43 (a-b) 10-11 Importance of Proper Rung Order
Fig. 10-44 10-11 Trigger Flip-Flop Circuit for PLC
Fig. 10-45 10-11 PLC Sequence Chart for Fig. 10-44
Fig. 10-46 10-11 Analog Input Devices for PLC
Fig. 10-47 10-11 Standard Analog-Input Interface Modules
Fig. 10-48 10-11 Analog Output Devices Actuated by PLC
Fig. 10-49 10-12 Standard Analog-Output Interface Modules
Fig. 10-50 10-12 Storing an Analog Input Value
Fig. 10-51 10-12 Instruction Block
Fig. 10-52 10-12 Transferring a Word to Analog Output Module
Fig. 10-53 10-12
Fig. 10-54 10-12
Fig. 10-55 10-13
Fig. 10-56 10-13
Fig. 10-57 10-13 Logic Operations
Fig. 10-58 10-13 Data Commands
Fig. 10-59 10-13 PLC Micro/Macro Definition
Fig. 10-60 10-13 Several Possible LAN Topologies
Fig. 10-61 (a-f) 10-14 PLC Design of Thickness Detector System
Fig. 10-62 (a-e) 10-14 PLC Design of Traffic Light Control System
Fig. 10-63 (a-l) 10-15 PLC Design of Alarm System
Fig. 10-64 (a-e) 10-16 PLC Design of Motor Direction Detector System
Fig. 10-65 (a-i) 10-17 Combination Lock System
CHAPTER 11 Introduction to Assembly
Automation
Fig. 11-1 11-1 Bladed Wheel Hopper Feeder
Fig. 11-2 11-1 Central Board Hopper Feeder
Fig. 11-3 (a-c) 11-1 Shape of Centerboard Slot
Fig. 11-4 11-1 Rotary Centerboard Hopper Feeder
Fig. 11-5 11-1 Design Sheet for Reciprocating Tube Hooper Feeder
Fig. 11-6 11-1 Revolving Hook Hopper Feeder
Fig. 11-7 11-2 Design Sheet for Tumbling
Fig. 11-8 11-2 Magnetic-Disk Hopper Feeder
Fig. 11-9 11-2 Vibratory Bowl Feeder
Fig. 11-10 11-2 Design Sheet for Vibratory Bowl Feeder
Fig. 11-11 11-2 Disk Feeder
Fig. 11-12 11-2 Slide Escapement
CHAPTER 12 Robotics and Numerical Control

Fig. 12-1 (a-b) 12-1 Cartesian Robot and Coordinate System
Fig. 12-2 12-1 Cylinde Robot and Coordinate System
Fig. 12-3 12-1 Spherical Robot and Coordinate System
Fig. 12-4 12-1 Articulated Robot and Coordinate System
Fig. 12-5 12-1 Robot Work Envelope
Fig. 12-6 12-1 RCC Device
CHAPTER 13 Simester Exams

13-1 Simester Exam Example - Questions
13-3 Simester Exam Example Responses
13-7 Typical Simester Exam Questions - Questions
0-4
INDUSTRIAL AUTOMATION
Automation of Mechanical Industrial Production Systems START S?
S?
Control Section
On-Off (Binary) Elements and Information SW SPDT
Various Methodes to Obtain Low-Cost Systems SW DPDT
a. Electrical Switches
Fig. 0-1 Subject Definition K?
K?
Value Value RELAY SPST

RELAY DPDT
b. Electro-Mechanical Relays
2-Input AND 3-Input AND 2-Input NAND

1 1
3 3
2 2
Time Time
a. Analog 2-Input OR 2-Input NOR Inverter

1 2
3 1
2 3
Value Value
c. Electronic Gates
+ - +
Time Time
b. Digital + - + - +
Value Value
d. Pneumatic Valves
a1,a2 = 00
a1 a2
+
-
Time Time
(open) (open)
c. Binary (Logic, "Digital") A+ A-
Value
Signal
"High"
LOGIC e. Electrical Limit Switches
"Unspecified" IMPLEMENTATION
"Low"
Time
(d)
+
d. Logic Levels A+ A-
Fig. 0-2 Information Types
f. Pneumatic Limit Valves
Logic BINARY SENSORS :

In Element Out Pressure , Flow , Temperature , Height etc
(a)
g. Various Elements
(b) Relay SPDT
Fig. 0-4 Self Correction Fig. 0-3 Binary (Switching) Elements

CHAPTER 1
MOTION ACTUATORS
Linear and Angular Motion

Electrical Linear Actuators
Electrical Rotary Actuators
Fluid-power Linear Actuators
Fluid-power Rotating Actuators
Boolean Functions Standard Formats
CHAPTER 2
SENSORS
Electric Position Sensors

Contacts Symbols
Photoelectric Sensors
Reed Switches
Proximity Sensors
Pressure, Flow and Level Switches
Pneumatic Limit Valves
Back-Pressure Sensors
CHAPTER 3
INTRODUCTION TO
SWITCHING THEORY
Boolean Algebra
Truth Tables
Functions Algebric Minimization
DeMorgan Theorem
Universal Systems
Boolean Functions Standard Formats
Karnaugh Maps
Maximal Cells
Essentoal (Maximal) Cells
Adjucent Cells
Minimzation By Karnaugh Maps
4-Variables Minimization Examples
5 8 Variables Implementation
BOOLEAN ALGEBRA 3-1
NAND (NOT AND) : X nand Y = (X.Y)'
Logic Theory Implementation in Switching
NOR (NOT OR) : X nor Y = (X+Y)'
George Boole
XOR (Exlussive OR) X xor Y = X'Y+XY'
False and True replaced by 0 and 1
INHIBITION X.Y'
Binary Items and Variables
IMPLICATION X+Y'
Logic , Boolean , Binary , Digital
Switch or Relay ON/OFF Position :
f. More Useful Operators
Contacts : Open / Closed
Net : Connected / Not-connected
Binary sensors (Temperature, Pressure, etc)
(A.B)' = A'+B'
Representations :
(A+B)' = A'.B'
"0 / "1"
Implementations :
"ON" / "OFF"
(A.B+A'.C)' = (A'+B').(A+C')
"HIGH" / "LOW"
(AB(C'+DE'))' = A'+B'+C(D'+E)
a. Basic Definitions
g. DeMorgan Theorem
AND OR NOT
AND , OR , NOT
0.0 = 0 0+0 = 0 0' = 1
0.1 = 0 0+1 = 1 1' = 0
AND , NOT A+B = (A'.B')'
1.0 = 0 1+0 = 1
1.1 = 1 1+1 = 1 {*}
OR , NOT A.B = (A'+B')'
b. Basic Operators NAND A' = (A.A)' = (A NAND A)
A+B = (A'.B')' = ((A.A)'.(B.B)')' =
= (A NAND A) NAND (B NAND B)
X.0 = 0 X+0 = X
X.1 = X X+1 = 1
NOR A' = (A+A)' = (A NOR A)
X.X = X X+X = X
X.X' = 0 X+X' = 1 A.B = (A'+B')' = ((A+A)'+(B+B)')' =
X+X.Y = X = (A NOR A) NOR (B NOR B)
X+X'.Y = X+Y
X(Y+Z) = XY+XZ
(X+Y).(X+Z) = X+YZ h. Universal Systems
XY+X'Z+YZ = XY+X'Z
c. Basic Relations
A B C D F
0 0 0 0 0
XY+X'Z+YZ = XY+X'Z
0 0 0 1 0
F1 = XY+X'Z+YZ F2 = XY+X'Z 0 0 1 0 1
1. Universal Sum-of-Products :
0 0 1 1 1
X Y Z F1 F2 0 1 0 0 1 2. Universal Products of Sum :
0 1 0 1 1
0 0 0 0 0 0 1 1 0 0
3. Minimal Sum-of-Products :
0 0 1 1 1 0 1 1 1 1
0 1 0 0 0 4. Minimal Products of Sum :
0 1 1 1 1 1 0 0 0 0
1 0 0 0 0 1 0 0 1 0
1 0 1 0 0 1 0 1 0 1
1 1 0 1 1 1 0 1 1 1
1 1 1 1 1 1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
d. Minimization - Truth Table
1. Universal Sum-of-Products :
f(A,B,C,D) = A'B'CD'+A'B'CD+A'BC'D'+A'BC'D+A'BCD+
+ AB'CD'+AB'CD+ABCD'+ABCD
2. Universal Products of Sum :

XY+X'Z+YZ = XY+X'Z
f'(A,B,C,D) = A'B'C'D' + A'B'C'D + A'BCD' + AB'C'D' +
F1 = XY+X'Z+YZ F2 = XY+X'Z
+ AB'C'D + ABC'D' + ABC'D
If Z=0 then : f(A,B,C,D) = (A+B+C+D)(A+B+C+D')(A+B'+C'+D)(A'+B+C+D).
.(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D')
F1 = XY+X'.0+Y.0 = XY F2 = XY+X'.0 = XY
3. Minimal Sum-of-Products :
If Z=1 then :
f(A,B,C,D) = A'BC'+AC+B'C+CD
F1 = XY+X'1+Y.1 = F2 = XY+X'.1 =
= XY+X'+Y = X'+Y = X'+XY = X'+Y 4. Minimal Products of Sum :
f(A,B,C,D) = (A'+C)(B+C)(A+B'+C'+D)
e. Minimization - Math Operations i. Functions Basic Representations
Fig. 3-1 : Boolean Algebra Concepts

3-2
Karnaugh Maps
INSURANCE COMPANY REQUIREMENTS
* Visual method for boolean functions
AN INSURANCE COMPANY SELECTS CLIENTS ACCORDING TO THE FOLLOWING minimization
CRITERIA : NATIONALITY, GENDER, AGE AND HAVING DRIVING-LICENSE. * Each variable occupies half map
* n variables split map into 2 n basic cells, named
CLIENT MUST SATISFY AT LEAST ONE OF THE FOLLOWING CONDITIONS :
and/or ISRAELI
and/or NON-ISRAELI UNDER 50 WITH DRIVING LICENSE
map Elements
and/or NON-ISRAELI MAIL 50 OR ABOVE
NON-ISRAELI UNDER 50 WITHOUT DRIVING LICENSE * Each element is represented by a n-variable
FIND THE MINIMAL REQUIRED CONDITIONS boolean product, named "Minterm"
a. System Definition * Any two adjacent elements are represented
by two "Adjacent" minterms
CRETERIA VARIABLE 1 0
NATIONALITY A ISRAELI NON-ISRAELI * Merging two adjacent elements produces

GENDER B MALE FEMAIL
AGE C 50 OR ABOVE UNDER 50
a 2-elements cell, represented by a product of
LICENSE D HAS LICENSE DOESN'T HAVE LICENSE (n-1) variables
b. Boolean Variables Assignment * Two adjacent 2-element cells may be merged
Into a 4-elements cell, represented by a
T = A+A'C'D+A'BC+A'C'D' = A+A'(C'D+BC+C'D') product of n-2 variables, and so on
= A+C'D+BC+C'D'= A+C'(D'+D)+BC= A+C'+CB= A+B+C'
a. Map Concepts and Basic Properties
c. Direct Minimzation
B B' B
A B C D T
T= A+A'B'C'D'+A'B'C'D+A'BC'D'+A'BC'D+A'BCD'+A'BCD 0 0 0 0 1
A'
0 0 0 1 1
= A+A'(B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD)' = 0 0 1 0 0
= A+B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD' = 0 0 1 1 0 A A
0 1 0 0 1
= A+B'C'(D'+D)+BC'(D'+D)+BC(D'+D)' 0 1 0 1 1
= A+B'C'+B.C'+BC = A + B'C' + B(C'+C) = 0 1 1 0 1
0 1 1 1 1
= A + B'C' + B B
1 0 0 0 1
= A + C' + B 1 0 0 1 1 0 1 B
A
1 0 1 0 1
e. Truth Table Minimzation 1 0 1 1 1 0
1 1 0 0 1
1 1 0 1 1
SIMPLIFIED RESULT : 1 1 1 0 1 1 A
1 1 1 1 1
and/or ISRAELI
and/or UNDER 50
MALE d. Truth Table
f. Minimal Requirements b. 2-Variables Map Representations
Fig. 3-2 : Algebric Minimization (1)

BC
AN OCTAL NUMBER IS DEFINED BY THE BINARY COMBINATION X2,X1,X0
A 00 01 11 10 B
WHERE N(X2,X1,X0)=4.X2+2.X1+1.X0 A'B'C' A'B'C A'BC A'BC'
0
A COMBINATIONAL SYSTEM DETECETS IF THE NUMBER IS DIVIDABLE
BY EITHER 2 OR 3 1 AB'C' AB'C ABC ABC' A
a. System Definition C
X2 X1 X0 T c. 3-Variables Map Representations
0 0 0 1
X1 CD
0 0 1 0 C
COMBINATIONAL 00 01 11 10
X1 CIRCUIT T
X1 AB
0 1 0 1
00
b. Block Diagram
0 1 1 1 01
T = X2'X1'X0'+X2'X1.X0'+X2'X1.X0 + B
1 0 0 1 + X2.X1'X0'+X2.X1.X0'= 11
=X0'(X2'X1'+X2'X1+X2X1'+X2X1)+X2'X1X0= A
1 0 1 0 =X0'(X2'(X1'+X1)+X2(X1'+X1))+X2'X1X0= 10
=X0'(X2'+X2)+X2'X1X0=
D
1 1 0 1 =X0'+X2'X1X0=
=X0'+X2'X1 d. 4-Variables Map Representations
1 1 1 0
c. Truth-Table d. Minimization Steps

Fig. 3-4 : Karnaugh Maps Concept
Fig. 3-3 : Algebric Minimization (2)
C C C C
Fig. 3-5 : Example 1 Fig. 3-6 : Example 2 Maps Definitions
1 1 1 1 1 1
Essential cells : 3 Essential cells : 4 I Function "Area"
1 1 1 1 1 1 1 1 1 1 Non-Essential cells : 1 II All (Maximal) Cells
B
Non-Essential cells : 0 B B
B
Minimal solutions : 1 1 1 1 1 1 1 Minimal solutions : 1 III Minimal Solution 1
1 1 1 1 A A
A A IV Minimal Solution 2
F = AD + C'D + A'CD' 1 1 F = A'C'D + ACD + A'BC + ABC'
1 1 1 1 V Minimal Solution 4
D D D D
I II I II
C 2 C C C Fig. 3-7: Example 3

1 1 1 1 Essential cells : 2
Non-Essential cells : 2
1 1 1 1 1 1 1 1 1 1 1 1 Minimal solutions : 2
B B B B
1 1 1 1 1 1 1 1 F1 = BC + B'C'D + A'BD
A A A A
1 1 1 1 F2 = BC + B'C'D + A'C'D
D I D D D IV
II III
C C C Fig. 3-8 : Example 4

1 1 1 1 1 1
Essential cells : 3
1 1 1 1 1 1 1 1 1
B B Non-Essential cells : 2
B
1 1 1 1 1 1 Minimal solutions : 1
A A A
1 1 1 1 1 1 F = AC + B'C + A'BC' + CD
D I D D III
II
C C C C C C
Fig. 3-9 : Example 5
Essential cells : 2
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 Minimal solutions : 4
B B B B B B
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F1 = A'C' + AC + ABD + AB'D'
A A A A A A
F2 = A'C' + AC + ABD + B'C'D'
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
F3 = A'C' + AC + BC'D + AB'D'
D D D D IV D D VI
I II III V F4 = A'C' + AC + BC'D + B'C'D'
C C C C
Essential cells : 0
1 1 1 1 1 1 1 1 1 1 1 1 Non-Essential cells : 6
3-3
B B B B Minimal solutions : 2
1 1 1 1 1 1 1 1 1 1 1 1
A A A A F1 = ABC + BC'D + A'BD'
F2 = BCD' + ABD + A'BC'
D I D D III D IV
II
C C C C C C Fig. 3-11 : Example 7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Essential cells : 0 Maps Definitions
Non-Essential cells : 12 I Function "Area"
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B B B B B B Minimal solutions : 6 II All (Maximal) Cells
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 III Minimal Solution 1
A A A A A A F1 = A'C' + B'D'+ AB + CD
IV Minimal Solution 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F2 = BD+ AC + A'B'+ C'D'
V Minimal Solution 4
D D D D D D F3 = AD'+ BC'+ CD + A'B'
I II III IV V VI
F4 = A'D + B'C + AB+ C'D'
F5 =
C C C
Fig. 3-12 : Example 7.1 F6 =
Essential cells : 2
0 0 0 Non-Essential cells : 0
B B B Minimal solutions : 1
A A A F' = A'BCD' + AB'C'D
0 0 0
F = (A + B' + C' + D).(A' + B + C + D')
D I D D
II III
C C
C C C Fig. 3-13 : Example 8 C Fig. 3-14 : Example 8.1
- - -
1 1 - 1 1 1 - 1 1 1 - 1 Essential cells : 2 Essential cells : 0
Non-Essential cells : 1 (+2) 0 0 0 0 0 0 Non-Essential cells : 8
1 1 1 0 0 0 B B
Selected Don't Cares : None
B B B Selected Don't Cares : All
- B
0 - 0 -
1 1 - 1 1 - 1 1 - Minimal solutions : 1 0 A A
-
Minimal solutions : 1
A A - A
-
A
- 0 0 - 0 0 F' = AB'D + A'BD' + BC'D
1 - 1 1 F = AD' + A'B' + BCD 0 0 D
D D III
D D D I II F = (A'+B+D').(A+B'+D).(B'+C+D')
I II III
C C C
Fig. 3-15: Example 9
- - 1 -
1 1 1 1 1 Essential cells : 0
1 - 1 1 - 1 1 - 1 Non-Essential cells : 3 (+5)
B B - - B Selected Don't Cares : None
1 1 - - 1 1 - - 1 1 Minimal solutions : 1
A A A -
1 1 - 1 1 - 1 1 F = AC' + C'D + A'CD'
D D II D III
I
C C C Fig. 3-16 : Example 10

1 - 1 1 - 1 -
1 1 Essential cells : 2
1 - 1 1 - 1 - Non-Essential cells : 1
B B
1 1
Selected Don't Cares : Partial
1 - - 1 - - - - B
A A
1 Minimal solutions : 1
1 - - 1 - -
A - -
1 F = AD + A'D'
D D D
I II III
C C - C C
1 - - 1 - - 1 - - 1 - - Essential cells : 1
1 - - 1 - - 1 - - 1 - - Selected Don't Cares : Partial
B B B B
- 1 1 1 - 1 1 1 - 1 1 1 - 1 1 1 Minimal solutions : 2
3-4
A A A A F1 = ACD + AB + A'C'
1 1 1 1 F2 = ACD + AB + A'D'
D D D D
I II III IV Note : F1 and F2 are equivalent but not identical
X Y Z M 3-5
0 0 0 0 BCD to 7-SEGMENTS CONVERTER
Design a combinational circuit that gets a BCD input, and converts it to
0 0 1 0 7-Segment display.
BCD is short form of Binary-Coded-Decimal. It Represents 10 decimal
0 1 0 0
digits (0-9) in 4-bit binary code (0000-1001).
Binary combinations 1010-1111 (above decimal 9) may not appear as
inputs, and are refered as don't-care.
0 1 1 1
Y,Z a. System Definition
X 00 01 11 10
1 0 0 0
0 0 0 1 0
1 0 1 1
1 0 1 1 1
1 1 0 1
b. 7-Sigments Arrangement
M = XY+XZ+YZ
1 1 1 1
b. Karnaugh-Map A
G
a. Truth-Table D3 B
D2 C B E
D A
Fig. 3-18 : Majority Function D1 E C F
D0 F
G D
c. Block Diagram
Y,Z
X 00 01 11 10
X Y Z A B C
0 1 1 1 D3 D2 D1 D0 A B C D E F G
0 0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 1 0 1
1 1 1 1 1 0 0 1 0 1 1
0 0 1 1 0 0 0 0 1 1 1 1
A=X+Y+Z 0 1 0 0 1 1
0 1 0 1 1 0
0 1 0 1 0 0 0 1 1 0 0
Y,Z 1
X 00 01 11 10
0 1 1 1 0 0
1 0 0 0 1 1
0 1 1 1 1 0 1 0 0 1 1 1
0 0 0 1 0 1 0 1 0 - -
1 0 0 1 0 0
1 0 1 1 - -
1
1 1 0 0 - -
0 1 1 1 1 1 0 1 - -
1 1 1 0 - -
1 0 1 1 1 0 1 1 1 1 - -
B = XY + XZ + YZ
1 1 0 1 1 0 Y,Z d. Truth-Table (Partial)

X 00 01 11 10
1 1 1 1 1 1 0 0 0 0 D3,D2
0
00 01 11 10
D1,D0
1 0 0 1 0
00 1 1 - 1
a. Truth-Table
C = XYZ 1 0 - 1
01
b. Karnaugh-Maps
11 1 0 - -
X
Y 10 1 0 - -
A
Z
F=D2'+D1'D0'
X Y e. Karnaugh Map of "F"
X
Z
Y B
X Y Z
* D3,D2
D1,D0
00 01 11 10 D1,D0
D3,D2
00 01 11 10
C
0 1 - 1 00 0 1 - 1
00
c. Contact Circit Realization 01 0

*
1 -
* 1
01
0 1 - 1
X
11
Y 11 1 0 - - 1 0 - -
Z
A
10
* 1 1 - -
10 1 1 - -
X Y
X B
Z
Y A=D3+D2.D1'+D2'D1+D1.D0'=
X Y Z =D3+D2.D1'+D2'D1+D2.D0'
C
f. Karnaugh Map of "A"
SWITCH-X SWITCH-Y SWITCH-Z
d. Electrical Diagram
Fig. 3-20 : BCD to 7-Segments

Fig. 3-19 : Motor Operation Control
(Exer1-7)
3-6
SW PUSHBUTTON
SW DPST
RELAY SPST LAMP
SW SPST
RELAY 4PST
SW SPDT SW DPDT M1
RELAY SPDT
M2
A
RELAY DPST
M3
RELAY DPDT
RELAY 4PDT
B
M4
Fig. 3-21 : Various Switches and Relays Types C
M5
T = AB + AC + BC = AB + (A + B)C M6
b. Majority Boolean Function
M7
A B COMMON
C a. Block-Diagram
+ -
b. Switches-Operated Circuit
A'B'C'
A'B'C
A B A'BC'
A'BC
A AB'C'
C AB'C
B ABC'
ABC
c. Contacts Circuit A B C
b. Switches-Operated Circuit
C' A'B'C'
-
B B'
+
A' C A'B'C
C' A'BC'
M B
C A'BC
C
C' AB'C'
B'
A C AB'C
d. Switches Remote Operation
9 Long Lines, Carrying High Current C' ABC'
B
C ABC
c. Contacts Circuit
- +
A
M
A B C
B A'B'C'
B C
A'B'C
A A'BC'
C A'BC
AB'C'
A
AB'C
B ABC'
- +
ABC
C
e. Relays Remote Operation COMMON

3 Long Lines, Carrying Low Current d. Relays-Operated Circuit
Fig. 3-22 : "MAJORITY" Function Circuit Fig 3-23 : 3-TO-8 DECODER CIRCUIT
E' E C
C C 3-7
B B B
A
A A
D D
D D E
a. 3-D Representation b. Flat Representation
Fig. 3-25 : Optional Construction
Fig. 3-24 : Three-Dimentional Five-Variable of Five-Variable Karnaugh Map
Karnaugh Map, and Its Developmenet (Not Recommended)
E' E T=A'B'C'D'+A'BDE'+A'B'CDE'+AB'C'D'+A'BC'DE+ABCDE+ABCD'E
C C
1 0 1 - 1 0 0 - with impossible conditions : A'B'CD''=1 ACDE'=1
0 1 1 0 0 *1 0 0 a. Original Function
B B
A
0 0 - 0
A
0 0 1 *1
T=B'C'D'+A'BC'D+CDE'+ABCE
*1 0 - 0 1 0 0 0
D D c. Simplified Function
b. Karnaugh Map
Fig. 3-26 : 5-Variable Minimzation Exercise (With Solution)
*
E' E
C C T=A'B'C'E'+A'B'CD'+ABC'DE'+AB'C'E'+AB'CD'E'+B'C'D'E+A'B'C'DE+CD'E
a. Original Function
B B
A A T=
D D c. Simplified Function
b. Karnaugh Map Fig. 3-27 : 5-Variable Minimzation Exercise, (Without Solution)
F
b. Flat Representation
a. 3-D Representation Fig. 3-28 : Three-Dimentional sIx-Variable

Karnaugh Map, and Its Developmenet
1
E T=A'BC'F'+AB'C'DE'F+ABDF+ACDE+ACD'E+
+A'C'DE'+A'C'DEF'
- 1 0 0 - 1 0 0 - 0 0 0 - 1 0 0 with impossible conditions :
1* 1 0 0 0 1 0 - 0 0 0 - 1 1 0 0 A'B'C'D'=1 A'BCD'F=1
0 0 0 0 0 1 1* 0 0 1 1 1 0 0 1 *1 a. Original Function
0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1
4 T=A'C'F'+ACE+C'DE'F+ABDF
3
F 2
1 2 3 4
b. Karnaugh Map
c. Simplified Function
Fig. 3-29 : 6-Variable Minimzation Exercise (With Solution)

3-8
B
G
A
F
D
G
a. Upper Level b. Lower Level
F
Fig. 3-30 : Seven-Variable Karnaugh c. Flat Representation
Map, and Its Developmenet AB'C'D'EF'G'
1 E
1 1 1 1 - -
*1 1 1 1 - -
* 1* 1 1 1
T=A'C'D'G'+ABCF'+B'D'FG+A'C'EF'
1 2 3 4
b. Simplified Function
1 1 1 1 1 *1 4
G
1 1
1 1 1 1
1 *1 1 1
F 2
Fig. 3-31 : 7-Variable Minimzation
Exercise (With Solution) a. Function Karnaugh Map 3
E C G
- 1 1 1 1 - - 1 1
F B - 1 1 1 -
G A 1 - - - - 1 - - -
H D - 1 1 - 1 1 - 1 1
a. Upper Level a. Lower Level
1 - 1
Fig. 3-32 : Eight-Variable Karnaugh - 1
Map, and Its Developmenet
- - 1 - -
1 1 -
F
Number of Variables
in The Function - - - - - - - - - - - - - - - -
Size of Cell 2 3 4 5 6 7 8
- - - - - - - - - - - - - - - -
Single Square 2 3 4 5 6 7 8 - - - - - - - - - - - - - - - -
2-Square Cell 1 2 3 4 5 6 7
- - - - - - - - - - - - - - - -
E
4-Square Cell 1 2 3 4 5 6 1 1 1
8-Square Cell 1 2 3 4 5 1 1
16-Square Cell 1 2 3 4 - - - -
32-Square Cell 1 2 3 1
64-Square Cell 1 2 H
128-Square Cell 1
Fig. 3-33 : 8-Variable Minimzation Exercise
Fig. 3-34 : Number of Variables Required
to Define Certain Cell Address
X2
3-9
Y1 Y1
X1 (X1')
X2
1 2
X1
Y2 1 2 Y1
X2
(X1) CR1
X2 (X2') Y2
X1 CR1 CR1 (X2)
Y1 1 2
X1
X1 Y2
Y2 X2
1 2
CR1=Y1.X2+Y2.X2'+Y1.X1'+Y2.X1 CR1=Y1(X1'+X2)+Y2(X1+X2') CR1=Y1(X1'+X2)+Y2(X1+X2')

8 Contacts , 16 Springs 6 Contacts , 12 Springs 4 Contacts , 10 Springs
a. Original Function b. Saving Contacts c. Saving Contact Springs
Fig. 3-35 : Saving Contacts and Contacts Springs

Exitation Output
Function Variables (y,y')
(Y) y
y
y
Y2
Y RELAY
Y3 Y2 y'
y'
T Y3 y'
Y1
T
Y1
Y1 Y2 Y3
Y2 Y3 Fig. 3-37 : Use of Relay
Input Output
Variables (x') Function (T)
T=Y2.Y3+Y1.Y3+Y1.Y2.Y3' T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'+(Y2.Y3') x1
T
x2
a. Original Function b. Sneak Path Y2.Y3' x3 GATE
x4
Fig. 3-36 : Sneak Path Creation

Fig. 3-38 : Use of Gate
NOT AND OR EXCLUSIVE NOR NAND IMHIBITION FLIP-FLOP

OR
y
Old S
European
y'
Symbols R
y
Old USA S
Symbols FF
R y'
New Symbols S y
Recommended
by ISO 1 & >1 =1 >1 & & R y'
Fig. 3-39 : Logic Gate Symbols
C C C C
0 - - 1 0 - -1 0 0 0 0 1 1 1 1
- - 0 - - - 0 - 0 - 1 0 0 0 1 0
B B B B
- 1 - - - 1 - - 1 1 1 0 0 0 1 0
A A A A
0 0 0 - 0 0 0 - 1 1 0 0 0 0 0 0
D D Input Output D D
Variables Variables
T=BC'+A'C'D= T=B'C'D+A'C'D= A T1 T1=AC'+BCD T2=A'B+BCD
B
=C'(B+A'D) =(B+A')C'D C RELAY T2 (Instead of A'C+BD)
D
a. 5 Gates b. 4 Gates T3
E a. Function T1 b. Function T2
Fig. 3-40 : Minimize by Selecting Fig. 3-41 : Multiple

Non-Prime Cells Output System Fig. 3-42 : Minimize by Selecting
Non-Prime Cells, in
Multiple-Ourtut System
CHAPTER 4
INDUSTRIAL SWITCHING
ELEMENTS
Electronic Gates
Electronic Gates Implementation
Input/Output Module
Electric Relays
Moving Parts Logic (MPL)

7
SN54LS00
4-1
VCC SN74LS00
14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
GND
a. Quad 2-Input NAND Gate g. Chip Configuration
SN54LS32
SN74LS32
VCC
14 13 12 11 10 9 8
SN54LS00
1 2 3 4 6
SN 54 LS 00
5
GND
b. Quad 2-Input OR Gate Function

Vendor
(Serial Number)
SN54LS27 Family Technology

VCC SN74LS27
14 8
13 12 11 10 9
h. Chip Name "Code"
1 2 3 4 5 6 7
GND
74 : Commercial Family
c. Tripple 3-Input NAND Gate 54 : Military Family
Difference : Temperature Range
SN54LS20 Many More Families

VCC SN74LS20
14 13 12 11 10 9 8 i. Families
1 2 3 4 5 6 7
High / Low Speed
GND
High / Low Power Dissipation
d. Dual 4-Input NAND Gate
High / Low Power Drive (Fan-Out)
High / Low Power Supply Voltage
SN54LS04 And Many More
SN74LS04
VCC
14 13 12 11 10 9 8
j. Technologies Characteristics
1 2 3 4 5 6 7
GND
e. Hex INVERTER
SN54LS76
SN74LS76
GND
16 15 14 13 12 11 10 9
k. Grid-Array Package
7
9 11 4 15
(not SSI)
PR
PR
J Q J Q
6 1
CLK CLK
12 10 16 14
CL
CL
K Q K Q
8
1 2 3 4 5 6 7 8
VCC
f. Dual J-K FLIP-FLOP
Fig. 4-1 : Typical Simple Gates Packages (SSI - Small Scale Integrated)
4-2
A AB A (AB)'
B B
((AB}'.(CD)'.(EF)')' =
C CD AB+CD+EF C (CD)'
D D
= AB+CD+EF
E EF E (EF)'
F F
a. AND-OR-NOT system b. NAND system
Fig. 4-2 : Equivalent Circuits for Function AB+CD+EF
B AB B
A A (AB)'
AB+A'C A' AB+A'C
A'
A'C (A'C)'
C C
a. AND-OR-NOT system b. NAND system

4 Gates , 3 Packages 4 Gates , 1 Package
Fig.4- 3 : Equivalent Circuits for Function AB+A'C (Save Packages)
A,B
C 00 01 11 10
1
A 3
0
2 4 0 0 1 0
B 6
5 9
C 8
10 12
D 11 1 0 1 1 1
E 13 1
3
(a)
2 4
F 6
5 9
G B AB
H
10
8
T A 1
AB+A'C
a. 7 Gates , 2 Packages , 7xT delay A' A'C

C 2 (b)
1
A 3
2
B 1 A
3
2
4
C 6
5
D 9
8
10 T A'C
9
E 8
10
F 4
6
5
G 12 AB
11
13
H
b. 7 Gates , 2 Packages , 3xT delay AB+A'C
(c)
Fig. 4-4 : Equivalent Circuits for Function ABCDEFGH
Transition From 011 to 111
(Gate 1 Slower Than Gate 2)
(Increase Speed)
A,B
PRESS BOUNCE RELEASE BOUNCE
ANTI-BOUNCE CIRCUIT C 00 01 11 10
A A
1
3 0 0 0 1 0
B 2
1 0 1 1 1
(d)
1
3
OUT 2 OUT A AB
B
B AB+A'C+BC
a. Contact Bounce (A,B) and
A' CD
Required Signal (OUT) b. Eliminate Bounce by a Simple Flip-Flop C
(e)
B EF
C
Fig. 4-6 : Switch Bounce Elimination

Fig. 4-5 : Hazard Elimination
4-4
A A B B
+
T=A T=A' A T=A.B T=A+B
A
a. YES Gate b. NOT Gate c. AND Gate d. OR Gate
B B
A
+
+
T=A.B' A T=A+B'
C T=A.C+A'B
A
B
e. INHIBITION Gate f. IMPLICATION Gate g. SELECTOR Gate
B
A B
+
+
T=A.B'
T=A' T=A+B A
A T=A+B'
T=A T=A.B
-
-
h. YES/NOT Gate i. AND/OR Gate j. INHIBITION/IMPLICATION Gate
A Hot Hot
(T=A+B)
Cold Cold
k. Non-Valve "OR" Element l. Almost equal HOT/COLD m. COLD Pressure Less Than HOT -
pressure - No Flow HOT Flows Into COLD
Fig. 4-13: Pneumatic Valve Gates

D E
4-5
P1 P2
A B C
a. Position 1
X1
D E
T=X1+X2
P2 X2
P1
Fig. 4-15 : Shuttle Valve

(OR Gate)
A B C
b. Position 2
Fig. 4-14 : Operation of 5/2 Spool Valve
X2 X4
T=X5(X1'+X2)+X4.X1.X2'
X1 X5
Fig. 4-16 : Pneumatic Universal Gate (MPL)

(Samsomatic, W. Germany)
X1 X3 X4 X2
T
T=X3(X1'+X2)+X4(X1+X2')
Fig. 4-17 : Pneumatic Universal Gate (MPL)

(Dreloea, E.Germany)
Fig. 4-18 : Pneumatic Gates (TELEMECHANIQUE, France)
Fig. 4-19 : Fluid Flip-Flop (Wall Attachment Principle)
Fig. 4-20 : Fluid OR-NOR Gate 4-8
Fig. 4-21 : Fluid NOR Gate (Impact Modulator, AIR Logic, USA)
Fig. 4-22 : Pneumatic Binary Amplifier (Single Stage, AIR LOGIC, USA)
Fig. 4-23 : Pneumatic Binary Amplifier (Two Stage, CLIPPARD, USA)

4-9
Fig. 4-25 : Comparison Between Switching Methods

4-10
Fig. 4-25 : Comparison Between Switching Methods

CHAPTER 5
ELECTRIC
LADDER DIAGRAMS
Ladder Diagram
Relays, Cylinders, Valves Symbols
Sequential Sequences
Relays Cascade Implementation
Huffman Methode
Flow Diagram
Primitive and Merged Flow Tables
State Assignment
Output and Exitation Functions
a1 a2
5-1
Switching Load-1
Circuit-1
-
Switching A+ A-
Circuit-2 Load-2
Switching Load-3
Circuit-3
a. Valve Without Return Spring
Switching Load-4
Circuit-4
| |
| | a2
| | a1
-
Switching Load-n
Circuit1-n A+
Fig. 5-1 : Ladder Diagram

b. Valve With Return Spring
START STOP Fig. 5-4 : Cylinder Actuation Valves

CR1
CR1
a. Basic Circuit
a1,a2 = 10
START STOP
CR1 a2
a1
CR1
-
(Closed) (open)
b. Basic Contacts Circuit A+ A-
Set Reset CR1

Circuit Circuit a. Position "-"
CR1
c. General Circuit a1,a2 = 00

a1 a2
Fig. 5-2 : Set-Reset Relay Flip-Flop
+
(open) (open)
A+ A-
START STOP
CR1
CR1
b. Position "Moving"
CR1 Red
Lamp
a1,a2 = 01
CR1 Red a1
Lamp a2
+
(open) (Closed)
a. Example - Schematic Circuit A+ A-
START STOP
Voltage c. Position "+"
8 1
7 2
Fig. 5-5 : Positions of Cylinder Limit Switches
RELAY
6 CR1 3
5 4
Red Red
Lamp Lamp
a. Normally Open b. Normally Closed

b. Example - Wiring Diagram
Fig. 5-6 : Graphic Symbols of Limit Switches
Fig. 5-3 : Flip-Flop Implementation Example
START,A+,A-,B+,10 Sec delay,B- 5-2
(STEPS 1 2 3 4 5)
:
a. Process Sequence (No Return Springs)
START
b1 A+ START
cr1 A+
b1
b. Step 1 : Actuate A+ a2 b2
CR1
cr1
START
b1 A+ A-
cr1
a2 A-
cr1 a1 B+
PROBLEM
Long Start causes Actuation of
A+ and A- simultaneously b2
TMR
c. Step 2 : Actuate A-
tmr B-
Add reset (b2') to CR1

START
b1 cr1 A+ f. Correct problems of (e)
a2 A-
cr1
CR1
START
a1 B+ b1 cr1
CR2
PROBLEM cr2 A+
B+ is also actuated
before cycle starts
a2 b2
CR1
d. Step 3 : Correct and Actuate B+
cr1
cr1 A-
START
b1 cr1 A+
cr1 a1
a2 CR3
CR1
cr3 B+
cr1
cr1 A-
b2
TMR
cr1 a1 B+
tmr B-
b2
TMR
tmr B-
g. Isolate Limit Swithes from Solenoids Current
PROBLEM
B+ and B- are actuated simultaneously.
CR1 is actuated infinitily
e. Steps 4-5 : Correct and Actuate TMR and B-
Fig. 5-7 : "Intuitive" Design Problems

5-3
RELAYS CASCADE SYSTEMS
* Avoid conflicting actuation of a

cylinder
C-
START , A+ , A- , B+ , C+ , , A- , B-
* Distinguish between situations A+
where a cylinder performs more than
I II III IV
a single cycle
Fig. 5-10 : Typical Groups Partitioning

* Maximal size groups (to obtain
minimum number of group relays)
* Same "Letter" may appear no more
than once in a group (to avoid
conflicted commands to a cylinder)
* Except for specific cases, groups START cr3' cr4' cr2'

Partitioning doesn't depend on having CR1
or not having valves return springs cr1
cr1 cr3'
Fig. 5-8 : Cascade Method Target & Rules Group 1 CR2
Termination
cr2
cr2 cr4'
Group 2 CR3
Termination
cr3
C-
START , A+ , A- , B+ , C+ , , A- , B-
cr3
A+ Group 3 Group 4 (Last) CR4
Termination Termination
cr4
a. Sequence List Representation
A+
1 2 3 4 5 6 7 8 9 cr
Group(s) Condition(s)
A+
A-
A- cr
B+
B- B+
cr
C+ Group(s) Condition(s)
C-
START B-
cr
a2 Group(s) Condition(s)
a1
b2 C+
cr
b1
c2
C-
c1 cr
b. Flow Chart Representation

Fig. 5-11 : Typical Initial Cascade Circuit,
of 3-Cylinder / 4-Groups Process
Fig. 5-9 : Typical Process Definition
A- C- A- C-
START , A+ , , C+ , A- C- START , A+ , , C+ , , A- , B-
, A- , B- START , A+ , , C+ , , A- , B- B+ A+ B+ duration
B+ A+ B+ A+
1. Cylinders are actuated by 5/2 valves without I II III IV 1. Cylinders are actuated by 5/2 valves with A- C-
START , A+ , , C+ , , A- , B-
return springs. return springs. B+ A+
2. Valves are actuated electrically (solenoids). 2. Valves are actuated electrically (solenoids). I II III IV
b. Groups Partitions
a. Process Sequence Information a. Process Sequence Information b. Groups Partitions
START START START

cr3' cr4' cr2' cr3' cr4' cr2' START cr3' cr4' cr2'
CR1
CR1 cr3' cr4' cr2' CR1
cr1 CR1
cr1 cr1
cr1
cr3'
cr1 cr3' cr3'
CR2 cr1 a2 cr3' cr1 a2
CR2 cr1 CR2
cr2 CR2
cr2 cr2
cr2
cr2 cr4' cr2 cr4' cr4'

CR3 c2 cr4' cr2 c2
CR3 cr2 CR3
cr3 CR3
cr3 cr3
cr3
cr3 CR4
cr3 c1 a2 b1 cr3 c1 a2 b1
CR4 cr3 CR4
CR4
cr4 cr4 cr4
cr4
cr A+ A+ cr1
cr1 A+
cr A+ cr3
cr3
cr A- A- cr B+ cr2 B+
cr2
cr3 cr3
cr C+
cr4 a1
cr B+ cr2 B+
c. Total Initial Circuit cr2 a1 b2
C+
cr B- cr2 a1 B-
d. Complete Circuit
cr C+ cr2 a1 b2 C+
Fig. 5-13 : Relay Cascade Design Process 1 (With Return Springs)
cr C- cr3 C-
c. Total Initial Circuit

d Complete Circuit
5-4
Fig. 5-12 : Relay Cascade Design Process 1 (No Return Springs)
START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- , START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- ,
1. Cylinders are actuated by 5/2 valves without return springs. 1. Cylinders are actuated by 5/2 valves with return springs.
2. Valves are actuated electrically (solenoids). 2. Valves are actuated electrically (solenoids).
a. Process Sequence Information
a. Process Sequence Information
B+
A+ D+
START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- ,
START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- ,
I II III (IV)
I II III (IV)
b. Groups Partition
cr2'
START START cr3' cr4' b. Groups Partition
cr3' cr4' cr2' cr2'
CR1 CR1
START cr3' cr2' START cr3' cr2'
cr1 cr1 a1
CR1 CR1
cr1 cr1
cr1 cr3' cr1
cr1 c2 cr3'
CR2 CR2
cr2 cr2 cr1 cr3' cr1 c2 cr3'
CR2 CR2
cr4' b1 cr2 cr2

cr2 cr2 d2
CR3 CR3
cr3 cr3 b1
cr2 cr2 d2
CR3 CR3
cr3 cr3 b1 a1 cr3 cr3

CR4 CR4
cr4 cr4
cr1 A+ cr1 A+
cr A+ cr1 A+
cr3 c1
cr3
cr3
cr A- cr2 c1 A-
cr1 B+ cr1 a2 B+
cr4
cr2
cr B+ cr1 a2 B+
cr3 d1
cr B- cr3 d1 B-
cr1 C+ cr2 b2 C+
cr C+ cr1 b2 C+
cr1 D+ cr2 a1 D+
cr C- cr2 C-
cr3 a2
cr D+ cr2 a1 D+
cr cr3 c. Total Initial Circuit d. Complete Circuit

D- a2 D-
c. Total Initial Circuit d. Complete Circuit Fig. 5-15 : Relay Cascade Design Process 2
5-5
(With Return Springs)
Fig. 5-14 : Relay Cascade Design Process 2
(Without Return Springs)
5-6
* System requirements definition
External External
Inputs Outputs * Primitive flow diagram
Combination
System * Primitive flow table
* Merge options Diagram
* Merge groups selection
* Merged flow table
Memory
System * States assignment
Internal Memory
State Exitation * Output table
* Flip-flops exitation expressions
a. General Block Diagram
* Outputs expressions
External * System Logic Circuit
External Outputs
Inputs
X1 Z1
Fig. 5-18 : Huffman Design Steps
Xn Combination Zm
System
Yk
Y1 Huffman method is very effective in

reducing the number of relays flip-flops.
S
Y R It is also effective for design of
systems with Random Inputs.
S
Y R
Internal Set-Reset Design process by Huffman method
State Control
may become very complex, from
"State Assignmsnt" step, and on.
b. General Detailed Block Diagram Furthermore, it is based on
Karnaugh maps, which eliminate
Fig. 5-16 : Sequential System the number of involved variables.
When system realization is based on PLC,

Set number of "relay" flip-flops doesn't actually
effect system cost.
Reset
The Huffman-PLC method implements
Electrical flip-flop for each state, but eliminates the
Delay td1 td3
complexity of Huffman method, and also
Mechanical
enables to implement large Pseudo
Delay td2 td4 Karnaugh maps.
Fig. 5-19 : Huffman/PLC Combination

Unstable Stable State Unstable
State State
a. Relay Flip-Flop Transition Response
Each transition is combined of Unstable Two (or more) lines in flow table can be merged,
State, followed by a Stable State. as long as they don't conflict.
Unstable State duration is the time delay Merging lines reduce internal states, reduce
from the command start (set/reset) to its number of required flip-flops, and make design
fully execution. more simple.
Refering to relay flip-flop, unstable State
duration is the time delay from the set
(or reset) start until relay contact 1 2 - 4 - Line i
closing (or releasing).
Unstable state i will be represented by
1 2 3 - - Line j
its number : i.
Stable state i will be represented by its 1 2 3 4 - Merged Lines (i,j)
number surround by a circle : i
b. Stability Definition
Fig. 5-20: Merge Flow Lines Rules
Fig. 5-17 : Stability States
START , A+ , {1,2) , (3,4)
{1,2) , (3,4) START , A+ ,
A-
a. Sequence f. Selected Groups A- f. Selected Groups
a. Sequence
a1,a2 a1,a2
10 00 01 11 10 00 01 11
START START
CONTROL
1 2 3 - CONTROL
1 2 3 -
a1 SYSTEM A+ a1 SYSTEM A+
a2 1 4 3 - a2 1 4 3 -
b. Basic Block Diagram g. Merged Flow-table
b. Basic Block Diagram g. Merged Flow-table
START 10/1
1 a1,a2 a1,a2
START 10/1
10 00 01 11 1 10 00 01 11
CR1 CR1
00/0 4 2 00/1
0 1 2 3 - 00/0 4 2 00/1 0 1 2 3 -
3 01/0
1 1 4 3 - 3 1 1 4 3 -
01/0
c. Primitive Flow-diagram
h States Assignment c. Flow-diagram (primitive) h States Assignment
a1,a2
10 00 01 11 a1,a2 a1,a2 a1,a2
CR1 10 00 01 11 10 00 01 11 10 00 01 11
1
,1 2 - - CR1
0 1 1 - - 1 2 - - 10 -0 - -
10 0
- 2 ,1 3 -
1 - 0 0 - - 2 3 - - 0- 01 -
- 4 3 ,0 - -0 1
- 4 3 - a1,a2 a1,a2
1 4 ,0 01
- - A+ CR1 10 00 01 11 CR1 10 00 01 11
1 4 - -
i Output Table 0- 0 0
d. Primitive Flow-table 1 - - - 0 0 - -
d. Primitive Flow-table
a1,a2
S1 = a2 (S1 =cr1'. a1'.a2) 1 - 0 0 - 1 - - 1 -
R1 = a1 (R1 =cr1. a1.a2')
10 00 01 11 A+
A+ = cr1' a1,a2
A+ i. Output Tables A-
1 10 00 01 11 A+ A-
2 - - 1 A+ = START.a1 + a1'.cr1'
1 2 - - 1 0 S1 = a2 (S1 = cr1'.a1'.a2)
- 2 3 - 1 j. Exitation and Output Functions R1 = a1 (R1 = cr1.a1.a2')
- 2 3 - - 0 A+ = cr1'
- 4 3 - 0
A+ = START.a1
a2 a1 3
1 4 CR1 - 4 - 0 1 A- = cr1
- - 0
cr1
4 0 - k. Exitation and Output Functions
1 - -
d.1 . Primitive Flow-table START
(Different Format) a1 d.1. Primitive Flow-table a2 a1
A+ (Different Format) CR1
1 cr1
cr1 a1 1
START a1
A+
4 2 4
k. Relays Ladder Diagram 2
cr1 A-
3
3
e. Merge Diagram e. Merge Diagram
Fig. 5-21 : Sequence A+,A- (Huffman Method)
5-7
j. Relays Ladder Diagram
(With Returned Springs)
Fig. 5-22 : Sequence A+,A- (Huffman Method)
(Without Returned Springs)
START , A+ , A- , A+ , A- a1,a2
10 00 01 11
START , A+ , A- , A+ , A-
a. Sequence 1 2 3 - a1,a2 a1,a2
10 00 01 11 CR 10 00 01 11
START
5 4 3 - a. Sequence
CONTROL 1 2 3 - CR1 1 2 3 -
a1 SYSTEM A+ 5 6 7 -
a2 5 4 3 - CR2 5 4 3 -
1 8 7 - START
A+
CONTROL CR3
b. Basic Block Diagram a1 SYSTEM A- 5 6 7 - 5 6 7 -
g. Merged Flow-table a2
10/1 1 8 7 - CR4 1 8 7 -
START 1 a1,a2 b. Basic Block Diagram
10 00 01 11 g. Merged Flow-table h. States Assignment
00/0 8 2 00/1
CR1 1 2 3 - 10/10
a1,a2
CR2
5 4 3 - START 1 CR 10 00 01 11
01/0 7 3 01/0
CR3 5 6 7 - 00/0- 8 2 00/-0 CR1 10 -0 - -
00/1 6 4 00/0 1 8 7 - CR2 - 0- 01 -
CR4
01/01 7 3 01/01
5 10/1 CR3 10 -0 - -
h. States Assignment
c. Primitive Flow-diagram 00/-0 6 4 00/0- CR4 - 0- 01 -
a1,a2
CR 10 00 01 11 A+ , A-
a1,a2
5 10/10
CR1 1 1 - - a1,a2 a1,a2
10 00 01 11 CR 10 00 01 11 CR 10 00 01 11
CR2 - 0 0 - c. Primitive Flow-diagram
1
1
2 - - CR1 1 - - - CR1 0 - - 0
CR3 - -
- 2
1 3 - 1 1
a1,a2 CR2 - 0 0 - CR2 - - 1 -
CR4 - 0 0 -
- 4 3
0
- 10 00 01 11
CR3 1 - - - CR3 0 0 - -
A+ 1 2 -
5 4
0
- -
i. Output Table
10 - CR4 - 0 0 - CR4 - - 1 -
- 2
-0 3 -
5 6 - - A+ A-
1
- i. Output Tables
- 6 - 4 3
1 7 - S1 = cr4.a1 R1 = cr2 (R1 = cr2.a2) 01
S2 = cr1.a2 R2 = cr3 (R2 = cr3.a1) 4 - -
7 - 5 0- S1 = cr4.a1 R1 = cr2 (R1 = cr2.a2)
- 8 0 S3 = cr2.a1 R3 = cr4 (R3 = cr4.a2)
S4 = cr3.a2 R4 = cr1 (R4 = cr1.a1) S2 = cr1.a2 R2 = cr3 (R2 = cr3.a1)
5 - -
8 - - 10 6 S3 = cr2.a1 R3 = cr4 (R3 = cr4.a2)
1 0 S1 = a1(cr2+cr3)' = a1.cr2'.cr3'
S4 = cr3.a2 R4 = cr1 (R4 = cr1.a1)
A+ = cr1 + cr3 - 6
-0 7 - S1 = a1(cr2+cr3)' = a1.cr2'.cr3'
d. Primitive Flow-table A+ = START.cr1.a1 + cr1.a1' + cr3
7 - A+ = cr1 + cr3
- 8 01
j. Exitation and Output Functions A+ = START.cr1 + cr3
1 8 - - A- = a2
1 0-
a1 cr2 cr3 cr2 j. Exitation and Output Functions
2 CR1 d. Primitive Flow-table
8 cr1
a1 cr2 cr3 cr2
cr1 a2 cr3 1 CR1
3 cr1
CR2
7 cr2 2
8 cr1 a2 cr3
cr2 a1 cr4 CR2
6 4 cr2
CR3
cr3 3
5 7 cr2 a1 cr4
cr3 a2 cr1 CR3
e. Merge Diagram CR4 cr3
cr4 6 4
cr3 a2 cr1
START A+
5 CR4
{1,2) , (3,4) , (5,6) , (7,8) cr1 a1 cr4
e. Merge Diagram
f. Selected Groups cr1 a1 START A+
cr1
cr3 {1,2) , (3,4) , (5,6) , (7,8)
cr3
f. Selected Groups
a2 A-
5-8
Fig. 5-23 : Sequence A+,A-,A+,A- (Huffman Method) k. Relays Ladder Diagram
Fig. 5-24 : Sequence A+,A-,A+,A- (Huffman Method)
(With Returned Springs) k. Relays Ladder Diagram
(Without Returned Springs)
A mixing system requires filling a tank with liquid, mix it for a
specific time and then drain the liquid out.
Process is same as defined ai Fig. 6-25/a . 5-9
An automatic process is represented as follows : a. Process definitions
LHT
1. Sequence starts by pressing START buttom. This opens FIll valve.
2. Liquid fills tank until HIGH level switch is operated. 000 100 110 111 101 F D M Ymr
3. At that time FILL valve is closed, mixing motor is turned on, and a
timer is activated 1 2 - - - 1 0 0 0
4. On timeout, motor is turned off, and DRAIN valve is opened.
5. When tank is empty, LOW level switch is opened, and DRAIN valve
- 2 3 - - 1 0 0 0
is closed.
- - 3 4 - 0 0 1 1
Fill Valve
- - - 4 5 0 1 - 1
F
Mixer Motor - 6 - - 5 0 1 0 0
M
1 6 - - - 0 1 0 0
Level Switch
b. Primitive Flow Table
H (High)
1
Level Switch 2
L (Low) 6
Drain Valve D
Start 5 3
F
L MIXING
D
H
SYSTEM 4
M
T TMR c. Merge Diagram
Timer
a. Process presentation and requirements definitions {1 , 2 , 3} , {4 , 5 , 6}

d. Selected Groups Partition
F' LHT
D L.H
START , F , (H) M CR 000 100 110 111 101 00 10 11 01
, (T) , (L') D'
CR,T
M' 1 - -
TMR 1 1 2 3 4 - 00
6
0 1 6 - 4 5 01 - 5 4 -
b. Process Sequence
11 - - 4 -
e. Merged Flow Table
10 1 2 3 -
F' f. "Path" Map
D
START , F , M , D'
M'
TMR L.H START L.H START
CR,T 00 10 11 01 CR,T 00 10 11 01
I II III IV
- -
c. Groups Partition
00 0 0 - 00 0 1 -
01 - 0 0 - 01 - 1 1 -
11 - - (0) - 11 - - - -
START L cr3 cr2
CR1 10 1 1 0 - 10 0 0 0 -
cr1
F D
cr1 cr3 L.H L.H
H
CR2 CR,T 00 10 11 01 CR,T 00 10 11 01
cr2
00 (0) 0 - - 00 (0) 0 - -
L 01 - 0 - - 01 - 0 1 -
cr2 T
CR3
11 - - - - 11 - - (1) -
cr3
10 0 0 1 - 10 0 0 1 -
cr1 F
M TMR
g. Output Tables
cr2
M
S = L'.START F = H'.CR M=H
Tmr
R = tmr D = L.CR' TMR = H
cr3 D h. System Functions
d. Cascade Contacts Circuit Fig. 5-26 : Automatic Mixing System

Huffman Method
Fig. 5-25 : Automatic Mixing System
Cascade Method
1 2 3 4 5 6 7 8 1 1 2 3 4 1
10 00 01 00 10 00 01 00 10 10 01 10 01 10
5-10
a. Sequence Inputs b. Ignore Input 00
Fig. 5-27 : Full/Partial Input Stream (A+,A-,A+,A-)
a1,a2 a1 a1,a2
CR 00 01 11 10 CR 00 01 11 10 a1 a2
CR1 - 1 CR1
CR2 - CR2
CR3 1 - CR3
CR4 - CR4
a2
a1.a2'.F a1.F Column 00 not required c. Pseudo Map

a1'.a2.F a2.F Column 11 merge
a. Column 11 Merge b. Reduced Columns
Fig. 5-28 : Full/Pseudo Karnaugh Maps
a1 a2 A+ A- a1 a2 A+ A- a1 a2 a1 a2
S1 = CR2'.CR3'.a1.Start R1 = CR2.a2
1 2 1 0 CR1 1 2 1 0 1 - CR1 0 -
S2 = CR1.a2 R2 = CR3.a1
3 2 0 1 CR2 3 2 0 1 - 0 CR2 - 1 S3 = CR2.a1 R3 = CR4.a2
S4 = CR3.a2 R4 = CR1.a1
3 4 1 0 CR3 3 4 1 0 1 - CR3 0 -
A+ = CR1+CR3
1 4 0 1 CR4 1 4 0 1
* 0 0 CR4 - 1
A- = a2
a. Primitive Flow Table b. State Assignment c. A+ Map d. A- Map e. System Functions
Fig. 5-29 : Pseudo Map For A+,A-,A+,A- * Assigned "0" to "rest" state
b1 b2
a1 b1
a1.b1 a2.b1 a2.b2 a1.b2
CR1 CR1
CR2 CR2
CR3 CR3
CR4 CR4
a2 a1 a2 a1
b2
Fig. 5-30 : Pseudo Map For 2 Cylinders & 4 States
b1 b2
d1 d2 CR1
CR5 CR2
CR6 CR3
CR4
CR7
a1 a1
CR8
a2
c1 c1
c2
Fig. 5-31 : Pseudo Map For 4 Cylinders & 8 States

1 2 3 4 5 6 7 8 1 5-11
a2
a1 B+ A+
b2
START , A- , B- , A- , C+ , C- , A+
b1
C+ C-
c2
c1
a. Sequence Inputs
1
8 2
a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1 a1.b1.c2 A+ A- B+ B- C+ C-
1 2 - - - 1 0 - 0 - 0
- 2 3 - - - 0 0 1 0 1 7 3
- - 3 4 - 0 1 0 - 1 0
5 - - 4 - 0 - 1 0 - 0 6 4
5
5 6 - - - 1 0 - 0 - 0
c. Merge Diagram
- 6
- - 7 - 0 - 0 0 1
{1,2},{3,4,5,6},{7,8} Selected
- 8 - - 7 - 0 - 0 1 0
{1,2},{3,7,8},{4,5,6)
1 8 - - - 0 1 - 0 - 0 {1,2,3},{4,5,6},{7,8}
b. Primitive Flow Table d. Merge Options
a1 a2 a1 a1 a2 a1
(b2.c1)
(a2.b1) (b2.c2) (a2.b2) (b1.c2) CR1 2 1 - - CR1 - - - 3
a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1 a1.b1.c2 CR2 6 5 4 - CR2 7 - - 3

CR1 1 2 3 - - CR3 8 1 - - CR3 7 - - -
CR2 5 6 3 4 7 b1 b2 b1 b2
CR3
1 8 - - 7 c1 c2
e. Merged Flow Table

f. Path Map
a1 a2 a1 a1 a2 a1 a1 a2 a1 a1 a2 a1
CR1
0 0 - - CR1 - - - - CR1 - 1 - - CR1 - - - -
CR2 0 0 - - CR2 0 - - 1 CR2 - 1 0 - CR2 - - - 0
CR3 1 - - - CR3 0 - - - CR3 0 - - - CR3 - - - -

b1 b2 b1 b2 b1 b2 b1 b2
c1 c2 c1 c2
A+ A-
a1 a2 a1 a1 a2 a1 a1 a2 a1 a1 a2 a1
CR1
1 0 - - CR1 - - - - CR1
0 - - - CR1 - - - 0
CR2 0 0 0 - CR2 0 - - - CR2 - - 1 - CR2 - - - 0

S1 = Start.a2.CR2'
CR3 0 0 - - CR3 0 - - - CR3 - - - - CR3 - - - - S2 = b2
b1 b2 b1 b2 b1 b2 b1 b2 S3 = b1.c2
c1 c2 c1 c2
B+ B- R1 = b2
R2 = b1.c2
R3 = CR1.a2
a1 a2 a1 a1 a2 a1 a1 a2 a1 a1 a2 a1
CR1
1 0 - - CR1 - - - - CR1 0 - - - CR1 - - - - A+ = CR3.c1+b2
A- = a2.b1
CR2 1 0 0 - CR2 - - - 0 CR2 0 - - - CR2 - - - 1
B+ = CR1.a1
CR3 0 0 - - CR3 0 - - - CR3 - - - - CR3 1 - - - B- = a2
b1 b2 b1 b2 b1 b2 b1 b2 C+ = a1.b1(CR1+CR2)
c1 c2 c1 c2
C- = c2
C+ C-
h. System Functions
g. Output Maps
Fig. 5-32 : Pseudo Karnaugh Map Example

i Zi i Zi
1
"Ready" Signal Xi
Wait
Xi-P Xi-P
START - L'
A1 ZA1 B1 ZB1 A1 ZA1 B1 ZB1

2 F
XA1 XB1 XA1 XB1
H

3 F' M Ytmr
XA2 XB2 XA2 XB2
.....
.....
Ytmr
.....
.....
XAJ-1 XBk-1 XAJ-1 XBk-1
4 M' D
Aj ZAj Bk ZBk Aj ZAj Bk ZBk
L'
XAj XBk
5 XAj.XBk
D'
END
Valve D is Closed i+1 Zi+1 i+1 Zi+1
Xi+1 Xi+1
Fig. 5-33 : GRAFCET for

Automated Mixing
Fig. 5-34 : GRAFCET for Fig. 5-35 : GRAFCET for
System (Fig. 5-25) Alternate Parallel Paths Simultaneous Parallel Paths
5-12
i ZB1 i Zi
1 "Ready" Signal Xi
Wait
Xi-P Xi-P
START - L'

2 F
XA1 XB1 XA1 XB1
H

3 F' M Ytmr
XA2 XB2 XA2 XB2
.....
.....
Ytmr
.....
.....
XAJ-1 XBk-1 XAJ-1 XBk-1
4 M' D
Aj ZAj Bk ZBk Aj ZAj Bk ZBk
L'
XAj XBk
5 XAj.XBk
D'
END
Valve D is Closed i+1 Zi+1 i+1 Zi+1
Xi+1 Xi+1
Fig. 5-33 : GRAFCET for

Automated Mixing
Fig. 5-34 : GRAFCET for Fig. 5-35 : GRAFCET for
System (Fig. 5-25) Alternate Parallel Paths Simultaneous Parallel Paths
5-12
\
Start AND Initial Conditions
Advance 5 Advance Discend

2 Loader Clamp 10 Gauge T=2s
Piece Loaded Piece Clamped

Gauge Down AND T<2s T>2s
3 Retract Discend Raise Raise

Loader 6 Drill 11 Gauge 15 Gauge
Loader Retracted Drill Down Gauge Up Gauge Up
4 Rase Advance
7 Drill 12 Ejector 16
Wait
Drill Up Piece Ejected Manual Reset
8 Retract Retract
Clamp 13 Ejector
Piece Unclamped Ejector Retacted
9 14
Wait Wait
=1
17 Rotate
Plate
Plate Rotated
Fig. 5-37 : GRAFCET for Drilling Station

(From Telemechanique TSX T607 Manual)
5-13
CHAPTER 6
SEQUENTIAL SYSTEMS WITH

RANDOM INPUTS
Random Signals
Examples
Design as Input to PLC System
{1,2,5},{3,4} 6-1
1. Different size elements are transferred on a conveyor belt.
2. All elements that are below specific thickness must be rejected. {1,5},{2,3,4}
3. Reject is performed by opening a reject door - Z=1.
4. Photocells X1 and X2 are placed in specific locations.
5. X2 is covered by all sizes. X1 is covered by elements over f. Merge Options
specific thickness.
X1 X2
{1,5},{2,3,4}
g. Selected Options
X1,X2
00 10 11 01
1 2 - 5
a. System Definition 1 2 3 4
Photocell 1 X1 THOCKNESS
DETECTOR T Reject Door h. Merged Flow Table
Photocell 2 X2 SYSTEM
X1,X2
b. System Block Diagram CR 00 10 11 01
0 1 2 - 5
1 1 2 3 4
00/0 10/0 11/0 01/0
1 2 3 4
i. State Assignment
X1,X2
01/1 CR 00 10 11 01
5
c. Primitive Flow Diagram 0 0 (0) - 1
1 (0) 0 0 0
X1,X2
00 10 11 01 Z j. Output Table
1 2 - 5 0
S = X1 (S = X1.X2')
- 2 3 - 0 R = X1'.X2'
4 Z = X2.CR'
- - 3 0
k. System Functions
1 - - 4 0
1 - - 5 1
X1 X1
d. Primitive Flow Table CR1
CR X2
1 Z
CR X2
l. Relays Implementation
5 2
(CR = Q)
X1 S Q
3 R Q'
Z
4
e. Merge Diagram X2
m. Gates Implementation
Fig. 6-1 : Thickness Detector System Design

A red light signal is placed in the junction of road and raillway. 6-2
Train must operate red light as soon as it enters "junction area", far from the junction, and turn it off as soon as
last waggon leaves the railway (near junction).
Trains may go in two direction, but the following assumption are known :
* Only a single train crosses the junction area, at a time.
* Train doesn't changes direction within the junction area.
Junction Area
L
RAILWAY
ROAD
L
One of the tracks is connected to common node (Ground), while the other track is splitted - within the junction area -
into 3 sections, that are physically joined, but electrically isolated from the tracks outside the junction area.
Mid-section is also isolated from the other 2 sections (that are connected electrically).
Junction Area
L
A B
When the junction area is empty (no trains inside) all 3 sections are disconnected from common track, thus providing
"0" signal on each section.
When the train crosses a track section, it connects it electrically to the common track, thus changing its signal into "1".
Signal returns to "0" as soon as last waggon leaves the appropriate section.
Signaling control system senses A and B signals, and turns red light on or off, accordingly.
a. System description
1
AB
CONTROL 00 01 11 10
A CR1
SYSTEM L 5 2
0 0 1 (1) 1
B
1 (0) 0 1 (0)
b. Basic Block Diagram
4 3
00/0 L
e Merge Diagram j. Output Table
AB/L 1
01/0 4 2 01/1 {1,2,5) , (3,4)

{3.,4,5) , (1,2)
3
11/1 f. Merge Options
5 01/1 {1,2,5) , (3,4)

g. Selected Groups S1 = AB
c. Flow-diagram (primitive) R1 = B' (R1' = B)
AB L = A + CR1'.B
00 01 11 10
k. Control Functions
AB 5
1 2 3
00 01 11 10
A B B
1 - - 1 4 3 5
0 2 CR1
CR1
- 2 3 - h. Merged Flow-table
1
- 4 3 5 AB CR1 B
1
CR1 00 01 11 10 L
1 4 - -
0 3 5 A
0 1 2
- - 3 5
1 1 1 4 3 5
l. System circuit
d. Primitive Flow-table i. States Assignment
Fig. 6-2 : Traffic-Light Control System Design

1. External alarm sets X1=1. It must activate siren Z1, until
6-3
operator confirmation {3,4,5} {2.6} {1}
2. Operator confirms by pressing X2 buttom. This de-activates siren.
3. If alarm signal still exists, flash light is activated. {1,5} {2.6} {3,4}
4. After confirmation, flash also is de-activated.
a. System Definition f. Merge Options
Danger Signal X1 ALARM Z1 ALARM SIREN

SYSTEM {1,5} {2.6} {3,4}
Confirmation X2 Z2 ALARM FLASH
g. Selected Options
b. System Block Diagram
00 10 11 01
CR1 1 2 3 5
00/00 10/10 11/01 10/01
1 2 3 4 CR2 6 2 3 5
CR3 1 4 3 5
01/00 00/10
5 6
h. Merged Flow Table &
States Assignment
c. Primitive Flow Diagram

00 10 11 01 00 10 11 01
00 10 11 01 z1 z2 CR1 0 - (0) 0 CR1 0 (0) - 0
1 2 - 5 0 0 CR2 1 1 (0) - CR2 0 0 - (0)
6 2 3 - 1 0 CR3 (0) 0 0 (0) CR3 - 1 1 -

- 4 3 5 0 1 i. Output Table of Z1 j. Output Table of Z2
1 4 3 - 0 1
1 - 3 5 0 0
S1 = X1'.X2'.CR2' + X1'.X2 = X1'(X2 + CR2')
6 2 - 5 1 0 S2 = CR1.X1.X2'
S3 = X1.X2
d. Primitive Flow Table
R1 = CR2.X1.X2' + X1,X2 = X1(X2 + CR2)
R2 = X1'.X2 + X1.X2 = X2
1 R3 = CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1'
Z1 = CR2.X2' *
Z2 = CR3
6 2
k. Exitation & Output Functions
3
5
e. Merge Diagram Fig. 6-3 : Alarm System Design

B
6-4
A
a. Disk Partitions ans Sensors Arrangement
Change 0
Direction 360
0
90
A
1
B 8 2
"UP" direction "DOWN" direction
(A leads B) (B leads A)
7 3
b. Encoder Code Waveforms for Both Directions
6 4
CONTROL
A D 5
B SYSTEM
f. Merge Diagram
c. Contro,l System Block Diagram
AB AB
00 01 11 10 00 01 11 10
CR1 1 5 8 2 CR1 O 1 (1) (0)
CR2 6 5 3 2 CR2 1 (1) (0) O

01/1 00/1 10/1 11/1
5 6 7 8
CR3 6 4 3 7
CR3 (1) (0) O 1
CR4 1 4 8 7 CR4 (0) O 1 (1)

00/0 10/0 11/0 01/0 D
1 2 3 4 g. Merged Flow-table &
State Assignment h. Output Table
d. Primitive Flow-diagram
S1 = CR4.A.B' + CR2.A'B' R1 = CR2.A.B' + CR4.A.B
S2 = CR1.AB' + CR3.A.'B' R2 = CR1.A'B + CR3.AB
AB
S3 = CR2.A.B + CR4.A.B' R3 = CR2.A'.B' + CR4.A'B
00 01 11 10 D
S4 = CR1.A.B + CR3.A'B R4 = CR1.A'.B' + CR3.AB'
1 5 - 2 O
D = CR1.B + CR2.A' + CR3.B' + CR4.A
6 - 3 2 O i. Exitation and Output Functions
- 4 3 7
O
8 Initially, while A=B=0, and all Flip-flops are in reset
1 4 - O
state (CRi=0).
1 5 8 - 1 At that state, Flip-flop 1 must be set, with no confilict later,
that is to say, while CR1 and CR2 are not set.
6 5 - 2 1 S1 = A'B'.CR2'.CR3'
6 - 3 7 1 j. Corrected System Initialization
- 4 8 7 1
e. Primitive Flow-table Fig. 6-4 : Motor Direction Detection System Design
6-5
1. A security door is controlled by two input switches : X1 and X2 .

2. The door is opened and closed, by entering the following sequence :
X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00
Open (T=1) Close (T=0)
Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as
input becomes 00.
a. System Definition
Improper Sequence Proper Sequence

Switch X1
Combination Open
Switch X2 Lock T Door
X1,X2 / T
01/0 00/0 10/0

11/0
8 1 2
b. System Block Diagram 3
01/1
7
11/0 10/0 10/1 11/1 10/0

9 10 6 5 4
X1,X2
00 01 11 10 T
1 8 - 2 0
1 - 3 2 0
- 8 3 4 0 1
10
1 - 5 4 0 2
- 7 5 6 1
1 - 5 6 1 9 3
1 7 5 - 1
1 8 9 - 0 8 4
- 8 9 10 0
1 - 9 10 0 7 5
d. Primitive Flow Table 6
e. Merge Diagram
X1,X2 X1,X2
00 01 11 10 00 01 11 10 {1,2},{3},{4},{5,6,7},{8,9,10}
f. SelectedMerge Partitions
CR1 1 8 3 2 CR1 0 - - 0
CR2 - 8 3 4 CR2 - - 0 - S1 = X1'.X2' R1 = CR2.X1.X2 + CR5.X1'.X2
CR3 1 - 5 4 CR3 - - - 0 S2 = CR1.X1.X2 R2 = CR3.X1.X2' + CR5.X1'.X2
S3 = CR2.X1.X2' R3 = CR4.X1.X2 +X1'.X2'
CR4 1 7 5 6 CR4 - 1 1 1 S4 = CR3.X2 R4 = X1'.X2'
CR5 1 8 9 10 CR5 - 0 0 0 S5 = CR4'.X1'.X2 R5 = X1'.X2'
g. Merged Flow Table h. Output Table T = CR4

& States Assignment i. System Functions
Fig. 6-5 : Combination Lock System Design

PART 2
Chapters 7 - 12
List of Figures PART 2 Updated :
July 20, 2003
CHAPTER 7 Pneumatic Control Circuits

Fig. 7-1 7-1 Intuitive Design Of Sequence A+,B+,A-,B-
Fig. 7-2 7-1 Intuitive Design Of Sequence A+,B+,B-,A-
Fig. 7-3 (a-b) 7-1 Cascade Design Of Sequence A+,B+, B-, A-,C+.C-
Fig. 7-4 7-1 Cascade Design Of Sequence A+,A-,A+,A-
Fig. 7-5 7-1 Multiple Limit-Valves Replacement
Fig. 7-6 7-2 Pneumatic Cascade Basic Concept
Fig. 7-7 (a-c) 7-2 Pneumatic Cascade Group Configurations
Fig. 7-8 (a-g) 7-3,4 Pneumatic Cascade Design Process Steps
Fig. 7-11 (a-b) 7-6 Flip-Flop Valve & Steering Valve
Fig. 7-12 7-6 Two Steering Valves Providing Three Addresses
Fig. 7-13 7-6 Three Steering Valves Providing Four Addresses
Fig. 7-14 (a-e) 7-6 Design Sequence A+,A-,A+,A-,A+,A-
Fig. 7-15 (a-d) 7-6 Design Sequence A+,B+,A-,B-,(A+/B+),A-,B-
Fig. 7-16 (a-e) 7-7 Design Sequence A+,B+,B-,C+,B+,B-,C-,A-
Fig. 7-17 7-8 Simplified Input Map
Fig. 7-18 (a-d) 7-8 Design a Sequence With Passive States
Fig. 7-19 7-9 Examples of Complex Functions
Fig. 7-20 7-9 Function Tables Background
Fig. 7-21 (a-b) 7-9 Function Tables Arrangement
Fig. 7-22 (a-b) 7-9 3/2 Valve Connections yielding Single Output Function
Fig. 7-25 7-12 Valve Connections With 2 Separate Outputs, 4/5-Variables Input
Fig. 7-26 7-13 Valve Connections yielding Flip-Flop Output Functions
Fig. 7-27 7-14 Example 1
Fig. 7-28 (a-f) 7-14 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-)
Fig. 7-29 (a-h) 7-15 Solution for Sequence A+,B+,B-,A-,B+,B-
Fig. 7-30 (a-c) 7-16 Stop-Restart With Single Button & Separate Buttons
Fig. 7-31 7-16 Stop-Restart With Multiple Remote-Control Stop Buttons
Fig. 7-32 7-16 Electronic Circuit for Fig. 7-31
Fig. 7-33 7-16 Emergency Stop Modes Definition
Fig. 7-34 (a-d) 7-16 Pneumatic / Electric
Fig. 7-35 7-17
Fig. 7-36 7-17
Fig. 7-37 7-17
Fig. 7-38 7-17
Fig. 7-39 7-17
Fig. 7-40 7-17
CHAPTER 8 Miscellaneous Switching Elements
& Systems
Fig. 8-1 (a-h) 8-1 Sequence Chart for Common Timers Modes
Fig. 8-2 8-1 -
Fig. 8-3 8-1 -
Fig. 8-4 8-1 -Delay Off-
Fig. 8-5 8-1 -
Fig. 8-6 8-1 - linder Retraction
Fig. 8-7 (a-b) 8-1 Sequence Charts for Pulse Shaper
Fig. 8-8 8-1 Relay Pulse Shaper
Fig. 8-9 8-1 Pneumatic Pulse Shaper
Fig. 8-10 (a-c) 8-2 Basic Set-Reset Flip-Flop (SR)
Fig. 8-11 (a-b) 8-2 Toggle Flip-Flop (T)
Fig. 8-12 (a-d) 8-2 T Flip-Flop Implementation - Counters
Fig. 8-13 (a-c) 8-2 D Flip-Flop Implementation Shift Register
Fig. 8-14 8-3 10-Stage Shift Register
Fig. 8-15 8-3 Shift Register With 4 Parallel Tracks
Fig. 8-16 8-3 Schmitt-Trigger Response
Fig. 8-17 8-3 Schmitt-Trigger Response to Fuzzy Waveform
Fig. 8-18 8-3 Truth Table for Error-Checking of BCD code
Fig. 8-19 8-4 Truth Table for 2-Out-of-5 Code
Fig. 8-20 (a-d) 8-4 Use of Karnaugh Map to Obtain Cyclic Code
Fig. 8-21 8-4 Reflected Cyclic Code for Six Numbers
Fig. 8-22 8-4
Fig. 8-23 8-5 Binary 8-Section Encoder
Fig. 8-24 8-5 Typical 8-Section Encoder
Fig. 8-25 8-5 Single-Output Incremental Encoder
Fig. 8-26 8-6 Two-Output Incremental Encoder
Fig. 8-27 (a-j) 8-6 Motor Direction Detection System Design (Copy of Fig. 6-4)
Fig. 8-28 8-6 Simplified Block Diagram of a Closed-Loop NC System
Fig. 8-29 8-6 Block Diagram of Open-Loop NC System
Fig. 8-30 (a-c) 8-7 Adder for 2-Bit Numbers
Fig. 8-31 8-7 Iterative Adder Block Diagram
Fig. 8-32 (a-c) 8-7 Iterative Binary Adder Design
Fig. 8-33 (a-g) 8-8 Iterative Parity Checker
Fig. 8-34 (a-f) 8-8 Iterative 2 Out of n Checker
Fig. 8-35 (a-g) 8-9 Iterative Binary Numbers Comparator
Fig. 8-36 8-10 Comparison Between Natural-Binary & Reflected Cyclic Code
Fig. 8-37 8-10 Iterative Circuit for Translating Natural-to-Reflected Cyclic Code
Fig. 8-38 8-10 Iterative Circuit for Translating Reflected Cyclic to Natural
Fig. 8-39 8-10 Truth Table for Translating Natural-to-Reflected Cyclic Code
CHAPTER 9 Semi-Flexible Automation
Hardware Programmers
Fig. 9-1 9-1 Drum Programmer
Fig. 9-2 9-2 Drum Programmer Solution
Fig. 9-3 (a-b) 9-2 Patch Board & Matrix Board
Fig. 9-4 (a-b) 9-2
Fig. 9-5 9-2 Schematic Representation of Programmable Counter
Fig. 9-6 9-2 Programmable Counter With a Single-Cycle Start Mode
Fig. 9-7 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs
Fig. 9-8 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs
Fig. 9-13 (a-e) 9-4 2/n Stability Cases
Fig. 9-14 9-5 1/n Code Programmer for Two Simultaneous Parallel Paths
Fig. 9-15 9-5 1/n Code Programmer for Two Alternative Parallel Paths
Fig. 9-16 9-5 1/n Code Programmer With Skipped Steps Option
Fig. 9-17 9-5 1/n Code Programmer With Repeated Steps Option
Fig. 9-18 9-6 Flow Chart for Selecting System Design Method
CHAPTER 10 Flexible Automation

Programmable Controller
Fig. 10-1 10-1 Block Diagram of Programmable Controller (PLC)
Fig. 10-2 10-1 PLC Classifications According to Size
Fig. 10-3 10-1 Discrete Input Devices to PLC
Fig. 10-4 10-1 Discrete Output Devices Actuated by PLC
Fig. 10-5 10-1 Standard Discrete I/O Interface Modules
Fig. 10-6 10-1 Type of Electronic Memories
Fig. 10-7 10-1 I/O Connection Diagram
Fig. 10-8 (a-b) 10-1 PLC- Different I/O Connections Locations
Fig. 10-9 10-2 Typical PLC Memory Map
Fig. 10-10 10-2 PLC Programming Languages
Fig. 10-11 10-2 Ladder Diagram Section Appearing on Screen
Fig. 10-12 10-3 PLC Configuration
Fig. 10-13 10-3 Typical PLC Control System
Fig. 10-14 10-3 PLC Network (Macro)
Fig. 10-15 (a-e) 10-4 PLC I/O Variables Assignment
Fig. 10-16 (a-g) 10-4 PLC Motor Control System
Fig. 10-17 10-5 Forward/Reverse Circuit
Fig. 10-18 10-5 Example of Ladder Diagram Segment
Fig. 10-19 10-5 I/O Assignment for Fig. 10-18
Fig. 10-20 10-5 Ladder Diagram of Fig. 10-18 in PLC Format
Fig. 10-22 10-5 Use of LIFO Memory Stack
Fig. 10-24 (a-f) 10-6 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-)
Fig. 10-25 (a-b) 10-7 Multiple Use of LIFO Stack
Fig. 10-26 (a-b) 10-7 Rearrangement of Ladder-Diagram to Simplify Program
Fig. 10-27 (a-b) 10-7 Timer Set for 20 Sec
Fig. 10-29 (a-b) 10-7 Counter Set to Count to 25
Fig. 10-31 (a-b) 10-7 PLC Light-Flash Program
Fig. 10-32 (a-c) 10-7 PLC Up/Down Counter Program
Fig. 10-33 10-8 Two-Hand Safety Circuit Using PLC
Fig. 10-34 (a-b) 10-8 PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.D-
Fig. 10-35 (a-c) 10-8 Ladder Diagram and Program for sequence of Fig. 10-34
Fig. 10-36 (a-d) 10-9 Timers and Counters
Fig. 10-37 (a-c) 10-9
Fig. 10-38 (a-c) 10-10 Master-Control-Relay Command (MCR)
Fig. 10-39 (a-c) 10-10 Jump Command (JMP)
Fig. 10-40 (a-d) 10-10
Fig. 10-41 (a-c) 10-10 Equivalent PLC and Relay Circuits
Fig. 10-42 10-11 Effect of Scanning Action on Internal States of Relays
Fig. 10-43 (a-b) 10-11 Importance of Proper Rung Order
Fig. 10-44 10-11 Trigger Flip-Flop Circuit for PLC
Fig. 10-45 10-11 PLC Sequence Chart for Fig. 10-44
Fig. 10-46 10-11 Analog Input Devices for PLC
Fig. 10-47 10-11 Standard Analog-Input Interface Modules
Fig. 10-48 10-11 Analog Output Devices Actuated by PLC
Fig. 10-49 10-12 Standard Analog-Output Interface Modules
Fig. 10-50 10-12 Storing an Analog Input Value
Fig. 10-51 10-12
Fig. 10-52 10-12 Transferring a Word to Analog Output Module
Fig. 10-53 10-12
Fig. 10-54 10-12
Fig. 10-55 10-13
Fig. 10-56 10-13
Fig. 10-57 10-13 Logic Operations
Fig. 10-58 10-13 Data Commands
Fig. 10-59 10-13 PLC Micro/Macro Definition
Fig. 10-60 10-13 Several Possible LAN Topologies
Fig. 10-61 (a-f) 10-14 PLC Design of Thickness Detector System
Fig. 10-62 (a-e) 10-14 PLC Design of Traffic Light Control System
Fig. 10-63 (a-l) 10-15 PLC Design of Alarm System
Fig. 10-64 (a-e) 10-16 PLC Design of Motor Direction Detector System
Fig. 10-65 (a-i) 10-17 Combination Lock System
CHAPTER 11 Introduction to Assembly
Automation
Fig. 11-1 11-1 Bladed Wheel Hopper Feeder
Fig. 11-2 11-1 Central Board Hopper Feeder
Fig. 11-3 (a-c) 11-1 Shape of Centerboard Slot
Fig. 11-4 11-1 Rotary Centerboard Hopper Feeder
Fig. 11-5 11-1 Design Sheet for Reciprocating Tube Hooper Feeder
Fig. 11-6 11-1 Revolving Hook Hopper Feeder
Fig. 11-7 11-2 Design Sheet for Tumbling
Fig. 11-8 11-2 Magnetic-Disk Hopper Feeder
Fig. 11-9 11-2 Vibratory Bowl Feeder
Fig. 11-10 11-2 Design Sheet for Vibratory Bowl Feeder
Fig. 11-11 11-2 Disk Feeder
Fig. 11-12 11-2 Slide Escapement
CHAPTER 12 Robotics and Numerical Control

Fig. 12-1 (a-b) 12-1 Cartesian Robot and Coordinate System
Fig. 12-2 12-1 Cylinde Robot and Coordinate System
Fig. 12-3 12-1 Spherical Robot and Coordinate System
Fig. 12-4 12-1 Articulated Robot and Coordinate System
Fig. 12-5 12-1 Robot Work Envelope
Fig. 12-6 12-1 RCC Device
CHAPTER 13 Simester Exams

13-1 Simester Exam Example - Questions
13-3 Simester Exam Example Responses
13-7 Typical Simester Exam Questions - Questions
CHAPTER 7
PNEUMATIC
CONTROL CIRCUITS
Pneumatic Cascade Design

Pneumatic Flow Table Design
Valves Function Tables
Emergency Stop Modes
7-1
CYLINDER "A" CYLINDER "B" CYLINDER "A" CYLINDER "B"
+
a1 a2 b1 b2 a1 a2 b1 b2
+
-
-
A- + -
A+ B- + -
B+ A- + -
A+ B- + -
B+
START START
START (A+) Conflicts With A- Actuation (by b1)

Fig. 7-1 : Intuitive Design for More Conflicting States
Sequence Start , A+,B+,A-,B- Fig. 7-2 : Sequence Start , A+,B+,B-,A-
CYLINDER "B" CYLINDER "C"

CYLINDER "A" b1 b2 c1 c2
a1 a2
-
+
-
+
A- A+ B- + -
B+ C- + -
C+
+ -
I
II
1 + -
2
Start , A+ , B+ , B- , A- , C+ , C-
I II I
b. Cascade Circuit
a. Cascade Groups Partitioning
Fig. 7-3 : Cascade Design for Sequence Start , A+,B+,B-,A-,C+,C-
CYLINDER "A"
a1 a2
+
A- + -
A+
I
.....
+
II
III
IV
+ -
2
+ -
3 Fig. 7-5: Multiple Limit Valves Replacement
1 - +
4
Fig. 7-4 : Cascade System for Sequence Start , A+,A-,A+,A- (Cascade)

Pure pneumatic control system 7-2
Simplicity and realiability
Limited to control cylinders with actuation valves that satisfy the following restrictions :
* Valves do not have return springs
* Valves are operated pneumatically (no solenoids)
Group Partitioning differences between pneumatic and relays cascade are :
* There is always an active group, even when not operating
(START is also included within a group)
* Last Group may be merged with first group, provided that groups do not conflict
Fig. 7-6 : Pneumatic Cascade Basic Concept
I
II
2 GROUPS
1 + -
2
a. 2-Groups Manifold Lines Configuration
I
II
III
+ -
2
3 GROUPS
1 + -
3
b. 3-Groups Manifold Lines Configuration
I
II
III
IV
+ -
2
3
+ -
4 GROUPS
1 - +
4
c. 4-Groups Manifold Lines Configuration
Fig. 7-7 : Pneumatic Cascade Group Configurations

7-3
ORIGINAL SEQUENCE SEQUENCE GROUPS
B+ B+ B- B+ B+ B-
START, A+, , B-, , START, A+, , B-, ,
C+ A- C- C+ A- C-
I II III IV
a. Process Sequence Definition
b. Sequence Groups Partioning
1. cylinder actuated by valves without return springs. 1. cylinder actuated by valves without return springs.
2. A set of two limit valves. 2. Two sets of two limit valves.
3. A two-input OR gate for each valve control.
CYLINDER "A"
a1 a2
+
CYLINDER "B"
b1 b2
A- A+
-
+ -
B- + -
B+
c. Single-Cycle Cylinder Requirement
d. Two-Cycle Cylinder Requirement
1. System consists of 3 cylinders, each equipped with limit-valves

2. Cylinders "A" and "C" perform single cycle (each), and require a single set of limit valves.
3. Cylinder "B" performs two cycles, and requires two sets of limit-valves, and OR valves.
4. A START valve is also required.
CYLINDER "A" CYLINDER "B" CYLINDER "C"

a1 a2 c1 c2
b1 b2
+
+
-
A- + -
A+ B- + -
B+ C- + -
C+
START
e. System Cylinders Requirements
Fig. 7-8 : Pneumatic Cascade Design Process Steps

7-4
a1 a2 c1 c2
b1 b2
+
-
-
A- + -
A+ B- + -
B+ C- + -
C+
START
I
II
III
IV
+ -
2
B+ B+ B-
3
+ -
START, A+, , B-, ,
C+ A- C-
1 - +
4
I II III IV
f. System Components

a1 a2 c1 c2
b1 b2
+
+
-
-
A- + -
A+ B- + -
B+ C- + -
C+
START
I
II
III
IV
2
+ -
3
+ -
1 4
- +
g. Complete System
Fig. 7-8 : Pneumatic Cascade Design Process Steps (Cont'd)

A+ C+ D- A+ C+ D-
7-5
START , , B- , A- , , START , , B- , A- , ,
B+ D+ C- B+ D+ C-
I II I
CYLINDER "A" CYLINDER "B" CYLINDER "C" CYLINDER "D"

a1 a2 c1 c2 d1 d2
b1 b2
+
+
-
-
A- + -
A+ B- + -
B+ C- + -
C+ D- + -
D+
START
I
II
2 + -
1
Fig. 7-9 : Pneumatic Cascade Example 1

(from semester exam September 2002)
A- B- A- B-
START, A+, B+, , START, A+, B+, ,
C+ C- C+ C-
I II III

a1 a2 c1 c2
b1 b2
+
+
-
A- + -
A+ B- + -
B+ C- + -
C+
START
II
III
+ -
2
1 + -
3
Fig. 7-10 : Pneumatic Cascade Example 2

(from semester exam July 2002)
y y'
7-6
R - +
S c2.y1.y2.y3 c2.y1.y2.y3'
R3 - +
S3
c2.y1.y2 c2.y1.y2'
a. Flip-Flop Valve c2.y1.y2'
R2 - +
S2
R2 - +
S2
c2.y c2.y' c2.y1'
c2.y1'
R - +
S R1 - +
S1
R1 - +
S1
c2 c2
b. Steering Valve c2
Fig. 7-12 : Two Steering Fig. 7-13 : Three Steering
Fig. 7-11 : Flip-Flop Valve Valves providing 3 Valves providing 4
and Steering Valve addresses addresses
START,A+,A-,A+,A-,A+,A-
A+
a. Process sequence START,A+,B+,A-,B-, ,A-,B-
B+
a. Process sequence
a1.b1 a2.b1 a2.b2 a1.b2 A+ A- B + B-

a1 a2 A+ A- a1 a2 A+ A- y1' 1 1
1 1 y1' 1 R 3 1
1 R2 1
2 1 y3' 2 S1
R2
1
y2' 3 R3 1
S3
3 1 y1.y2' 3 R4 1
y3' 4 S1 1
4 1 y3.y4' 4 S2 1
y1 5 s2 1 1
5 1 y1.y2 5 S4 1 y2 6 S3 1
6 1 y3.y4 6 R1 1 y3 7 R 1 1
b. Flow Table c. Complete Flow Table b. Complete Flow Table
S1= a2.y3' S2 = a2.y3.y4' S3 = a1.y1.y2' S4 = a1.y1.y2 S1 = a1.b2.y3' S2 = a1.b1.y1 S3 = a2.b2.y2

R1 = a2.y3.y4 R2 = a2.y3' R3 = a1.y1' R4 = a1.y1.y2' R1 = a1.b2.y3 R2 = a2.b1 R3 = a2.b2.y2'
A+ = a1.b1.y1'.Start+a1.b1.y1 = a1.b1.Start+a1.b1.y1
A+ = a1.y1'.Start+a1.y1.y2'+a1.y1.y2 = a1.y1'.Start+a1.y1
A- = a2.b2.y2'+a2.b2.y2 = a2.b2
A- = a2.y3'+a2.y3.y4'+a2.y3.y4 = a2.y3'+a2.y3 = a2
B+ = a2.b1+a1.b1.y1
d. Exitation and Output Functions B- = a1.b2.y3'+a1.b2.y3 = a1.b2
c. Exitation and Output Functions

a1.y1.y2 a1.y1.y2'
S4 S3 a2.y3.y4
R1 a2.y3.y4'
R4 S2
R2 - +
S2 R4 - +
S4 A+
A+ B+
a1.y1 a2.y3 S3 R3 R1 S1
START S1 a2.b2.y2 a2.b2.y2'
R3 a1.y1' a2.y3' a1.b1.y1 a1.b1.y1' a1.b2.y3 a1.b2.y3'
R2 S2
R1 - +
S1 R3 - +
S3 R1 - +
S1 R2 - +
S2 R3 - +
S3
R2
A- (a2.b1) (a1.b1) A- a2.b2 B- a1.b2
a1 a2
e. Control Circuit a1 - +
a2 a2 +
a1 +
b2 b2
b1
Fig. 7-14 : Pneumatic Flow-Table Design for d. Control Circuit
sequences START,A+,A-,A+,A-,A+,A-
Fig. 7-15 : Pneumatic Flow-Table Design for

A+
Sequence START,A+,B+,A-,B-, ,A-,B-
B+
START,A+,B+,B-,C+,B+,B-,C-,A-
7-7
a. Process sequence
a1.b1.c1 a2.b1.c1 a2.b2.c1 a2.b1.c2 a2.b2.c2

A+ A- B+ B- C+ C-
(a1) (b2.c1) (b1.c2) (b2.c2)
1 R1 1
y1' 2 1
S1 1
3 R2
y1.y2' 4 R3 1
y3' 5 1
6 S3 1
y3 7 S2 1
y1.y2 8 1
b. Complete Flow Table
a1 a2
a1 b1 c1 a1 S1 = b2.c1 S2 = b1.c2.y3 S3 = b2.c2
c1 X X X a2 b2 c1 b2 a1 R1 = a1 R2 = b2.c1 R3 = a2.b1.c1.y1.y2'
c2 X X a2 b1 c2 b1 c2
a2 b2 c2 b2 c2
b1 b2 b1 A+ = a1.START A- = a2.b1.c1.y1.y2
c. Simplifiying Input Map B+ = a2.b1.c1.y1'+b1.c2.y3' B- = b2.c1+b2.c2 = (b2)
C+ = a2.b1.c1.y1.y2' C- = b1.c2.y3
d. Exitation and Output Functions
S2 C- B+ A- R3 C+ S3 S1 R2 B- A+ R1
a2.b1.c1.y1.y2 a2.b1.c1.y1.y2'
R2 - +
S2
b1.c2.y3 b1.c2.y3' a2.b1.c1.y1'
R3 - +
S3 S1 - +
R1
(b1.c2) (b1.c1) a2.b1.c1 (b2.c2) (b2.c1)
c1 - + c2
c1 - +
c2 +
a2 a1
b1 b2
e. Control Circuit
Fig. 7-16 : Pneumatic Flow-Table Design for Sequence START,A+,B+,B-,C+,B+,B-,C-,A-

a1 a2 a1 a2 a1 b1 c1 d1 e1 a1 7-8
c1 c1
X X X X a1 b1 c1 d1 e2 a1 e2
d1 d1
X a2 b1 c1 d1 e2 a2 b1 c1 d1
c2 c2
d2
a2 b2 c1 d1 e2 b2
d2
c1 c1
X a2 b1 c2 d1 e2 c2
b1 b2 b1 b1 b2 b1
a2 b1 c1 d2 e2 d2
e1 e2
Fig. 7-17 : Simplifiying Input Map for Sequence

START,E+,A+,B+,B-,C+,C-,B+,B-,D+,D-,A-,E-
a1 a2 a3 a4
-
a. Cylinder Type
START,A+,(a4),A-,A+(a3),A-,A+,(a2),A-
b. Required Sequence
a1 a2 a3 a4 A+ A-
R3
y1' 1 1
R4
y3' 1 P
y4' 3 P
S1
4 R2 1
y4' 5 P
y3' 6 P
y1.y2' 7 S4 1
y3' 8 P
y4 9 S2 1
y3' 10 P
y1.y2 11 S3 1
y3 12 R 1 1
c. Simplified Flow-Table
S1 = a4 S2 = a3.y4 S3 = a1.y1.y2 S4 = a1.y1.y2'

R1 = a2.y3 R2 = a4 R3 = a1.y1' R4 = a1.y1'
A+ = a1.y1'.START+a2.y1 = A- = a4+a3.y4+a2.y3
= a1.START+a2.y1
d. System Functions
Fig. 7-18 : Design a Sequence With Passive States

Efficient Use of Directional-Control T T
Valves in Fluid-Logic Circuits P + S + - R

A+B AB
2 3 2 3
Various types of directional-control valves have been systematically analized
3/2 Valve Gate 3/2 Valve Flip-Flop
B + -
to determine the logic output functions obtained for different input-signal
combinations. It was found that a surprisingly large variety of fairly complex
T1 T2 T1 T2
1 A 0 logic functions can be obtained with a single valve.The results are summarised
in five tables which include 186 (i.e. all the significant) input-signal combinations. P + S + - R
Several examples are presented, illustrating how the tables can be used to
implement given fluid-logic functions with a minimum number of valves. 2 3 4 2 3 4
A.B' A+B'
It thus becomes possible to exploit the logic capacity of these valves to their 5/2 Valve Gate 5/2 Valve Flip-Flop
fullest extent, which can result in considerable reduction in the number of valves.
B + -
P + . ..
D.W. Pessen P1 P2
0 A 1 Associate Professor
Dept of Mechanical Engineering, 2 3 4 5 2 3 4
Technion - Israel Institute of Technology, 6/2 Valve Gate 5/3 Valve Gate
Haifa, Israel
Note : Use of shuttle valves is uaually less expensive.

AC+BC' AC'+BC Mem ASME a. Valves Pins Assignment
Fig. 7-20 : Function Tables Background

C + -
T
A B A
P +
2 3
Fig. 7-19 : Examples of
Complex Functions Line Function Boolean
No. Name Function P 2 3
a. 3/2 Valve , Single Output Function 1 YES T=A A 1 0
2 NOT T = A' A 0 1
b. Two Separate Output Function, 3 AND T = AB B A 0
2 Input Variables
4 AND T = AB B A B
1 YES
2 NOT
c. Two Separate Output Function, 5 OR T = A+B B 1 A
3 Input Variables 6 OR T = A+B B B A
3 AND
d. Two Separate Output Function, 7 INHIBITION T = AB' B 0 A
4 OR
5 INHIBITION 4/5 Input Variables 8 IMPLICATION T = A+B' B A 1
9 SELECTOR T = AC+AC' C A B
6 IMPLICATION e. Two Separate Flip-Flop Output
7 SELECTOR Function b. 3/2 Valve Connections yielding Single
Output Function
a. Function Search Order b. Tables List
7-9
Fig. 7-22 : 3/2 Valve Connections
Fig. 7-21 : Function Tables Arangement yielding Single Output Function
and Valves Pins Assignment
7-10
7-11
No. FUNCTION NAME BOOLEAN BOOLEAN Valve 5/2 Valve 6/2 Valve 5/3
FUNCTION 1 FUNCTION 2 P234 P2345 P1 P2 2 3 4
59 YES/SELECTOR T2=C CAB10

60 NOT/SELECTOR CAB01
61 AND/OR T2=AB T1=B+C BABC
66 AND/AND T2=AC T1=BC CA0B0
70 AND/INHIBITION T2=AC T1=BC CA0B
73 AND/IMPLICATION T2=AC CA0B1
75 AND/SELECTOR T2=BC CAB0
79 AND/SELECTOR T2=AC CABA0
81 OR/OR T2=B+C T1=A+C C1B1A
84 OR/OR T2=B+C T1=A+C CCBCA
85 OR/INHIBITION T2=B+C C1B0A
86 OR/INHIBITION T2=B+C CCB0A
87 OR/IMPLICATION T2=A+C CB1A
90 OR/SELECTOR T2=A+C C1AB
91 OR/SELECTOR T2=A+C CCAB
94 OR/SELECTOR T2=B+C C1BAB
95 OR/SELECTOR T2=B+C CCBAB
96 INHIBITION/INHIBITION C0A0B
97 INHIBITION/INHIBITION B C 0 A 0
99 INHIBITION/IIMPLICATION C0AB1
100 INHIBITION/IIMPLICATION B C 0 A 1
101 INHIBITION/SELECTOR C0AB
103 INHIBITION/SELECTOR C0BAB
104 IMPLICATION/IMPLICATION CA1B1
105 IMPLICATION/IMPLICATION C BC1A1
107 IMPLICATION/SELECTOR CAB1
109 IMPLICATION/SELECTOR CABA1
110 SELECTOR/SELECTOR CABA
112 AND+AND/AND+AND T2=AB+AC T1=AC+BC C A A B C

113 AND+AND/AND+ T2=AB+AC T1=A+BC C A A B A
114 AND+AND/INHIBITION T2=AB+AC C A A B 0
115 AND+AND/IMPLICATION T2=AB+AC C A A B 1
117 AND+INHIBITION/AND+INHIBITION B C A 0 A
118 AND+INHIBITION/INHIBITION+ B C A B A
119 AND+INHIBITION/OR T1=B+C B C A B C
120 AND+INHIBITION/AND T1=BC B C A 0 B
121 AND+INHIBITION/INHIBITION B C A B 0
122 AND+INHIBITION/IMPLICATION B C A 0 1
127 AND+/AND+ T2=A+BC T1=C+AB A C A B C
128 AND+/INHIBITION T2=A+BC A C A B 0
129 AND+/IMPLICATION T2=A+BC A C A B 1
131 INHIBITION+/INHIBITION+ T2= C B A 1 A
132 INHIBITION+/OR T1=B+C C B A 1 B
133 INHIBITION+/AND T1=BC C B A B C
134 INHIBITION+/INHIBITIOM C B A 1 0
135 INHIBITION+/IMPLICATION C B A B 1
Fig 7-24 : Valve Connections Yielding 2 Separate

Output Functions, 3 Variables
7-12
7-13
3/2 Valve 5/2 Valve

No. Output 1 Output 2 2 3 2 3 4
No Input Variables
161 T=y 1 0
162 T2=y 0 1 0
163 T1=y 1 0 1
One Input Variables

164 T=Ay A 0
165 0 A
166 T2=Ay 0 A 0
167 T1=Ay A 0 A
168 T1=Ay A 0 1
169 T1=y 1 0 A
170 A 1
171 T=A+y 1 A
172 T1=A+y 1 A 1
173 T2=A+y A 1 A
174 T2=y A 1 0
175 T2=A+y 0 1 A
176 0 A 1
177 T1=A+y T2=Ay 1 A 0
Two Input Variables

178 T1=Ay A 0 B
179 T2=B+y A 1 B
180 A B
181 T2=By A B 0
182 A B 1
183 0 A B
184 T1=A+y 1 A B
185 A B A
Three Input Variables

186 A B C
Fig. 7-26 : Valve Connections Yielding Flip-Flop

Output Functions
Required Functions 7-14
F1 = X1.X2'
Start
F2 = X1.X2 + X2'.X3
a1 CONTROL A+
F1 is Inhibition Function SYSTEM
F2 is Selector Function a2
Search in 3-variables table

Found Functions 101 and 103
Only 101 satisfies requirements Y1 S1
Y S
1 R1
Y' R
F1 = X1.X2' F2 = X1.X2 + X2'.X3
Y2 S2
Y S
2
R2
Y' R
X2 + -
1 X1 X3
d. System Solution Block Diagram
Fig. 7-27 : Example 1 (Huffman Method Realization)
START,A+,A-,A+,A-
* Start , a1, a2 are external signals
a. Process Sequence
* y1 ,y2 are outputs of internal flip-flops
Start * S1,R1,S2,R2 are Set/Reset of those flip-flops
CONTROL
a1 SYSTEM A+
* Functions that contain only external variables
a2 are to be searched in first 4 tables
* Function that contain internal variables (y)

b. System Block Diagram are to be searchedfirst in fifth table
* In current system, all functions contain internal

variables, so they are to be searched in fifth table
S1=Start.a1.y2' R1=a1.y2
S2=a2.y1 r2=a2.y1'
e. Design Considerations
A+ = y1.y2'+y1'.y2
A- = a2
C. Huffman Method Solution
A+
y1.y2'+y1'.y2 Start.a1.y2'
R2 S2
S1
a1.y2' a2.y1' a2.y1

S2 - + R2
a1.y2
180 y1' y1 R1 S1 - +
R1
S1 - +
R1 S2 - +
R2 166
A-
162 166
a1 a2
f. System Valve Circuit

START,A+,B+,B-,A-,B+,B- 7-15
a. Process Sequence
1
a1b1 a2b1 a2b2 a1b2 A+ A- B+ B-
1 2 - - 1 0 0 - 6 2
- 2 3 - - 0 1 0
- 4 3 - - 0 0 1
5 4 - - 0 1 0 - 3
5
5 - - 6 0 - 1 0
4
1 - - 6 0 - 0 1
c. Merge Diagram
b. Primitive Flow Table
b1 b2 b1 b2 b1 b2
y
{1,2,6} {3,4,5} 0 1 2 3 6
0 0 0 1 0 0 - - 0 -
d. Selected Option 1 4 3 6 1 - - - 0 1 0 0 0 1
5
a1 a2 a1 a1 a2 a1 a1 a2 a1
e. Merged Flow Table & S = a2.b2 R = a1.b2

States Assignment f. Exitation Functions
b1 b2 b1 b2 b1 b2 b1 b2
y
0 0 0 0
1 - 0 0 0 0 0 - 0 1 - 0 - 0 - 1
1 0 0 - 0 1
- 1 0 - 1 1 0 0 - 1 0 - 1 -
a1 a2 a1 a1 a2 a1 a1 a2 a1 a1 a2 a1
A+ = Start.b1.y' A- = b1.y B+ = a2.y'+a1.y B- = b2

g. Output Functions
A+
B- B+ A-
a2.y'+a1.y
b1.y b1.y'
180
R + -
S R - +
S
166 b1
a2 c1
166 (a1.b2) (a2.b2)
a2 - + a1
b2 h. System Valve Circuit
Fig. 7-29 : Solution for Sequence START,A+,B+,B-,A-,B+,B-

7-16
EMERGENCY STOP STOP
Stop process due to emergency condition RESTART

Easy accessible buttons
Safety continuation Restart (Continue) STOP CONTINUE
Different modes
Add-on CONTINUE
RESTART
a. Target & Definition b. Single STOP-RESTART c. Separate STOP/RESTART buttons
button
Fig. 7-30 : STOP-RESTART Single/Separate Buttons
STOP STOP STOP RESTART STOP

CR1
STOP
STOP
-
RESTART
cr1
+
cr1
CONTINUE
CONTINUE
Fig. 7-32 : Electric STOP-RESTART
System With Multiple Remote-Control
Fig. 7-31 : STOP-RESTART With Multiple STOP Buttons
Remote-Control STOP Buttons
No Change C
C
Cylinder at rest must remain at rest.
Cylinder in motion must complete its stroke, and
remain at rest.
+
To limit To limit
No Motion valves valves

Cylinder in motion must be disconnected from pressure
and move until stopped by friction (or end stroke).
a. No-Change Mode b. No-Change Mode
Lock Piston Pneumatic Actuation Electric Actuation
Cylinder in motion must be locked at its current position.
C C
Safety Position
Cylinder must be moved to its either (+) or (-) position,
which been pre-definrd as "Safety Position".
+
To cylinder To cylinder
No-Change/No-Motion valves valves
Combination of No-Change and No-Motion modes.
No-Change/Lock-Piston
c. No-Motion Mode d. No-Motion Mode
Combination of No-Change and Lock-Piston modes. Pneumatic Actuation Electric Actuation
No-Change/Safety-Position
Combination of No-Change and Safety-Position modes. Fig. 7-34 : No-Change & No-Motion
Circuits
Fig. 7-33 : Emergency Stop Modes Definition

7-17
Cylinder "A"
Cylinder "A"
-
+
-
+ + A- - +
A+
C
C a1+a2
A- - +
A+
a1 a2
Fig. 7-35 : "Lock-Piston" Mode Circuit

Fig. 7-38 : "No-Change/No-Motion" Mode
Circuit
Cylinder "A"
A+ A-
0 0 1 0 1 0 1 1
+
C C - - 0 1 0 0 1 0
A- A+ a2 a2
VA- VA+ - - - - - - - -
+
- +
a1 a1
0 0 1 0 - 0 1 -
C C
VA+ = C(A+) VA- = C(A-)+C'.a2'
Fig. 7-36 : "Safety-Position" Mode Circuit

(Applied to an Individual Cylinder) Fig. 7-39 : Karnaugh Maps for
"No-Change/Safety-Position"Circuit
Cylinder "A" Cylinder "A"
from control
+
+
-
circuit
C C
VA- VA+=A+ A- VA- VA+ A+

+
- +
A+ a2'
- +
from control
circuit
A-
one valve
per
cylinder To all shuttle valves
Fig. 7-40 : "No-Change/Safety-Position" Mode Circuit
C air supply to
C'
control
circuit
C +
continue
cycle
one valve for the
whole system
Fig. 7-37 : "Safety-Position" Mode Circuit

(Applied to Entire System)
CHAPTER 8
SWITCHING ELEMENTS
AND
SYSTEMS
Timers
Flip-Flops (FF)
FF Implemntation for Binary Counters
FF Implemntation for Shift Registers
Endocers
Iterative Circuits
Binary Codes
Output
Control Control
Control Bias Pressure (from
Volume + -
pressure regulator)
Delay A Signal
Delay Delay B
Output
Output
a. On-Delay e. On-Delat Off-Delay
irrelevant
Fig. 8-5 : Pneumatic "On-Delay" Timer Using Bias Pressure
Control Control
Delay Delay A Delay B A

Output Output
START
b. Off-Delay f. Delayed Interval
-
irrelevant
Control Control A- + -
A+
Delay A Delay B
Delay
Output Output
c. Interval g. Monitored Delayed Interval
Volume +
Control Control
Delay Output
Output
h. Repeat Cycle Fig. 8-6 : "On-Delay" Timer for
d. Monitored Interval
Automatic Cylinder Retraction
Fig. 8-1 : Sequence Chart of Common Timer Modes
1 1
Input 0 Input 0
(Output)' Output 1 1
Needle Output Output

0 0
Valve b. Pulse Stretching
Control Volume + a. Pulse Shorening
Signal
Check Valve Fig. 8-7 : Sequence Chart for a Pulse Shaper (Monostable, One-Shot)
Fig. 8-2 : Pneumatic "On-Delay" Timer
START
(Output)' Output
Y1
y1
Control Volume + Y2
Signal
y1 y2
Output
Fig. 8-3 : Pneumatic "Off-Delay" Timer

Fig. 8-8 : Relay Pulse Shaper
(Output)' Output
Output
Control
Signal
Volume +
Control Volume +
Signal
8-1
Fig. 8-4 : Pneumatic "On-Delay Off-Delay" Timer
Fig. 8-9 : Pneumatic Pulse Shaper
8-2
1
S (SET)
2 S (Set) 3 2
3
1
Q S Q 2
3
1
Q
Clock
2
1
R Q' 1
2
1
R (RESET)
3 Q' 2
3 3 Q'
R (Reset)
a. Logic Circuit b. Short Symbol c. Clocked SR Flip-Flop
Fig. 8-10 : Basic Set-Reset Flip-Flop (SR)
1 1
1 2
3
S Q 2
3
S Q Q
2
3
S Q Q T
T 1
3
1
3
Q'
1 2 R Q' 2 R Q'
2
3
R Q' Q'
a. Basic Logic Circuit b. Master-Slave Type
Fig. 8-11 : Toggle Flip-Flop (T)
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
FF3 FF2 FF1 FF0 FF3 FF2 FF1 FF0
Q Q Q Q Q Q Q Q
T T T T CLOCK T T T T CLOCK
Q' Q' Q' Q' Q' Q' Q' Q'
a. "UP" Counter c. "DOWN" Counter

UP
1
3
2
Q0 1
Q
3
T 2 T
1
Q1 3
2
Q'
Q2
DOWN
Q3 RESET
Q3 : 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 ...
Q2 : 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ...
Q1 : 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ... b. "UP" Counter Timing Waveforms d. "UP/DOWN" Selector
Q0 : 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...
Fig. 8-12 : T Flip-Flop Implementation - Counters
D 1
3
1
3
Q
2 S Q 2 S Q
D 1
3
Q CP
2 S Q 1 1
3
R Q'
3
R Q' Q'
CP 1
2 2
2
3
R Q' Q'
a. Delay Flip-Flop (D)

b. Master-Slave Type
IN OUT
D Q D Q D Q D Q D Q D Q D Q
CP
CP Q' CP Q' CP Q' CP Q' CP Q' CP Q' CP Q'
c. Shift Registerr Based on D Flip-Flops
Fig. 8-13 : D Flip-Flop Implementation - Shift Register

8-3
Input x 1 0 0 1 1 0 1 1 0 1
Shift
Fig. 8-14 : 10 Stages Shift Register
X1 0 0 1 0 1 1 0 1 0 0
X2 1 1 0 1 0 0 1 0 1 1
Inputs
X3 1 0 0 0 0 1 1 0 1 0
X4 1 0 1 1 0 1 0 0 1 0
Shift
Fig. 8-15 : Shift Register With Four Parallel Tracks
Output
Voltage
HI (3.4V)
LO (0.3V)
Input
Voltage
0.95V 1.8V
Fig. 8-17 : Schmitt-Trigger Response
to Fuzzy Waveform
Fig. 8-16 : Schmitt-Trigger Response
Weight
8 4 2 1 P P = Parity Bit
Number
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
Fig. 8-18 : Truth Table for an Error Checking BCD Code

(Even Parity Check)
Weight
7 4 2 1 P P = Parity Bit 8-4
Number
0 1 1 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 1 0 0 0 1
8 1 0 0 1 0
9 1 0 1 0 0
Fig. 8-19 : Truth Table for 2-out-of-5 Code

(Even Parity Check)
C
B B B
B
A
A A A
C C C D
(a) (b) (c) (d)
Fig. 8-20 : Use of Karnaugh Map to Obtain Cyclic Codes
1 1 1 1
1 1 1 0 1 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 1
1 0 0 1 0 0 1
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 0 1 1
Fig. 8-21 : Reflected Cyclic Code for 6 Numbers
0 0 1 1
0 0 1 0
0 0 0 0
0 0 0 1
0 1 0 1
0 1 0 0
1 0 1 1 0
1 0 1 1 1
0 0 1 1 1
0 0 1 1 0
Fig. 8-22 : Construction of "Reflected" Cyckic Code
A H 8-5
000 111
B G
001 110
100 E WRONG
110 G OK
101 F OK
C F 111 H WRONG
010 101 c. Sections Border Problem
011 100
D E
b. Encoder Photo-Cells a. Encoder Plate
Fig. 8-23 : Binary 8-Sections Encoder

Absolute Coordinates
A H
011 111
B G
110
010
110 G OK
100 F OK
C F
000 100
c. Border Problem Solved
001 101
D E
Fig. 8-24 : Typical 8-Sections Encoder

Absolute Coordinates
c. Incremental Encoder Output

No Sense for Direction
Fig. 8-25 :Single Output Incremental Encoder

B
A
8-6
1
8 2
a. Disk Sensors Arrangement
Change 0 7 3
Direction 360
0
90
6 4
A
5
B d. Merge Diagram
"UP" direction "DOWN" direction
(A leads B) (B leads A)
AB
00 01 11 10
b. Encoder Code Waveforms for Both Directions
CR1 1 5 8 2
Fig. 8-26 : Two Output Incremental Encoder
CR2 6 5 3 2
CR3 6 4 3 7
CONTROL
A D 1
B SYSTEM CR4 4 8 7
a. Control System Block Diagram e. Merged Flow-table & State Assignment
AB
00 01 11 10
CR1 O 1 (1) (0)

01/1 00/1 10/1 11/1
5 6 7 8 CR2 1 (1) (0) O
CR3 (1) (0) O 1
00/0 10/0 11/0 01/0 CR4 (0) O 1 (1)
1 2 3 4
D
f. Output Table
b. Primitive Flow-diagram
S1 = CR4.A.B' + CR2.A'B' R1 = CR2.A.B' + CR4.A.B
AB S2 = CR1.AB' + CR3.A.'B' R2 = CR1.A'B + CR3.AB

00 01 11 10 D S3 = CR2.A.B + CR4.A.B' R3 = CR2.A'.B' + CR4.A'B
1 5 - 2 O S4 = CR1.A.B + CR3.A'B R4 = CR1.A'.B' + CR3.AB'
D = CR1.B + CR2.A' + CR3.B' + CR4.A

6 - 3 2 O
- g. Exitation and Output Functions
4 3 7 O
1 4 8 - O Initially, A=B=0 and all Flip-flops are in reset state (CRi=0).
1 5 8 - 1 At that state, Flip-flop 1 must be set, with no confilict later,

that is to say, while CR1 and CR2 are not set.
6 5 - 2 1 S1 = A'B'.CR2'.CR3'
6 - h. Corrected System Initialization

3 7 1
- 4 8 7 1
Fig. 8-27 : Motor Direction Detection System Design (Copy of 6-4)
c. Primitive Flow-table
Tachometer
Servo Motor
Program Digital Error D/A Amplifier or Load
Comparator Converter
Servo Valve
Binary Signal Encoder Position
Fig. 8-28 : Simplified Block Diagram of a Closed Loop NC System (One Control Axis)
Pulses
Program Control Step Load
Logic Direction Motor
Fig. 8-29 : Block Diagram of an Open-Loop NC System (One Control Axis)

8-7
X1 X0 Y1 Y0 Z2 Z1 Z0
0 0 0 0 0 0 0 Z2 = X1.Y1 + X1.X0.Y0 + X0.Y1.Y0
0 0 0 1 0 0 1
0 0 1 0 0 1 0 Z1 = X1'X0.Y1'Y0 + X1.X0.Y1.Y0 + X1.Y1'Y0' +
0 0 1 1 0 1 1 + X1.X0'Y1' + X1'Y1.Y0' + X1'X0'Y1
0 1 0 0 0 0 1
0 1 0 1 0 1 0 Z0 = X0.Y0' + X0'Y0
0 1 1 0 0 1 1
0 1 1 1 1 0 0 b. Sum Output Minimized Functions
1 0 0 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 1 0 0 * 3-Bit Numbers Adder requires 6-Variable Map
1 1 0 1 1 0 0 * Karnaugh Map Metode Is Limited to 4-Bit Numbers
1 1 1 0 1 0 1
1 1 1 1 1 1 0 c. Karnaugh Map Methose Limitation
a. Truth Table
Fig. 8-30 : Adder for 2-Bit Numbers
Xn Yn Xn-1 Yn-1 Xi Yi X1 Y1 X0 Y0
Cn C2 C1
Cn+1 Cn-1 Ci+1 Ci C0=0
FA FA FA FA FA
Sn Sn-1 Si S1 S0
Fig. 8-31 : Iterative Adder Block Diagram
00/0 Xi,Yi/Si 01/0

01/1 10/0
10/1 11/1
00/1
C=0 Ci
C=1 4
11/0 Xi 1
3 5
6
Si
2
Yi
a. General Cell (FA) Flow Chart 4
1 6 4
2
3 5
5
6
Ci+1
Ci Xi Yi Ci+1 Si
0 0 0 0 0
1
0 0 1 0 1 3
2
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 c. FA Logic Circuit
Si = (XI) xor (Yi) xor (Ci)

Ci+1 = Xi.Yi+ Ci (Xi + Yi)
b. FA Truth Table Fig. 8-32 : Iterative Binary Adder Design
8-8
DESIGN OF A PARITY CHECKER DESIGN OF 2-OUT-OF-5 CHECKER
Checker detects if number of "1" in a binary A specific code consists of vectors that contain
vector, is odd or even. exactly two "1"'s, and all other bits are "0".
It produces a single output line P, where : (11000000, 00101000, 010000001 etc).
Design a circuit that checks vectors and announces
P=1 denotes odd parity
P=0 denotes even parity Z=1 when detected vector been found valid.
a. Requirements Definition a. Requirements Definition
X (Vector) P X (Vector) Z
b. Simplified Block Diagram b. Simplified Block Diagram
Xn Xi 0
0 0 0 0 1
Pn+1 Pn Pi-1 Pi P1 P0
1 1 1
N=0 N=1 N=2 N>2
c. Iterative Block Diagram
A B C D
c. General Cell Flow Chart
0 0
Xn Xi X0
1
P=0 P=1
1 "1" An+1 An Ai-1 Ai A1 A0
"0" Bn+1 Bn Bi-1 Bi B1 B0
d. General Cell Flow Chart "0" Cn+1 Cn Ci-1 Ci C1 C0
D1
*
"0" Dn+1 Dn Di-1 Di D0
Pi-1 Xi Pi
d. Iteratice Block Diagram
0 0 0
0 1 1 Ai-1 Bi-1 Ci-1 Di-1 Xi Ai Bi Ci Di
1 0 1 1 - - - 0 1 0 0 0
1 1 0 1 - - - 1 0 1 0 0
e. General Cell Truth Table

- 1 - - 0 0 1 0 0
- 1 - - 1 0 0 1 0
Pi = Pi-1.Xi' + Pi-1'.Xi = Pi-1 xor X

- - 1 - 0 0 0 1 0
f. General Cell Function

- - 1 - 1 0 0 0 1
- - - 1 0 0 0 0 1
Xi
- - - 1 1 0 0 0 1
e. General Cell Truth Table
4
6
Pi-1
5 Pi
Ai = Ai-1.Xi'
Bi = Ai-1.Xi + Bi-1.Xi'
g. General Cell Logic Circuit Ci =Bi-1.Xi + Ci-1.Xi'
Di =Ci-1.Xi +Di-1
f. General Cell Function
Fig. 8-33: Iterative Parity Checker Fig. 8-34 : Iterative 2-Out-of-n Checker
8-9
DESIGN OF A BINARY COMPARATOR
Comparator compares 2 binary numbers X,Y (of equal length), and produces 3 output signals:
Line A : A=1 if X>Y
Line B : B=1 if X=Y
Line C : C=1 if X<Y
Design refers to positive numbers of n+1 bits, where n may vary according to case.
a. Requirements Definition
X (Vector) A (X>Y)
B (X=Y)
Y (Vector) C (X<Y)
b. Simplified Block Diagram
Xn Yn Xn-1 Yn-1 Xi Yi X0 Y0
An+1 An An-2 Ai-1 Ai A1 A0

0
Bn+1 Bn Bn-2 Bi-1 Bi B1 B0
1
Cn+1 Cn Cn-2 Ci-1 Ci C1 C0
0
c. Iterative Block Diagram
AB 00 11
Ai = Ai-1 + Bi-1.Xi.Yi'
- A=B -
01 10 Bi = Bi-1(Xi.Yi+Xi'.Yi') = Bi-1(Xi xor Yi)'
Ci = Ci-1 + Bi-1.Xi.'Yi
A<B A>B f. General Cell Functions
d. General Cell Flow Chart
Xi Yi
Ai-1 Bi-1 Ci-1 Xi Yi Ai Bi Ci
1 0 0 - - 1 0 0
0 0 1 - - 0 0 1
Ai-1 Ai
0 1 0 0 0 0 1 0
4
6
5
0 1 0 0 1 0 0 1 Bi
Bi-1
0 1 0 1 0 1 0 0
Ci-1 Ci
0 1 0 1 1 0 1 0
e. General Cell Truth Table g. General Cell Logic Circuit
Fig. 8-35 : Iterative Binary Numbers Comparator

8-10
Natural Reflected
Decimal Binary Cyclic
Value Code Code
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Fig. 8-36 : Comparison Between

Natural-Binary and Reflected-Cyclic Code
N(m) C(m) N(m)

C(m)
C(m-1)
C(m-1) N(m-1)
N(m-1)
C(m-2)
C(m-2) N(m-2)
N(m-2)
C(m-3)
C(m-3) N(m-3)
N(m-3)
Fig. 8-37 : Iterative Circuit for Translating Fig. 8-38 : Iterative Circuit for Translating
Natural-Binary into Reflected-Cyclic Code Reflected-Cyclic into Natural-Binary Code
N(i) N(i-1) C(i-1)
0 0 0
0 1 1
1 0 1
1 1 0
C(i-1)= N(i) N(i-1)

N(i-1)= N(i) C(i-1)
Fig. 8-39 : Truth Table for Translating

Natural-Binary into Reflected-Cyclic Code
CHAPTER 9
SEMI-FLEXIBLE AUTOMATION
HARDWARE PROGRAMMERS
Drum Programmers
Programmable-Counter 1/n
Programmable-Counter 2/n
DRUM PROGRAMMER (STEPPING SWITCHED) MATRIX BOARDS
9-2
Y X
y1 y2 x1 x2 In Out
1 6
+
+
1 2 3 4
-
Y+ Y- X+ 2 7 A
3 8 B
Cylinders D,E,F Types Cylinders A,B,C Types C

4 9
D
5 10
D- E
E+
START , A+, B+, B-, C+, C-, D+, A-, , F-, F+, F-, F+, E-
F+ F- a. Patch Board b. Matrix Board
Switches Fig. 9-3 : Boards

Signal I II III IV V VI VII VIII IX X
Desired to Connected to
Step Event Advance A+ B+ C+ D+ D- E+ E- F+ F- Motor
1 / Start
2 A+ a2 X
3 B+ b2 X X
4 B- b1 X 1 2 3 4 1 2 3 4
5 C+ c2 X X A A
6 C- c1 X
7 D+ d2 X X B B
8 A- a1
E+ C C
9 e2 f2 X X
F+ D D
10 F- f1 X
11 F+ f2 X
12 F- f1 X a. With Sneak Path b. Without Sneak Path
13 F+ f2 X
D-
14 E- d1 e1 f1 X X X Fig. 9-4 : Matrix Board
F-
15-24 Go / X
Home
Fig. 9-2 : Drum Programmer Solution
PROGRAMMABLE COUNTERS (SEQUENCERS) Xn
X1 X2 X3 X4 X5 X6 Xn START X1 X2 X3 X4 Xn-1
&
1 2 3 4 5 6 --- n 1 2 3 4 5 --- n n+1

Connected Connected
to Module 1 to Module
1
Not
Used
Z1 Z2 Z3 Z4 Z5 Z6 Zn Z1 Z2 Z3 Z4 Z5 Zn
Fig. 9-5 : Schematic Representation of Fig. 9-6 : Programmable Counter With

Programmable Counter Single-Cycle START mode
b1 c1 b1 c1
Start a2 b2 c2 a1 a2 a1 Start a2 b2 c2 a1 a2 a1
& &
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Not Not Not

Used Used Used
>1 >1
>1 >1 >1

A+ B+ C+ B- C- A-
B- A+ B+
START , A+, B+, C+ , A- , C+
, A+ , A-
C-
Fig. 9-7 : Programmable Counter Circuit for Fig. 9-8 : Programmable Counter Circuit for
Sequence With Parallel and Repeated Events Sequence of Fig 9-7, While Actuating Valves
(Actuating Valves Without Return Springs) Have Return Springs
Xi X1 X2 X3 X4 9-3
Si
Si+1
-
Si
+
Ri
Zi Z1 Z2 Z3 Z4
a. Actual General Cell b. Actual Counter Configuration
Xi X2 X3 X4
X1
& From Zi+1

& & & &
SET RESET SET RESET SET RESET SET RESET SET RESET
y y' y y' y y' y y' y y'

From Zi-1
To Zi+1 SET
To Zi-1 RESET
y1 y2 y3 y4
step y1 y2 y3 y4 y5
Zi Z1 Z2 Z3 Z4
1 1 0 0 0 0
c. Equivalent General Cell d. Equivalent Counter Configuration 2 0 1 0 0 0
3 0 0 1 0 0
4 0 0 0 1 0
5 0 0 0 0 1
Fig. 9-9 : Programmer Based on 1/n Code
e. Counter cycle states
Xi X1 X2 X3 X4
Si Si+1
-
-
+
Ri
Zi Z1 Z2 Z3 Z4
a. actual General Cell b. Actual Counter Configuration
From Zi-1 From Zi+1
SET RESET SET RESET SET RESET SET RESET SET RESET
step y1 y2 y3 y4 y5
y y' y y' y y' y y' y y' 1 1 1 0 0 0
2 0 1 1 0 0
Xi X1 y1 X2 y2 X3 y3 X4 y4 3 0 0 1 1 0
4 0 0 0 1 1
5 1 0 0 0 1
& & & & & e. Counter cycle states
To Zi+1 SET
To Zi-1 RESET
Zi Z1 Z2 Z3 Z4
c. Equivalent General Cell d. Equivalent Counter Configuration
Fig. 9-10 : Programmer Based on 2/n Code

B+
a1 b2 a1 a2
START , A+ , A- , B+ , C+ , B- . C- START A+ , , C+ , D+ , D- , C- , B-
, A-
a. Sequence a. Sequence
start a2 a1 b2 c2 d2 d1 c1 b1
Start a2 a1 b2 c2 b1 c1 & A+
B+
(a) (b)
1 2 3 4 5 6 7 8 a1 b2 c2
1 2 3 4 5 6 7 A+ B+ C+ D+ (D-) (B+) (B-) B+

(B+) (B+) (B+) Start b2
& A-, ,B-
(C+) C+
>1 >1 OR
OR
A+ B+ C+ B+
A+ D+ C+ B+
>1
b. 1/n Prog.Counter Circuit
b. 1/n Prog.rammable Counter Circuit
(c)
B+ C+
(d)
Start a2 a1 b2 c2 b1 c1
& - - - - A- , B+ , C+ , C- , B- - - - -
a1 b2 c2 c1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7
A+ B+ C+ D+ (D-) (B+) (B-)
(A-) (B+) (B+) (A-)
(C+)
FLIP-FLOP
S
Q
R
>1 >1 SET RESET
(B+) (B+) (B-)
FLIP-FLOP
(C-)
SET RESET SET RESET
FLIP-FLOP FLIP-FLOP
B+ C+
A+ B+ C+ (Both B and C require flip-flops)
c. 2/n Programmable Counter Circuit A+ B+ D+ C+ (e)
c. 2/n Programmable Counter Circuit
9-4
Fig. 9-11 : Programmable Counter Example 1 Fig. 9-12 : Programmable Counter Example 2 Fig. 9-13 : 2/n - Different Stability Cases
(With Return (With Return (With Return
Springs) Springs) Springs)
B1 B2 B3 Bm 9-5
A1 A2 An 1 2 2 --- m
D1 D2 Dp
ZB1 ZB2 ZB2 ZBm

1 2 --- 3
& 1 2 --- p
C2 Ck
ZA1 ZA2 ZAn

ZD1 ZD2 ZDp
1 2 --- k
ZC1 ZC2 ZCk
Fig. 9-14 : 1/n Programmer fot Two Simultaneous Parallel Paths

B1 B2 B3 Bm
A1 A2 An & 1 2 2 --- m
D1 D2 Dp
ZB1 ZB2 ZB2 ZBm

1 2 --- 3
>1 1 2 --- p
C2 Ck
ZA1 ZA2 ZAn

ZD1 ZD2 ZDp
& 1 2 --- k
Path B for P=1
P' Path C for P=0
ZC1 ZC2 ZCk
Fig. 9-15 : 1/n Programmer for Two Alternative Parallel Paths (Parallel)
P' C1 C2 Ck
A1 A2 An B1 B2 Bm
&
1 2 --- 3 & 1 2 --- m >1 1 2 --- k
P Skip for P=0

ZA1 ZA2 ZAn ZB1 ZB2 ABm ZC1 ZC2 ACk
Fig. 9-16 : 1/n Programmer for Program With Skip Steps Option
A1 A2 An B1 B2 Bm C1 C2 Ck
P
1 2 --- 3 >1 1 2 --- m & 1 2 --- k
&
ZA1 ZA2 ZAn ZB1 ZB2 ABm ZC1 ZC2 ACk
Repeat for P=0

P'
Fig. 9-17 : 1/n Programmer for Program With Repeated Steps Option
Is design
YES flexibility NO
requested?
Is design
YES simplicity more NO
important than
Programmable
element econpmy?
counter
Are
YES relays NO
used?
Relay Are Are

cascade YES valves NO YES valves NO
method used? used?
Are there More than NO Huffman

YES repeated NO YES 4 or 5 method
events? cylinders?
More than Are there

YES 4 or 5 NO YES repeated NO
cylinders? events?
Pneumatic Operation- Pneumatic Flow-Table

Programmable Flow-Table cascade Programmable table cascade or Huffman
counter method method counter method method method
Fig. 9-18 : Flow Chart for Selecting Sequence-Control System Design Method
9-6
CHAPTER 10
PROGRAMMABLE
LOGIC CONTROLLER
Introduction
PLC Configuration
PLC Programming
Implementation in Ladder Diagram
Implementation in Huffman Metode
PLC CONSTRUCTION RAM Random-Access Memory
ROM Read-Only Memory
PROM Programmable Read-Only Memory
Central Input EPROM Erasable Programmable Read-Only Memory
Processing Modules EEPPOM Electrically Erasable Programmable Read-Only Memory
Programming Controlled
Unit Unit (CPU) System
Output
Memory Modules Fig. 10-6 : Type of Electronic Memories
PLC
Input Output
Modules Modules
Fig. 10-1 : Block Diagram of Programmable Controller (PLC) Start PB1
000 000 PL1 Rdy
Memory Size (Words) I/O Capacity (Modules) Reset PB2
001 001 Set 1 Open
Micro PLC Up to 64
Small PLC Up to 128 Temp TS3 PLC
002 Program 002 PL2 #1
Medium PLC Up to 512 Coding
Large PLC > 512 Level FS4
003 003 Set 2 Open
Fig. 10-2 : PLC Classification According to Size Level FS5
004 004 PL3 #2
.........
.........
Limit Switches
Proximity Switches
Photoelectric Switches
Sensor Switches (Level, Pressure, Temperature etc) n m
Push-Button Switches
Selector Switches
Relay Contacts
Fig. 10-7 : I/O Connection Diagram
Fig. 10-3 : Discrete Input Devices to PLC
Contact Relay Coils

Valve Solenoids Controlled System Controlled System
Pneumatic or Hydraulic Cylinders and Motors
..........
Lights
Audible Alarms (Bells,Buzzers,Sirens) I/O Modules (Field Mounted
.......... with Multiplexer)
Fans
Heaters
Motor Starters
..........
Fig. 10-4 : Discrete Output Devices Actuated by PLC I/O Modules (PLC Mounted)
PLC PLC
12, 24, 48, 120, 230 Volt AC
12, 24, 48, 120, 230 Volt DC a. PLC-Mounted I/O b. Remote-Mounted I/O
10-1
5V DC (TTL Level)
Conract Relay Output
Fig. 10-8 : Different I/O Connection Location
Fig. 10-5 : Standard Discrete I/O Interface Modules
Word Adress (Octal) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10-2
0000
(8 Words) Input Table - 128 Bits

0007
0010
(8 Words) Output Table - 128 Bits
0017
0020
(8 Words) Internals - 128 Bits
0027
0030
(256 Words) Registers
0427
0430
(3816 Words) User Memory
7777
Fig. 10-9 : Typical PLC Memory Map
Programming the PLC

1. Ladder Diagramms or Graphic Programing - entered either by drawing the Ladder diagram on screen, or by
Boolean Mnemonics.
2. Boolean Mnemonics or Logic Instruction Set.
3. GRAFCET or Function Chart -
Used by : Telemechanique, France (GRAFCET)
Allen Bradley, USA (SFC = Sequential Function Chart)
Siemens, Germany (Graph 5)
4. Enhansed Ladder Diagrams (Ladder Diagrams with "Instruction Blocks").
5. Computer Language such as BASIC, with additional commands.
Fig. 10-10 : Programming Languages
O0033
10036 10047
12 16
( ) 14
O0034
10124 10107 10113
03 86 82
( ) 02
10113 08114
86 10
O0034
04
86
( ) 17
10118 T0045
TIMER ON ADDR
01 (EN) 17
0.1 SECOND T 0045
10112 T0045
PR = 3200 TP0045
83 AC = 520 TA0045 (TC) 15
O0075
10054
16
( ) 15
Fig. 10-11 : Ladder Diagram Section Appearing On Screen

(Allen Bradley Co. PLC)
INPUT INPUT CPU
10-3
DEVICES MODULES OUTPUT OUTPUT
MODULES DEVICES
INPUT OUTPUT
SENSOR 1 HIGH/LOW MODULE
LOGIC X1 Y1 LOGIC MODULE
HIGH/LOW LOAD 1
VALUES 1 LEVEL LEVEL 1 VALUES
INPUT OUTPUT
HIGH/LOW LOGIC X2 PLC Y2 LOGIC MODULE HIGH/LOW LOAD 2
SENSOR 2 VALUES MODULE
LEVEL LEVEL 2 VALUES
2
CR1
CRk
INPUT OUTPUT
SENSOR n HIGH/LOW MODULE
LOGIC Xn Ym LOGIC MODULE HIGH/LOW LOAD m
VALUES N LEVEL LEVEL M VALUES
(LOGIC LEVEL)
Fig. 10-12 : PLC Configuration
PLC SYSTEM CYLINDER SYSTEM
START a1 a2
Start INPUT X0
-
MODULE
1
CPU Y1 OUTPUT A+
+ -
MODULE
a2 INPUT X1 1
MODULE
2
a1 INPUT X2 Y2 OUTPUT A-
MODULE
3 MODULE
2
Fig. 10-13 : Typical PLC Control System
PROCESS PROCESS
5 6
PLC PLC
6 6
PROCESS
PLC PROCESS
4 PLC 7 7
4
PLC
PROCESS PLC 8 PROCESS
3 8
3 HOST
PROCESSOR
PROCESS PLC PLC PROCESS

2 2 9 9
PLC PLC
1 n
PROCESS PROCESS
1 n
Fig. 10-14: PLC Network (Macro)

10-4
C-
D+
START , A+ , , C- , A- , B+ , A+ , C+ , B- , D- , Start X0
A-
C+
a1 X1 Y1 A+
a. Process sequence
a2 X2 Y2 A-
b1 X3 Y3 B+
INPUT TABLE OUTPUT TABLE OUTPUT TABLE
(NO RETURN SPRING) (WITH RETURN SPRING) b2 X4 Y4 B-
c1 X5 Y5 C+
X0 START Y1 A+ Y1 A+
X1 a1 Y2 A- Y2 B+ c2 X6 Y6 C-
X2 a2 Y3 B+ Y3 C+
X3 b1 Y4 B- Y4 D+ d1 X7 Y7 D+
X4 b2 Y5 C+ d2 X8 Y8 D-
X5 c1 Y6 C-
X6 c2 Y7 D+ PLC
X7 d1 Y8 D-
X8 d2 (no return springs)
(no return springs) (with return springs)
b. Input Table c. Output Table d. Output Table e. PLC and I/O System
Fig. 10-15 PLC I-O Variables Assignment
(Temperature Switch)
START STOP X18 X19
T.S. X17
CR1 CR1
C R1 C R1
MOTOR
C R1 C R1
MOTOR Y13
(Motor current must be isolated from sensors)
a. Relay Ladder Diagram for Motor Control e. PLC "Internal" Ladder Diagram
INPUT OUTPUTM
Start MODULE ODULE
Stop
System Motor Start X17
X17 X18 X19
T.S. Stop X18 Y13
T.S. X19
Y13
b. Block Diagram MOTOR Y13 (No isolation problem since all
I/O are isolated by modules)
c. I/O Assignment Table f. Simplified Ladder Diagram
Start Input STORE X17

Module X17
OR Y13
Stop Input Output Motor
Module X18 Y1
Module
MOTOR AND NOT X18
PLC AND NOT X19
T.S. Input
Module X19 OUT Y13
d. PLC Ladder Diagram g. PLC Program
Fig. 10-16 PLC Motor Control System

Stop M1
000 001 002 032 003 030
000 030 f x3 cr1 cr3
CR2
Reverse
030 cr2 X5
Forward PL1
...
000 001 002 031 Y12
001 031
cr2 x4
Forward 030 Y13
002 M2 cr6
000 002 001 030 004 032
...
032 r
cr1 032 Fig. 10-20 : Ladder Diagram of Fig. 10-18 in PLC Format
003
Reverse PL2
cr2 000 002 001 033
004 033 0 STORE NOT X1
1 AND CR1
032 OL1 Fault PL2 2 OR CR2
003 034
034 3 AND NOT CR3
4 OUT CR2
OL2 Fault PL2 5 AND X5
004 035 6 OUT Y12
035
7 STORE CR2
8 AND X4
9 OR CR6
Fig. 10-17 : Forward/Reverse Circuit
10 OUT Y13
(Using Two Motors M1 na M2, and Overload Switches OL1 and OL)
Fig. 10-21 : Program for Fig. 10-20
a2 cr1 cr3
CR2
cr2
d2 B+ X2 cr10
Y5
b2 C+ cr11
X4
cr6
Fig. 10-22 : Use of LIFO Memory Stack

Fig. 10-18 : Ladder Diagram Segment Illustrating
Repeated Actuation of Solenoid C+
0 STORE NOT X2
1 AND CR10
Input Module Output Module Connected to 2 STORE NOT X4
X3 a2 3 AND CR11
X4 b2 4 OR STORE
X5 d2 5 OUT Y5
Y12 B+
10-5
Y13 C+ Fig. 10-23 : Program for Fig. 10-22
Fig. 10-19 : I/O Assignment Table for Fig. 10-18

START cr3' cr4' cr2' A+ B-
CR1 START C+ A- C- C+
B+ C-
cr1
STORE X0
I II III IV AND NOT CR3
cr1 c2 cr3' AND NOT Y4
CR2 a. Process sequence Groups partitining
OR Y1
cr2
AND NOT Y2
X0 cr3' y4' y2' OUT Y1
cr2 c1 cr4' Y1
CR3 AND X6
y1
cr3
START x0 OR Y2
AND NOT CR3
a1 x1 y1 X6 cr3'
OUT Y2
cr3 c2 b1 Y2
CR4
a2 x2 y2
AND X5
cr4 c1 OR CR3
b1 x3 AND NOT Y4
y2 X5 y4'
CR3 OUT CR3
cr1 A+
b2 x4
cr3 AND X6
c1 x5 OR Y4
cr2 A- cr3 X6 X3'
STORE NOT X3
c2 x6 Y4 OR NOT X5
y4 X5' AND STORE
cr1 B+ OUT Y4
A+ Y1
y1
STORE Y1
cr4 B- A- Y2 Y3 OUT Y3
AND X2
B+ Y3
cr1 C+ y1 X2 x4 AND X4
a2 b2 Y5
B- Y4 OR CR3
cr3 cr3 OUT Y5
C+ Y5 STORE Y2
Y1 = CR1
cr2 C- y2 X1 AND X1
a1 C- Y6 Y2 = CR2 Y6 OR Y4
cr4 Y4 = CR4 y4 OUT Y6
c. PLC Variables d. Optimize CR f. PLC Program

b. Relays Cascade Circuit Assignment Relays e. PLC Cascade Circuit
10-6
Fig. 10-24 : PLC Cascade System Design
X1
X1 CR5 CR10 CR11 F1
CR1 CTR CTR
(25) CR1 (n) CR1
X2
X2 CR6 CR2 CR3 F2
X1= O-->1 One count F1= O-->1 One count

a. Ladder Diagram X2=1 Counter Enabled X2=0 Counter is Reset F2=1 Counter Enabled F2=0 Counter is Reset
a. Specific Case b. General Case
STORE NOT X1
AND CR5 Fig. 10-29 : Counter to Count 25 (Texas Instruments PLC)
STORE NOT X2
AND NOT CR6
OR STORE
STORE NOT CR10 STORE X1
AND NOT CR11 STORE X2
STORE CR2 CTR1
empty 25
AND NOT CR3
OR STORE OUT CR1
AND STORE
OUT CR1 Fig. 10-30 : Program for Fig. 10-29 (a)
b. PLC Programming
LOAD NOT TMR2
Fig. 10-25 : Multiple Use of LIFO Stack TMR1 OUT TMR1
5
TMR2 (0.5 Sec) LOAD TMR1
TMR1
X1 X2 X3 X4 X1 OUT TMR2
CR1 CR1
TMR1 (0.5 Sec) 5
X2 TMR2
X3 X4 LOAD X1
X3 X4 (Light Valve) AND TMR1
Y1 OUT Y1
STORE X1
STORE X2 STORE X3
STORE X3 AND X4 a. Ladder Duagram b. Programmable of (a)
AND X4 OR X2
OR STORE AND X1
AND STORE OUT CR1 Fig. 10-31 : Making Light Flash While X=1 (General Electric PLC)
OUT CR1
a. Original Circuit b. Programmable Simplified Circuit
Fig. 10-26 : Rearrangement of Ladder

Diagram for Simpler Programming
X1 (Up/Down) (Up/Down) LOAD NOT X1
F1
LOAD NOT X2
CTRi CTRi
X2 (Event) (Event) LOAD NOT X3
(120) F2 (n) OUT CTR3
TIMERS AND COUNTERS 120
X3 (Reset) (Reset)
F3 LOAD CTR3
OUT Y1
X1 CTR3 CTRi
F1 Y2 Y2
TMR TMR
(200) CR1 (n) CR1 c. Programmable of (a)
X2
F2
X1 determines UP or DOWN mode F1 determines UP or DOWN mode
X1=1 Timer Run X1=0 Timer Stops F1=1 Timer Run F1=0 Timer Stops X2= O-->1 One count F2= O-->1 One count
X2=1 Timer Enabled X2=0 Timer is Reset F2=1 Timer Enabled F2=0 Timer is Reset X3=1 Counter Enabled F3=1 Counter Enabled F3=0 Counter is Reset
X3=0 Counter is Reset
Fig. 10-27 : Timer Set for 20 Seconds (Texas Instruments PLC)
10-7
Fig. 10-32 : UP/DOWN Counter (General Electric PLC)
STORE X1
STORE X2
TMR1
empty 200
OUT CR1
Fig. 10-28 : Program for Fig. 10-27 (a)

X3
TMR
10-8
X5 (5)
CR1
X3
(0.3 Sec)
X5
CR1
X3 X3
Y1
y1
Fig. 10-33 : Two-Hands Circuit Using PLC
D
START,(D+,D-) repeat 6 times,D+,10 Sec DELAY,D-
d1 d2
+
a. Required Cycle
-
D- D+
b. Cylinder Type
Fig. 10-34 : Process Definition
CR5 X1 (d2)
Input Modules Output Modules Connected to Y0
X0 d1 CR7
X1 d2
X12 START
Y0 D-
Y1 D+
STORE X0
a. Assignment Table AND NOT CR5
OUT Y1
X0 (d1) CR5
STORE NOT CR5
Y1
OR CR7
X1 (d2) CR5
AND X1
Y0
CR7
OUT Y0
STORE X0
X0 (d1) STORE NOT X12
COUNTER
1 CR3 CTR1
X12 (Start) (6)
6
X1 (d2) CR3 (NOT USED)
CR6
OUT CR3
CR6 TIMER
1 AND X1
(100) CR7
CR6 (10 Sec) OUT CR6
STORE CR6
b. Ladder Diagram TMR1
100
(NOT USED)
OUT CR7
Fig. 10-35 : Design PLC Program for Sequence
of Fig.10-34 c. PLC Programm
10-9
TMR1 An elevator exists in a 5-floor building.

X1 COUNT OUT
Elevator runs automatically (without human control),
(120)
from 1st floor to 5th floor, and vica versa, while stopping
for 10 seconds in each floor.
TMR1
Each floor is equipped by a unique contact, that is closed
when the elevator reaches that floor. These contacts are
LOAD X1 implemented as input sensroes for PLC control system.
OUT TMR1
a. System Description
120
a. General-Electric PLC Timer
1st X1
INPUT
COUNTER (GE) MODULE
X1 PLC
UP/DOWN 2nd X2 UP
CTR1 INPUT Y1 OUTPUT MOTOR
X2 EVENT OUT
MODULE MODULE
(120)
X3 3rd
RESET X3 Y2 OUTPUT MOTOR
INPUT MODULE
CTR1 MODULE
DOWN
4th X4
LOAD X1 INPUT
LOAD X2 MODULE
LOAD X3 5th X5
120 INPUT
MODULE
OUT CTR1
b. General-Electric PLC Counter

b. PLC System Configuration
X1 COUNT
TMR1
(120)
OUT
CR1
X2 RESET
X1
X2
CR1
X3
STORE X1 CR0
STORE X2 X4
TMR1
X5
120
(empty)
CR0
OUT CR1 COUNT
TMR1
OUT CR1
c. Texas-Instruments PLC Timer (100)
CR0 RESET
X1
X5
CR2
X1 EVENT
CR2
CTR1
(120)
OUT
CR1 CR1
X2 CR2
RESET Y1
CR0
CR1
CR1
CR2
STORE X1 Y0
CR0
STORE X2
CTR1
120 Notes : CR2 control elevator direction
Y1 - Up direction
(empty) Y2 - Down direction
OUT CR1
d. Texas-Instruments PLC Counter c. PLC Ladder Diagram
Fig. 10-36 : PLC Timers and Counters Fig. 37 : "Saturday" Elevator

10-10
...
X6 STORE X6
MCR(3)
MCR 3
...
A. Ladder Diagram b. Programming Lines
If X6=0, then the next (3) outputs are kept at logic "0" (shut off)
c. Command Definition
Fig. 10-38 : Master Control Relay (MCR) Command
...
X6 STORE X6
JKP(3)
JMP 3
...
A. Ladder Diagram b. Programming Lines
If X6=0, then the next (3) outputs are frozen, and the PLC
continues its scan at the rung following the third output
c. Command Definition
Fig. 10-39 : Jump (JMP) Command
X1 X2 X1 X2
CR1 CR1
X3 X4 X3 X4
X5 X3 X5
CR2 CR2
a. Relay Ladder Diagram c. PLC Ladder Diagram
CR1 = X1.X2 + X3.X4.X2

CR1 = X1.X2 + X3.X4.X2
CR2 = X3.X5
CR2 = X3.X5 + X1.X4.X5
b. Boolean Function d. Boolean Function

Un-expected Sneak Path - X1.X4.X5 No Sneak Path
Fig. 10-40 :Differences Between Relay and PLC Ladder Diagram

Sneak Path
X1 X3 X1 X2
CR1 CR1
X5 X2 X3
X2 X4
X1 X5 X4
X2 X5 X3
a. Relay Ladder Diagram b. PLC Ladder Diagram
CR1 = X1.X3+X2.X4+X1.X5.X4+X2.X5.X3
c. Boolean Function
Fig. 10-41 :Differences Between Relay and PLC Ladder Diagram

Multiple Contacts
X1 cr2 y1
Rung 1 CR1
I/O Update X1 cr2 cr1

Variables
at Beginning of Scan States Rung 2 Y1
This Scan Next Scan y1
y7
CR2 Y7=0 , CR2=0 Y7=1 , CR2=1 X1
cr4 Rung 3 CR1
CR6 CR4=0 , CR6=0 CR4=1 , CR6=1
x4
Fig. 10-44 : Trigger (Toggle) Flip-Flop for PLC
Y7 X4=1 , Y7=1
x4 1 2 3 4 5 6 7 8 9 10 11 12 13
CR4 X4=1 , CR4=1 PLC Scan
y7 X1 (Input)
CR5 Y7=1 , CR5=1
cr6 Rung 1 : CR1

Y8 CR6=0 , Y8=0 CR6=1 , Y8=1
Rung2 : Y1
(Output)
Fig. 10-42 : Effect of Scanning Action on
Internal States of Relay Coils Rung 3 : CR2
Fig. 10-45 : PLC Sequence Chart for Fig. 10-44
USE OF PLC WITH ANALOG I/O

X1 cr1 STORE X1 Pressure Transducers
Y1 AND NOT CR1 X1
Temperature Transducers
OUT Y1 Flow Transducers
X1
STORE X1 Y1 Scan Period
CR1 Humidity Transducers
OUT CR1 Load Cells
Potentiometers
a. Proper Rung Order
Fig. 10-46 : Analog Input Devices to PLC
4 - 20 mA
X1 STORE X1 0 - 1 volt DC
CR1 X1 0 - 5 volt DC
OUT CR1
STORE X1 0 - 10 volt DC
X1 cr1
AND NOT CR1 Y1 1 - 5 volt DC
Y1
OUT Y1 +/- 5 volt DC
+/- 10 volt DC
b. Improper Rung Order Fig. 10-47 : Standard Analog-Input Interfaces Nodules
Fig. 10-43 : Importance of Proper Rung Order Analog Valves

Pneumatic or Hydraulic Cylinders or Motors
10-11
Recorders
Electric Motors
Fig. 10-48 : Analog-Output Devices Actuated by PLC

4 - 20 mA
Analog
10 - 50 mA instruction
used
0 - 5 volt DC
Voltage Signal
0 - 10 volt DC D/A Analog
0 0 1 0 1 1 0 1 1 0 0 1 Transducer
Return Line
+/- 5 volt DC 12 bits Register holding analog value
+/- 10 volt DC Analog Output module
PID Controller
Fig. 10-49 : Standard Analog Output Interface Modules Analog

instruction
used Not Used
Voltage Signal 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 Word location

Analog or
Transducer A/D 0 0 1 0 1 1 0 1 1 0 0 1
Return Line Register Storage
Register holding analog value location
12 bits
Analog input module Data Table
Fig. 10-52 : Tranferring a Word to Analog Output Module

0 0 1 0 1 1 0 1 1 0 0 1
Word location ANALOG OUTPUT
or
Register Storage
location Rack 4 (Rack with 4 slots)
Data Table
Slot 05 (Slots 0 to 7 per rack)
Number of channels 4
Since A/D converters are expensive, they are often shared by several Source register 300
4 to 8 channels. One channel is read and stored on every scan. (Octal code 300 = 192)
Fig. 10-50 : Storing an Analog Input Fig. 10-53 : Typical "Analog Out" Instruction Block
PID CONTROLLER
ANALOG IN Control Connected to Register
Rack o (Rack with 8 slots) (Enables Outputs) 1. Controlled Variable (Given by analog input module)
Slot 03 (Slots 0 to 7 per rack) 2. Controller Output (Sent to analog output module)
Number of channels 8 3. K (P-control) (Active loop control)
Destination register 200 (Octal code 200 = 128) Track 4. R (I-control)
(Tracks incoming (High alarm limit)
(Since there are 8 channels, the 8 slots would be assigned the variables, even if 5. T (D-control) (Low alarm limit)
Destination Register 200 8 to 207 8) "Control" is off) 6. Set Point
In some PLC's, the PID Controller is implemented

Fig. 10-51 : Typical "Analog In" Instruction Block by a special output module, i.e. by hardware. In
others, it is programmed using a special Insrtuction
10-12
Block, such as shown here.
Fig. 10-54 : Typical "PID Controller" Instruction Block

ENHANCED LADDER DIAGRAM INSTRUCTIONS Data Conversion
(Enhanced ladder diagram instructions are handeled very differently in different
PLC models. Therfore, only a few typical examples are shown here.) These change the contenta of a specified register.
Typical Conversions :
BCD to Binary
LATCH (UNLATCH) Binary to BCD
GOTO Absolute Value
ADD Complement (multiplied by -1)
ADD Invert (inverts all bits)
Control Overflow
(Enable) Register X Output Logical Shifts : Moves all bits of a register to right or left
+
Register Y
=
Register Z
Data Transfer Instructions : There are many such
instructions, used to move data
within the PLC
Fig. 10-58 : Data Commands
Fig. 10-55 : Typical "ADD" Instruction Block
MICRO-AUTOMATION versus MACRO-AUTOMATION

SUBTRACT Micro-Automation : Automation of a single machine, or a
MULTIPLICATION small group of machines, also called
an "Automation Island".
DIVISION (This course deals with Micro-Automation).
SQUARE ROOT Macro-Automation : Automation of a large plant, consisting of many

individual automation islands. Uses a large
COMPARE
computer or a large PLC, that coordinates the
COMPARE operation of the individual automation islands.
Each automation island is uusually controlled by its
Control
(Enable) > own control system, such as a small or
Register X
medium-sized PLC ("Distributed Control").
Register Y = Macro-automation makes use of a LAN (Local-Area-Network), which links
< the various stations or automation islands with the central supervising
computer or PLC. The use of a LAN provides :
Fig. 10-56 : Typical "COMPARE" Instruction Block 1. Distributed Control

2. Centralized Data Aquisision
The LAN can be organized according to any one of a several possible LAN
Topologies (arrangements), such as "Common Bus", "Star" or "Ring".
AND
Fig. 10-59 : PLC Micro/Macro Systems Definition
OR
XOR
NAND
NOR
NOT
Fig. 10-57 : Logic Operations BUS STAR RING
10-13
(or correcponding bits of two specified registers)
Fig. 10-60 : Several Possible LAN Topologies

10-14
1. Different size elements are transferred on a conveyor belt.
2. All elements that are below specific thickness must be rejected.
3. Reject is performed by opening a reject door - Z=1.
4. Photocells X1 and X2 are placed in specific locations.
5. X2 is covered by all sizes. X1 is covered by elements over Railway
specific thickness.
X1 X2
Road
See Fig. 6-3
a. System Configuration
A B B
CR1
CR1
00/0 10/0 11/0 01/0 CR1 B

1 2 3 4 L
01/1
5 b. System Relay Ladder Diagram
b. Primitive Flow Diagram
PLC I/O
S = X1.X2' (S = X1)
X1 A
R = X1'.X2' X2 B
Z = X2.CR1' Y1 L
c. System Functions (See Fig. 6-2)
c. PLC Variables Assignment
PLC I/O
X1 X1 X1 X2 X2
X2 X2 CR1
CR1
Y1 Z
d. PLC Variables Assignment CR1 X2
Y1
X1 X1 X1
CR1
CR1 X2
d. PLC Relay Ladder Diagram
Y1
CR1 X2
1 STORE X1
4 AND X2
e. PLC Ladder Diagram
3 OR CR1
4 AND X2
1 STORE X1 5 OUT CR1
2 OR CR1 6 STORE NOT CR1
3 STORE X1 7 AND X2
4 OR X2 8 OR X1
5 AND STORE 9 OUT Y1
6 OUT CR1
7 STORE NOT CR1
8 AND X2 e. PLC Program
9 OUT Y1
f. PLC Program
Fig. 10-62 : Traffic-Light
Control System
Fig. 10-61 : Thickness Detector System
Danger Signal X1 ALARM Z1 ALARM SIREN {3,4,5} {2.6} {1} 10-15
SYSTEM
Confirmation X2 Z2 ALARM FLASH
{1,5} {2.6} {3,4}
a. System Block Diagram (According to Fig.6-1) f. Merge Options
* Cannot ignore multiple input changes "simultaneously"

{1,5} {2.6} {3,4}
* No race or hazards. Action depends on commands Order
b. Different Considerations in Relay/PLC Systems g. Selected Options
X1,X2
00 10 11 01
00/00 10/10 11/01 10/10 CR1 1 2 3 5

1 2 3 4
CR2 6 2 3 5
CR3 1 4 3 5
01/00 00/10
5 6 X1,X2/Z1,Z2
h. Merged Flow Table &

States Assignment
X1,X2 X1,X2
c. Primitive Flow Diagram 00 10 11 01 00 10 11 01
X1,X2 CR1 0 - - 0 CR1 0 - - 0

00 10 11 01 z1 z2
CR2 1 1 - - CR2 0 0 - -
1 2 3 5 0 0
CR3 - 0 0 - CR3 - 1 1 -
6 2 3 5 1 0
1 4 3 5 0 1
i. Output Table of Z1 j. Output Table of Z2
1 4 3 5 0 1
1 2 3 5 S1 = X1'.X2'.CR2' + X1'.X2 = X1'(X2' + CR2')

0 0
S2 = CR1.X1.X2'
6 2 3 5 1 0 S3 = X1.X2
R1 = CR2.X1.X2' + X1.X2 = X1(X2 + CR2)
d. Primitive Flow Table
R2 = X1'.X2 + X1.X2 = X2
R3 = CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1'
1 Z1 = CR2 Z2 = CR3
k. Exitation & Output Functions
6 2 1 STORE NOT CR2 15 STORE X1

2 OR NOT X2 16 AND X2
3 AND NOT X1 17 OR CR3
4 OR CR1 18 STORE NOT CR1
5 STORE NOT X2 19 OR X1
5 3 6 AND NOT CR2 20 AND STORE

7 OR NOT X1 21 OUT CR3
8 AND STORE 22 OUT Z2
4 9 OUT CR1
23 STORE CR2
10 AND X1 24 OUT Z1
11 AND NOT X2
e. Merge Diagram 12 OR CR2
13 AND NOT X2
14 OUT CR2
l. PLC Program
Fig. 10-63: PLC Design of Alarm System

STORE NOT X1
10-16
AND NOT X2
Set 1 AND NOT CR2
A B AND NOT CR3
OR CR1
STORE NOT CR2
OR X2
See Fig. 6-4 STORE NOT CR4
Reset 1' OR NOT X2
AND STORE
OR NOT X1
AND STORE
OUT CR1
AND X1
S2 = CR1.A.B' + CR3.A'B' STORE CR3
Set 2 AND NOT X1
S3 = CR2.A.B + CR4.A.B' OR STORE
S4 = CR1.A.B + CR3.A'B AND NOT X2
OR CR2
S1 = A'B'.CR2'.CR3' STORE NOT CR1
R1 = CR2.A.B' + CR4.A.B = A(CR2.B' + CR4.B) OR X1
STORE NOT CR3
R2 = CR1.A'B + CR3.A.B = B(CR1.A' + CR3.A) Reset 2' OR NOT X1
R3 = CR2.A'.B' + CR4.A'B = A'(CR2.B' + CR4.B) AND STORE
OR NOT X2
R4 = CR1.A'.B' + CR3.A.B' = B'(CR1.A' + CR3.A) AND STORE
D = CR1.B + CR2.A' + CR3.B' + CR4.A OUT CR2
AND X2
b. System Original Functions (from 6-4) STORE CR4
AND NOT X2
Set 3 OR STORE
AND X1
OR CR3
PLC I/O STORE NOT CR2
OR X2
X1 A STORE NOT CR4
X2 B Reset 3' OR NOT X2
Y1 D AND STORE
OR X1
AND STORE
c. PLC Variables Assignment OUT CR3
AND NOT X1
STORE CR1
Set 4 AND X1
OR STORE
Set Functions AND X2
S1 = X1'X2'.CR2'.CR3' OR CR4
S2 = CR1.X1.X2' + CR3.X1'X2' = X2'(CR1.X1 + CR3.X1') STORE NOT CR1
OR X1
S3 = CR2.X1.X2 + CR4.X1.X2' = X1(CR2.X2 + CR4.X2') STORE NOT CR3
S4 = CR1.X1.X2 + CR3.X1'X2 = X2(CR1.X1 + CR3.X1') Reset 4' OR NOT X1
AND STORE
Inverted Reset Functions OR X2
R1' = X1' + (CR2'+X2)(CR4'+X2') AND STORE
R2' = X2' + (CR1'+X1)(CR3'+X1') OUT CR4
R3' = X1 + (CR2'+X2)(CR4'+X2') STORE CR1

R4' = X2 + (CR1'+X1)(CR3'+X1') AND X2
STORE CR2
Output Function AND NOT X1
Y1 = CR1.X2 + CR2.X1' + CR3.X2' + CR4.X1 OR STORE
Y1 STORE CR3
AND NOT X2
d. PLC System Functions OR STORE
STORE CR4
AND X1
OR STORE
OUT Y1
Fig. 10-64 : Motor Direction Detector
e. PLC Program
1. A security door is connected to a combination lock, that is controlled by two input switches : X1 and X2 . 10-17
2. The door is opened and closed, by entering the following sequence :
X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00
Open (T=1) Close (T=0)
Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as
input becomes 00.
a. System Definition
Improper Sequence Proper Sequence

Switch X1
Combination Open
Switch X2 Lock T Door
X1,X2 / T
01/0 00/0 10/0

11/0
8 1 2
b. System Block Diagram 3
01/1
7
11/0
10/0 10/1 11/1 10/0
9
10 6 5 4
X1,X2
00 01 11 10 T
1 8 9 2 0
1 8 3 2 0
1 8 3 4 0 1
1 8 5
10
4 0 2
1 7 5 6 1
1 7 5 6 1 9 3
1 7 5 6 1
1 8 9 10 0
8 4
1 8 9 10 0
1 8 9 10 0 7 5
{1},{2},{3},{4},{5,6,7},{8,9,10}
d. Primitive Flow Table 6
e. Merge Diagram f. Merge Selection
X1,X2 X1,X2
00 01 11 10 00 01 11 10
CR1 1 8 9 2 CR1 0 - - -
S1 = X1'.X2' R1 = CR2.X1.X2'+CR6.X2
CR2 1 8 3 2 CR2 - - - 0
S2 = CR1.X1.X2' R2 = CR2.X1.X2+CR.'.X2+X1'.X2'
CR3
1 8 3 4 CR3 - - 0 - S3 = CR2..X1.X2 R3 = CR3.X1.X2'+CR6.X1'+X1'.X2'
S4 = CR3.X1.X2' R4 =CR5.X1.X2+CR6.X2+X1'.X2'
CR4 1 8 5 4 CR4 - - - 0
S5 = CR4.X1.X2 R5 = X1'.X2'
CR5 1 7 5 6 CR5 - 1 1 1 S6 = CR1.X1.X2 +CR5'.X1'.X2 R6 = X1'.X2'
1 8 9 10 CR6
- 0 0 0 T = CR5
CR6
g. Merged Flow Table h. Output Table i. System Functions

& States Assignment
Fig. 10-65 : Combination Lock System

CHAPTER 11
INTRODUCTION TO
ASSEMBLY AUTOMATION
Nonvibratory Feeding & Orienting

Devices
Vibratory Feeding & Orienting Devices
Parts Transfer
CHAPTER 12
ROBOTICS AND
NUMERICAL CONTROL
Basic Robot Definitions

Basic Geometry
Numeric Control (NC) Systems
CHAPTER 13
APPENDIX
Simester Exam Example

Simester Exam Solution
Typical Simester Exam Questions
13-1
13-2
13-3
01.07.2003 - QUESTION 1
1 2 3 4
T = CDE'F + B'C'D'E'G + A'BDF + A'B'CD'E' +
+A'BC'DE + B'CDEF + A'B'E'FG + A'C'DE'F
5 6 7 8
13-4
7
01.07.2003 - QUESTION 2
PRIMITIVW FLOW TABLE

FLOW DIAGRAM
00 10 11 01 A
1
00/1
1 2 - - 1
3 2 5 - 0
4 5 2
01/0 11/0 3 - - 0
10/0 4
1 - - 4 0
3
00/0 - - 5 4 0
MINIMAL MERGE OPTIONS
2 A {1,4,5},{2,3} *
5
B {2,3,5},{1,4}
4 3
MERGED FLOW TABLE (A)
00 10 11 01
1 2 5 4
1 0 0
3 2 5 4
0 0
13-5
START X0
a1 X1
01.07.2003 - QUESTION 3 a2 X2
b1 X3
b2 X4
c1 X5
B+ B- c2 X6
START , , C+ , C- , C+ , , C-
A+ A-
A+ Y1
B+ Y2
I II III (IV) C+ Y3
STORE X0
AND NOT CR3
START
AND X5
cr3' c1 cr2' x0 cr3' x5 cr2'
CR1 CR1 OR CR1
cr1 cr1 AND NOT CR2
OUT CR1
cr1 c2 cr3' cr1 x6 cr3' AND X6
CR2 CR2 OR CR2
cr2 cr2 AND NOT CR3
a1 x1' OUT CR2
cr2 c1 cr2 x5
b1 CR3 x3' CR3 AND X5
cr3 cr3 OR CR3
STORE NOT X1
OR NOT X3
AND STORE
OUT CR3
AND NOT X6
cr1 A+ cr1 OR CR1
Y1
OR CR2
cr2 cr2
OUT Y1
cr3 c2
cr3 x6'
OUT Y2
STORE CR1
B+ AND X2
Y2
AND X4
OR CR3
cr1 a2 b2 cr1 OUT Y3
x2 x4
C+
cr3 cr3 Y3
PLC BASED DIAGRAM

RELAY BASED DIAGRAM
13-6
01.07.2003 - QUESTION 4
SEQUENCE
B+
START , A+ , , C+ , D+ , D- , C- , B- ,
A-
&
1 2 3 4 5 6 7 8 1/n
A+ B+ C+ D+ (D-) (B+) (B-)

(B+) (B+)
(C+)
OR
OR
A+ D+ C+ B+
&
1 2 3 4 5 6 7 8 2/n
A+ B+ C+ D+ (D-) (B+) (B-)

(A-) (B+) (B+) (A-)
(C+) Cell 1 : Unknown length of START.
May cause pulse on A+
SET RESET
Cell 2 : A- function opens a2
FLIP-FLOP Causes pulse on B+
SET RESET SET RESET
FLIP-FLOP FLIP-FLOP Cell 5 : D- function opens d2
Causes pulse on B+ and C+
A+ B+ D+ C+
13-7
13-8
13-9

INDUSTRIAL AUTOMATION 1 - אוטומציה תעשייתית 1

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CHAPTER 1 Motion Actuators

CHAPTER 5 Electrinc Ladder Diagrams

CHAPTER 6 Swquential Systems with Random

CHAPTER 7 Pneumatic Control Circuits

CHAPTER 10 Flexible Automation Programmable

CHAPTER 12 Robotics and Numerical Control

CHAPTER 13 Simester Exams

Various Methodes to Obtain Low-Cost Systems SW DPDT

Value Value RELAY SPST

2-Input AND 3-Input AND 2-Input NAND

a. Analog 2-Input OR 2-Input NOR Inverter

Fig. 0-2 Information Types

f. Pneumatic Limit Valves

Logic BINARY SENSORS :

(b) Relay SPDT

Fig. 0-4 Self Correction Fig. 0-3 Binary (Switching) Elements

Linear and Angular Motion

Electric Position Sensors

2. Universal Products of Sum :

e. Minimization - Math Operations i. Functions Basic Representations

Fig. 3-1 : Boolean Algebra Concepts

NATIONALITY A ISRAELI NON-ISRAELI * Merging two adjacent elements produces

Fig. 3-2 : Algebric Minimization (1)

c. Truth-Table d. Minimization Steps

C 2 C C C Fig. 3-7: Example 3

C C C Fig. 3-8 : Example 4

C C C Fig. 3-16 : Example 10

1 1 0 1 1 0 Y,Z d. Truth-Table (Partial)

c. Contact Circit Realization 01 0

Fig. 3-20 : BCD to 7-Segments

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