Adderessing Mode and Data Transfer Schemas 8085

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes
Module 1 learning unit 1 1 A Computer is a programmable machine. 2 The two principal characteristics of a computer are: !t responds to a specific set of instructions in a well"defined manner. # !t can e$ecute a prerecorded list of instructions %a program &. ' Modern computers are electronic and digital. ( The actual machiner) wires* transistors* and circuits is called hardware. the instructions and data are called software.
1 All general"purpose computers re+uire the following hardware components: 2 Memory: ,nables a computer to store* at least temporaril)* data and programs. Mass storage device: Allows a computer to permanentl) retain large amounts of data. -ommon mass storage de.ices include dis/ dri.es and tape dri.es. # Input device: 0suall) a /e)board and mouse are the input de.ice through which data and instructions enter a computer. ' Output device: A displa) screen* printer* or other de.ice that lets )ou see what the computer has accomplished. ( Central processing unit (CPU): The heart of the computer* this is the component that actuall) e$ecutes instructions. 1 !n addition to these components* man) others ma/e it possible for the basic components to wor/ together efficientl). 2 3or e$ample* e.er) computer re+uires a bus that transmits data from one part of the computer to another.
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terminals and other de.ices& sold to small and mid"si:e businesses 1 -omputers can be generall) for general business applications classified b) si:e and power as and to large enterprises for follows* though there is department"le.el operations. considerable o.erlap: # !n recent )ears* the minicomputer 2 Personal computer: A small* single" has e.ol.ed into the ;mid"range user computer based on a ser.er; and is part of a networ/. microprocessor. !6M<s A5/#99e is a good e$ample. !n addition to the ' The A5/#99 " formall) renamed the microprocessor* a personal ;!6M i5eries*; but still commonl) computer has a /e)board for /nown as A5/#99 " is a midrange entering data* a monitor for ser.er designed for small displa)ing information* and a businesses and departments in large storage de.ice for sa.ing data. enterprises and now redesigned so # Working station: A powerful* that it will wor/ well in distributed single"user computer. A networ/s with =eb applications. wor/station is li/e a personal ( The A5/#99 uses the >ower>computer* but it has a more microprocessor with its reduced powerful microprocessor and a instruction set computer higher"+ualit) monitor. technolog). !ts operating s)stem ' Minicomputer: A multi" is called the ?5/#99. user computer capable of 1 =ith multi"terab)tes of dis/ storage supporting from 19 to and a 8a.a .irtual memor) closel) hundreds of users tied into the operating s)stem* !6M simultaneousl). hopes to ma/e the A5/#99 a /ind of ( Mainframe: A powerful .ersatile all"purpose ser.er that can multi"user computer capable replace >- ser.ers and =eb ser.ers of supporting man) hundreds in the world<s businesses* competing or thousands of users with both =intel and 0ni$ ser.ers* simultaneousl). while gi.ing its present enormous 1 upercomputer: An customer base an immediate leap e$tremel) fast computer that into the !nternet. can perform hundreds of Workstation: millions of instructions per 1& A t)pe of computer used for second. engineering applications Minicomputer: %-A@/-AM&* des/top publishing* 1 A midsi:ed computer. !n si:e and software de.elopment* and other power* minicomputers lie between t)pes of applications that re+uire a wor/stations and mainframes. moderate amount of computing 2 A minicomputer* a term no longer power and relati.el) high +ualit) much used* is a computer of a si:e graphics capabilities. intermediate between a 1 =or/stations generall) come with a microcomputer and a mainframe. large* high" resolution graphics T)picall)* minicomputers ha.e screen* at least (# M6 %mega b)tes& been stand"alone computers of AAM* built"in networ/ support* %computer s)stems with attached and a graphical user interface.
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E Microcomputer: The term microcomputer is generall) 1 Most wor/stations also ha.e a mass s)non)mous with personal storage de.ice such as a dis/ dri.e* but computer* or a computer that a special t)pe of wor/station* called a depends on a microprocessor. dis/less wor/station* comes without a 19 Microcomputers are designed to be dis/ dri.e. used b) indi.iduals* whether in the 2 The most common operating s)stems form of >-s* wor/stations or for wor/stations are 0N!B and noteboo/ computers. =indows NT. 11 A microcomputer contains a ->0 on a !n terms of computing power* microchip %the microprocessor&* a wor/stations lie between personal memor) s)stem %t)picall) A?M and computers and minicomputers* AAM&* a bus s)stem and !/? ports* although the line is fu::) on both ends. t)picall) housed in a motherboard. # Cigh"end personal computers are 12 Microprocessor: A silicon chip that e+ui.alent to low"end wor/stations. contains a ->0. !n the world of And high"end wor/stations are personal computers* the terms e+ui.alent to minicomputers. microprocessor and ->0 are used ' Li/e personal computers* most interchangeabl). wor/stations are single"user computers. 1 A microprocessor %sometimes Cowe.er* wor/stations are t)picall) abbre.iated !P& is a digital electronic lin/ed together to form a local"area component with miniaturi:ed transistors networ/* although the) can also be used on a single semiconductor integrated as stand"alone s)stems. circuit %!-&. 2& !n networ/ing* workstation refers 1# ?ne or more microprocessors t)picall) to an) computer connected to a local" ser.e as a central processing unit %->0& area networ/. !t could be a in a computer s)stem or handheld wor/station or a personal computer. de.ice. ( Mainframe: A .er) large and e$pensi.e 1' Microprocessors made possible the computer capable of supporting ad.ent of the microcomputer. hundreds* or e.en thousands* of users 1( At the heart of all personal simultaneousl). !n the hierarch) that computers and most starts with a simple microprocessors %in wor/ing stations sits a watches* for e$ample& at the bottom and microprocessor. mo.es to supercomputer at the top* 11 Microprocessors also control the mainframes are Dust below logic of almost all digital de.ices* supercomputers. from cloc/ radios to fuel"inDection 1 !n some wa)s* mainframes are more s)stems for automobiles. powerful than supercomputers because 12 Three basic characteristics differentiate the) support more simultaneous microprocessors: programs. 1E Instruction set: The set of instructions 2 6ut supercomputers can e$ecute a that the microprocessor can e$ecute. single program faster than a 29 "and#idt$: The number of bits mainframe. The distinction between processed in a single instruction. small mainframes and minicomputers 21 Clock speed: Fi.en in megahert: is .ague* depending reall) on how the %MC:&* the cloc/ speed determines manufacturer wants to mar/et its how man) instructions per second the machines. processor can e$ecute.
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components* a microcontroller is designed for a .er) specific tas/ " to 1 !n both cases* the higher the .alue* the control a particular s)stem. more powerful the ->0. 3or e$ample* a 12 A microcontroller differs from a 2 bit microprocessor that runs at '9MC: microprocessor* which is a general" is more powerful than a 1("bit purpose chip that is used to create a microprocessor that runs at 2'MC:. multi"function computer or de.ice and 2 !n addition to bandwidth and cloc/ re+uires multiple chips to handle speed* microprocessors are classified as .arious tas/s. being either A!5- %reduced instruction 1 A microcontroller is meant to be set computer& or -!5- %comple$ more self"contained and instruction set computer&. independent* and functions as a upercomputer: A supercomputer tin)* dedicated computer. is a computer that performs at or 1# The great ad.antage of near the currentl) highest microcontrollers* as opposed to operational rate for computers. using larger microprocessors* is # A supercomputer is t)picall) used for that the parts"count and design scientific and engineering applications costs of the item being that must handle .er) large databases or controlled can be /ept to a do a great amount of computation %or minimum. both&. 1' The) are t)picall) designed using ' At an) gi.en time* there are usuall) a -M?5 %complementar) metal o$ide few well"publici:ed supercomputers semiconductor& technolog)* an efficient that operate at the .er) latest and fabrication techni+ue that uses less alwa)s incredible speeds. power and is more immune to power ( The term is also sometimes applied spi/es than other techni+ues. to far slower %but still impressi.el) 1( Microcontrollers are sometimes called fast& computers. embedded microcontrollers, which Dust 1 Most supercomputers are reall) means that the) are part of an multiple computers that perform embedded s)stem that is* one part of a parallel processing. larger de.ice or s)stem. 2 !n general* there are two 11 Controller: A de.ice that parallel processing controls the transfer of data from approaches: s)mmetric a computer to a peripheral de.ice multiprocessing %5M>& and and .ice .ersa. massi.el) parallel 12 3or e$ample* dis/ dri.es* displa) processing %M>>&. screens* /e)boards and printers E Microcontroller: A highl) all re+uire controllers. integrated chip that contains all the 1E !n personal computers* the controllers components comprising a are often single chips. controller. 29 =hen )ou purchase a computer* it 19 T)picall) this includes a ->0* AAM* comes with all the necessar) some form of A?M* !/? ports* and controllers for standard components* timers. such as the displa) screen* /e)board* 11 0nli/e a general"purpose computer* and dis/ dri.es. which also includes all of these
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per second& than standard serial and parallel ports. !n addition* )ou can 1 !f )ou attach additional de.ices* attach man) de.ices to a single 5-5! howe.er* )ou ma) need to insert new port* so that 5-5! is reall) an !/? bus controllers that come on e$pansion rather than simpl) an interface boards. 1 Although 5-5! is an AN5! standard* 2 -ontrollers must be designed to there are man) .ariations of it* so two communicate with the computer<s 5-5! interfaces ma) be incompatible. e$pansion bus. 1# 3or e$ample* 5-5! supports se.eral There are three standard bus t)pes of connectors. architectures for >-s " the AT bus* >-! 1' =hile 5-5! has been the standard %>eripheral -omponent !nterconnect & interface for Macintoshes* the iMac and 5-5!. comes with IDE* a less e$pensi.e # =hen )ou purchase a controller* interface* in which the controller is therefore* )ou must ensure that it integrated into the dis/ or -@"A?M conforms to the bus architecture that dri.e. )our computer uses. 1( The following .arieties of 5-5! are ' 5hort for Peripheral Component currentl) implemented: Interconnect, a local bus standard 11 5-5!"1: 0ses an 2"bit bus* and supports de.eloped b) !ntel -orporation. data rates of # M6ps. ( Most modern >-s include a >-! bus in 12 5-5!"2: 5ame as 5-5!"1* but uses a addition to a more general !A5 '9"pin connector instead of a 2'"pin e$pansion bus. connector* and supports multiple 1 >-! is also used on newer .ersions of the de.ices. This is what most people Macintosh computer. mean when the) refer to plain SCSI. 2 >-! is a (#"bit bus* though it is usuall) 1E =ide 5-5!: 0ses a wider cable implemented as a 2 bit bus. !t can run %1(2 cable lines to (2 pins& to at cloc/ speeds of or (( MC:. support 1("bit transfers. E At 2 bits and MC:* it )ields a29 3ast 5-5!: 0ses an 2"bit bus* but throughput rate of 1 M6ps. doubles the cloc/ rate to support data 19 5hort for small computer system rates of 19 M6ps. interface* a parallel interface standard 21 3ast =ide 5-5!: 0ses a 1("bit bus and used b) Apple Macintosh computers* supports data rates of 29 M6ps. >-s* and man) 0N!B s)stems for 22 0ltra 5-5!: 0ses an 2"bit bus* and attaching peripheral de.ices to supports data rates of 29 M6ps. computers. 2 =ide 0ltra2 5-5!: 0ses a 1("bit bus 11 Nearl) all Apple Macintosh computers* and supports data rates of 29 M6ps. e$cluding onl) the earliest Macs and the 2# 5-5!" : 0ses a 1("bit bus and recent iMac* come with a 5-5! port for supports data rates of #9 M6ps. Also attaching de.ices such as dis/ dri.es called Ultra Wide SCSI. and printers. 2' 0ltra2 5-5!: 0ses an 2"bit bus and 12 5-5! interfaces pro.ide for faster data supports data rates of #9 M6ps. transmission rates %up to 29 megab)tes
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1 %m&edded system: A speciali:ed computer s)stem that is part of a larger s)stem or machine. 2 T)picall)* an embedded s)stem is housed on a single microprocessor board with the programs stored in A?M. 7irtuall) all appliances that ha.e a digital !nterface" watches* microwa.es* 7-As* cars "utili:e embedded s)stems. # 5ome embedded s)stems include an operating s)stem* but man) are so speciali:ed that the entire logic can be implemented as a single program.
MIC'O CO()'O**%' MIC'O P'OC% !t is a single chip !t is a ->0 -onsists Memor)* Memor)* !/? >orts to be !/o ports connected e$ternall)
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Definitions: 1 A -igital ignal Processor is a special"purpose ->0 %-entral >rocessing 0nit& that pro.ides ultra"fast instruction se+uences* such as shift and add* and multipl) and add* which are commonl) used in math"intensi.e signal processing applications. 2 A digital signal processor %- P& is a speciali:ed microprocessor designed specificall) for digital signal processing* generall) in real time. Digital G operating by the use of discrete signals to represent data in the form of
numbers. Signal G a ariable parameter by which information is con eyed through an electronic circuit. Processing G to perform operations on data according to programmed instructions. -igital ignal processing G changing or anal)sing information which is measured as discrete se+uences of numbers. 1 -igital signal processing %@5>& is the stud) of signals in a digital representation and the processing methods of these signals. 2 @5> and analog signal processing are subfields of signal processing.
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@5> has three maDor subfields: 1 Audio signal processing* @igital image processing and 5peech processing. 2 5ince the goal of @5> is usuall) to measure or filter continuous real"world analog signals* the first step is usuall) to con.ert the signal from an analog to a digital form* b) using an analog to digital con.erter. ?ften* the re+uired output signal is another analog output signal* which re+uires a digital to analog con.erter. C$aracteristics of -igital ignal Processors: 1 5eparate program and data memories %Car.ard architecture&. 2 5pecial !nstructions for 5!M@ %5ingle !nstruction* Multiple @ata& operations. ?nl) parallel processing* no multitas/ing. # The abilit) to act as a direct memor) access de.ice if in a host en.ironment. ' Ta/es digital data from A@- %Analog"@igital -on.erter& and passes out data which is finall) output b) con.erting into analog b) @A- %@igital"Analog -on.erter&. ( analog input""HA@-""H@5>""H@A-""H analog output.
.nalog front end .nalo g signal in .ntialiasing filter/ ,0/ .,converter
- P Processor
.nalog &ack end -,. converter/ reconstruction filter
.na log sign al out put
Multiply-accumulate hardware: 1 Multipl) accumulate is the most fre+uentl) used operation in digital signal
p r o @A> c 5)st e em s s i n g . 2 ! n
order to impl emen t this effici entl)* the @5> has an hard ware
multiplier* an accumulator with an ade+uate number of bits to hold the sum of products and at e$plicit multipl)" accumulate instructions. Harvard architecture: in this memor) architecture* there are two memor) spaces. >rogram memor) and data memor).
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1 The processor core connects to these memor) spaces b) two separate bus sets* allowing two simultaneous
access to memor). This arrangement relati.el) small loops. doubles the processor memor) bandwidth. 2 The term :ero o.erhead looping means that the processor can e$ecute loops without consuming 1 Zero-overhead looping: one common c)cles to test the .alue of the loop characteristics of @5> algorithms is that counter* perform a conditional most of the processing time is split on branch to the top of the loop* and e$ecuting instructions contained with decrement the loop counter.
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Processi ng unit
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1 The ad.antages @5> are: :ersatility: 2 digital s)stems can be reprogrammed for other applications %at least where
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program mable @5> chips are used& digital s)stems can be ported to different hardware %for
e different @5> chip or $ board le.el product& a 'epeata&ility: m 1 digital s)stems can be easil) duplicated p s)stem l 2 digital responses do not drift e with temperature a
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digital s)stems do not depend on strict component tolerances. implicity: 1 some things can be done more easil) digitall) than with analogue s)stems 2 @5> is used in a .er) wide .ariet) of applications but most share some common features: the) use a lot of multipl)ing and adding signals. # the) deal with signals that come from the real world. ' the) re+uire a response in a certain time.
3igure: A bloc/ diagram %or dataflow graph&

1 =hat is the difference between a @5> and a microprocessor I 2 The essential difference between a @5> and a microprocessor is that a @5> processor has features designed to support high"performance* repetiti.e* numericall) intensi.e tas/s. !n contrast* general"purpose processors or microcontrollers %F>>s / M-0s for short& are either not speciali:ed for a specific /ind of applications %in the case of general"purpose processors&* or the) are designed for control"oriented applications %in the case of microcontrollers&. # 3eatures that accelerate performance in @5> applications include: ' 5ingle"c)cle multipl)"accumulate capabilit)J high"performance @5>s often ha.e
two multipliers that enable two multipl)"accumulate operations per instruction c)cleJ some @5> ha.e four or more multipliers. 1 5peciali:ed addressing modes* for e$ample* pre" and post"modification of address pointers* circular addressing* and bit"re.ersed addressing. 2 Most @5>s pro.ide .arious configurations of on"chip memor) and peripherals tailored for @5> applications. @5>s generall) feature multiple"access memor) architectures that enable @5>s to complete se.eral accesses to memor) in a single instruction c)cle.
1 5peciali:ed e$ecution control. 0suall)* @5> processors pro.ide a loop instruction that allows tight loops to be repeated without spending an) instruction c)cles for updating and testing the loop counter or for Dumping bac/ to the top of the loop 2 @5> processors are /nown for their irregular instruction sets* which generall) allow se.eral operations to be encoded in a single instruction. 3or e$ample* a processor that uses 2"bit instructions ma) encode two additions* two multiplications* and four 1("bit data mo.es into a single instruction. # !n general* @5> processor instruction sets allow a data mo.e to be performed in parallel with an arithmetic operation. F>>s / M-0s* in contrast* usuall) specif) a single operation per instruction. ' =hat is reall) important is to choose the processor that is best suited for )our application. ( !f a F>>/M-0 is better suited for )our @5> application than a @5> processor* the processor of choice is the F>>/M-0. 1 !t is also worth noting that the difference between @5>s and F>>s/M-0s is fading: man) F>>s/M-0s now include @5> features* and @5>s are increasingl) adding microcontroller features. Module 1: learning unit 2 868; Microprocessor ContentsFeneral definitions 1 ?.er.iew of 292' microprocessor 2 ?.er.iew of 292( microprocessor 5ignals and pins of 292( microprocessor The salient features of 292' Kp are: # !t is a 2 bit microprocessor. ' !t is manufactured with N"M?5 technolog). ( !t has 1("bit address bus and hence can address up to 21( L ('' ( b)tes %(#46& memor) locations through A9"A1'. 1 The first 2 lines of address bus and 2 lines of data bus are multiple$ed A@ 9 G A@1. 2 @ata bus is a group of 2 lines @9 G @1. E !t supports e$ternal interrupt re+uest. 19 A 1( bit program counter %>-& 11 A 1( bit stac/ pointer %5>& 12 5i$ 2"bit general purpose register arranged in pairs: 6-* @,* CL. 1 !t re+uires a signal M'7 power suppl) and operates at .2 MCN single phase cloc/. 1# !t is enclosed with #9 pins @!> %@ual in line pac/age&. Overvie# of 868; microprocessor 292' Architecture 1 >in @iagram 2 3unctional 6loc/ @iagram
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M. 4rishna 4umar/!!5c.
6angalore 9#/1'
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Memory 1 >rogram* data and stac/ memories occup) the same memor) space. The total addressable memor) si:e is (# 46. 2 Program memory " program can be located an)where in memor). 8ump* branch and call instructions use 1("bit addresses* i.e. the) can be used to Dump/branch an)where within (# 46. All Dump/branch instructions use absolute addressing. -ata memory " the processor alwa)s uses 1("bit addresses so that data can be placed an)where. # tack memory is limited onl) b) the si:e of memor). 5tac/ grows downward. ' 3irst (# b)tes in a :ero memor) page should be reser.ed for .ectors used b) A5T instructions. Interrupts 1 The processor has ' interrupts. The) are presented below in the order of their priorit) %from lowest to highest&: 1 I()' is mas/able 2929A compatible interrupt. =hen the interrupt occurs the processor fetches from the bus one instruction* usuall) one of these instructions: 2 ?ne of the 2 A5T instructions %A5T9 " A5T1&. The processor sa.es current program counter into stac/ and branches to memor) location N O 2 %where N is a "bit number from 9 to 1 supplied with the A5T instruction&. C.** instruction % b)te instruction&. The processor calls the subroutine* address of which is specified in the second and third b)tes of the instruction. # ' );?; is a mas/able interrupt. =hen this interrupt is recei.ed the processor sa.es the contents of the >- register into stac/ and branches to 2-C %he$adecimal& address. ' ' )3?; is a mas/able interrupt. =hen this interrupt is recei.ed the processor sa.es the contents of the >- register into stac/ and branches to #C %he$adecimal& address. ( ' )=?; is a mas/able interrupt. =hen this interrupt is recei.ed the processor sa.es the contents of the >- register into stac/ and branches to -C %he$adecimal& address. 1 )'.P is a non"mas/able interrupt. =hen this interrupt is recei.ed the processor sa.es the contents of the >- register into stac/ and branches to 2#C %he$adecimal& address. 2 All mas/able interrupts can be enabled or disabled using ,! and @! instructions. A5T '.'* A5T(.' and A5T1.' interrupts can be enabled or disabled indi.iduall) using 5!M instruction. 'eset ignals 1 '% %) I(: =hen this signal goes low* the program counter %>-& is set to Nero* Kp is reset and resets the interrupt enable and CL@A flip"flops. 2 The data and address buses and the control lines are "stated during A,5,T and because of as)nchronous nature of A,5,T* the processor internal registers and flags ma) be altered b) A,5,T with unpredictable results. A,5,T !N is a 5chmitt"triggered input* allowing connection to an A"- networ/ for power"on A,5,T dela).
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/1(
the C?L@ re+uest and that it will relin+uish the bus in the ne$t 1 0pon power"up* A,5,T !N must cloc/ c)cle. remain low for at least 19 ms after ' CL@A goes low after the Cold minimum 7cc has been reached. re+uest is remo.ed. The ->0 ta/es 2 3or proper reset operation after the the bus one half"cloc/ c)cle after power G up duration* A,5,T !N CL@A goes low. should be /ept low a minimum of ( '%.-+: This signal three cloc/ periods. 5)nchroni:es the fast ->0 The ->0 is held in the reset condition and the slow memor)* as long as A,5,T !N is applied. peripherals. T)pical >ower"on A,5,T A- .alues 1 !f A,A@P is high during a read or A1 L 1'4* -1 L 1K3. write c)cle* it indicates that the # '% %) OU): This signal indicates that memor) or peripheral is read) to Kp is being reset. This signal can be used send or recei.e data. to reset other de.ices. The signal is 2 !f A,A@P is low* the ->0 will s)nchroni:ed to the processor cloc/ and wait an integral number of lasts an integral number of cloc/ periods. cloc/ c)cle for A,A@P to go erial communication ignal high before completing the read 1 I- B erial Input -ata *ine: The data or write c)cle. on this line is loaded into accumulator bit E A,A@P must conform to specified 1 whene.er a A!M instruction is setup and hold times. e$ecuted. 'egisters 2 O- F erial Output -ata *ine : The 5!M instruction loads the .alue of bit 1 1 .ccumulator or A register is an 2"bit register used for arithmetic* logic* !/? of the accumulator into 5?@ latch if bit and load/store operations. ( %5?,& of the accumulator is 1. 2 Clag 'egister has fi.e 1"bit flags. -M. ignals ign " set if the most significant bit of 1 0O*-: !ndicates that another master is the result is set. re+uesting the use of the address and data # Dero " set if the result is :ero. buses. The ->0* upon recei.ing the hold re+uest* will relin+uish the use of the bus ' .u9iliary carry " set if there was a carr) out from bit to bit # of the as soon as the completion of the current result. bus transfer. ( Parity " set if the parit) %the number of 2 !nternal processing can continue. The set bits in the result& is e.en. processor can regain the bus onl) after 1 Carry " set if there the C?L@ is remo.ed. was a carr) during =hen the C?L@ is ac/nowledged* the addition* or borrow Address* @ata A@* =A and !?/M lines during are "stated. subtraction/compariso # 0*-.: 0old .ckno#ledge: n/rotation. !ndicates that the ->0 has recei.ed
7eneral 'egisters 1 2"bit 6 and 2"bit - registers can be used as one 1("bit 6- register pair. =hen used as a pair the - register contains low"order b)te. 5ome instructions ma) use 6- register as a data pointer. 2 2"bit @ and 2"bit , registers can be used as one 1("bit @, register pair. =hen used as a pair the , register contains low"order b)te. 5ome instructions ma) use @, register as a data pointer. 2"bit C and 2"bit L registers can be used as one 1("bit CL register pair. =hen used as a pair the L register contains low"order b)te. CL register usuall) contains a data pointer used to reference memor) addresses. # tack pointer is a 1( bit register. This register is alwa)s decremented/incremented b) 2 during push and pop. ' Program counter is a 1("bit register. Instruction et 1 292' instruction set consists of the following instructions: 2 @ata mo.ing instructions. Arithmetic " add* subtract* increment and decrement. # Logic " AN@* ?A* B?A and rotate. ' -ontrol transfer " conditional* unconditional* call subroutine* return from subroutine and restarts. ( !nput/?utput instructions. 1 ?ther " setting/clearing flag bits* enabling/disabling interrupts* stac/ operations* etc. .ddressing mode 1 'egister " references the data in a register or in a register pair. 'egister indirect " instruction specifies register pair containing address* where the data is located. -irect/ Immediate " 2 or 1("bit data. Module 1: learning unit 8683 Microprocessor !t is a 1("bit Kp.
292( has a 29 bit address bus can access up to 2 memor) locations %1 M6&. !t can support up to (#4 !/? ports. !t pro.ides 1#* 1( "bit registers. !t has multiple$ed address and data bus A@9" A@1' and A1( G A1E. !t re+uires single phase cloc/ with Q dut) c)cle to pro.ide internal timing. 292( is designed to operate in two modes* Minimum and Ma$imum. !t can prefetches upto ( instruction b)tes from memor) and +ueues them in order to speed up instruction e$ecution. !t re+uires M'7 power suppl). A #9 pin dual in line pac/age Minimum and Ma9imum Modes: The minimum mode is selected b) appl)ing logic 1 to the MN / MB input pin. This is a single microprocessor configuration. The ma$imum mode is selected b) appl)ing logic 9 to the MN / MB input pin. This is a multi micro processors configuration. M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/12
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Microprocessors and Microcontrollers/Architecture of Microprocessors
Lecture Notes
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"lock -iagram of 8683 Internal .rc$itecture of 8683 292( has two bloc/s 6!0 and ,0. The 6!0 performs all bus operations such as instruction fetching* reading and
writing operands for memor) and calculating the addresses of the memor) operands. The instruction b)tes are transferred to the instruction +ueue. ,0 e$ecutes instructions from the instruction s)stem b)te +ueue. 6oth units operate as)nchronousl) to gi.e the 292( an o.erlapping instruction fetch and e$ecution mechanism which is called as >ipelining. This results in efficient use of the s)stem bus and s)stem performance. 6!0 contains !nstruction +ueue* 5egment registers* !nstruction pointer* Address adder. ,0 contains -ontrol circuitr)* !nstruction decoder* AL0* >ointer and !nde$ register* 3lag register. "U I()%'C.C' U(I): !t pro.ides a full 1( bit bidirectional data bus and 29 bit address bus. The bus interface unit is responsible for performing all e$ternal bus operations. Specifically it has the following functions: !nstruction fetch* !nstruction +ueuing* ?perand fetch and storage* Address relocation and 6us control. The 6!0 uses a mechanism /nown as an instruction stream +ueue to implement a pipeline architecture. This +ueue permits prefetch of up to si$ b)tes of instruction code. =hen e.er the +ueue of the 6!0 is not full* it has room for at least two more b)tes and at the same time the ,0
is not re+uesting it to read or write operands from memor)* the 6!0 is free to loo/ ahead in the program b) prefetching the ne$t se+uential instruction. These prefetching instructions are held in its 3!3? +ueue. =ith its 1( bit data bus* the 6!0 fetches two instruction b)tes in a single memor) c)cle. After a b)te is loaded at the input end of the +ueue* it automaticall) shifts up through the 3!3? to the empt) location nearest the output. The ,0 accesses the +ueue from the output end. !t reads one instruction b)te after the other from the output of the +ueue. !f the +ueue is full and the ,0 is not re+uesting access to operand in memor). These inter.als of no bus acti.it)* which ma) occur between bus c)cles are /nown as Idle state. !f the 6!0 is alread) in the process of fetching an instruction when the ,0 re+uest it to read or write operands from memor) or !/?* the 6!0 first completes the instruction fetch bus c)cle before initiating the operand read / write c)cle. The 6!0 also contains a dedicated adder which is used to generate the 29bit ph)sical address that is output on the address bus. This address is formed b) adding an appended 1( bit segment address and a 1( bit offset address. 3or e$ample: The ph)sical address of the ne$t instruction to be fetched is formed b) combining the current contents of the code segment -5 register and the current contents of the instruction pointer !> register. The 6!0 is also responsible for generating bus control signals such as those for memor) read or write and !/? read or write. %1%CU)IO( U(I) The ,$ecution unit is responsible for decoding and e$ecuting all instructions. The ,0 e$tracts instructions from the top of the +ueue in the 6!0* decodes them* generates operands if necessar)* passes them to the 6!0 and re+uests it to perform the read or write b)s c)cles to memor) or !/? and perform the operation specified b) the instruction on the operands. @uring the e$ecution of the instruction* the ,0 tests the status and control flags and updates them based on the results of e$ecuting the instruction. !f the +ueue is empt)* the ,0 waits for the ne$t instruction b)te to be fetched and shifted to top of the +ueue. =hen the ,0 e$ecutes a branch or Dump instruction* it transfers control to a location corresponding to another set of se+uential instructions. =hene.er this happens* the 6!0 automaticall) resets the +ueue and then begins to fetch instructions from this new location to refill the +ueue. Module 1 and learning unit #: ignal -escription of 8683The Microprocessor 292( is a 1("bit ->0 a.ailable in different cloc/ rates and pac/aged in a #9 pin -,A@!> or plastic pac/age. The 292( operates in single processor or multiprocessor configuration to achie.e high performance. The pins ser.e a particular function in minimum mode %single processor mode& and other function in ma$imum mode configuration %multiprocessor mode &. The 292( signals can be categorised in three groups. The first are the signal ha.ing common functions in minimum as well as ma$imum mode. The second are the signals which ha.e special functions for minimum mode and third are the signals ha.ing special functions for ma$imum mode.
)$e follo#ing signal descriptions are common for &ot$ modes? .-1;B.-6: These are the time multiple$ed memor) !/? address and data lines. Address remains on the lines during T1 state* while the data is a.ailable on the data bus during T2* T * Tw and T#. These lines are acti.e high and float to a tristate during interrupt ac/nowledge and local bus hold ac/nowledge c)cles. .1<, 3/.18, ;/.1=, 5/.13, 4: These are the time multiple$ed address and status lines. @uring T1 these are the most significant address lines for memor) operations. @uring !/? operations* these lines are low. @uring memor) or !/? operations* status information is a.ailable on those lines for T2*T *Tw and T#. The status of the interrupt enable flag bit is updated at the beginning of each cloc/ c)cle. The 5# and 5 combinedl) indicate which segment register is presentl) being used for memor) accesses as in below fig. These lines float to tri"state off during the local bus hold ac/nowledge. The status line 5( is alwa)s low. The address bit are separated from the status bit using latches controlled b) the AL, signal.
5
4
6 6 1 1
6 1 6 1
Indication .lternate -ata tack Code or none -ata
"0% , =: The bus high enable is used to indicate the transfer of data o.er the higher order % @1'"@2 & data bus as shown in table. !t goes low for the data transfer o.er @1'" @2 and is used to deri.e chip selects of odd address memor) ban/ or peripherals. 6C, is low during T1 for read* write and interrupt ac/nowledge c)cles* whene.er a b)te is to be transferred on higher b)te of data bus. The status information is a.ailable during T2* T and T#. The signal is acti.e low and tristated during hold. !t is low during T1 for the first pulse of the interrupt ac/nowledges c)cle.
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W$ole #ord Upper &yte from or to oddevenaddresss *o#er &yte from or to even address (one
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'- 'ead: This signal on low indicates the peripheral that the processor is performing s memor) or !/? read operation. A@ is acti.e low and shows the state for T2* T * Tw of an) read c)cle. The signal remains tristated during the hold ac/nowledge.
'%.-+: This is the ac/nowledgement from the slow de.ice or memor) that the) ha.e completed the data transfer. The signal made a.ailable b) the de.ices is s)nchroni:ed b) the 222#A cloc/ generator to pro.ide read) input to the 292(. the signal is acti.e high. I()'BInterrupt 'eHuest: This is a triggered input. This is sampled during the last cloc/ c)cles of each instruction to determine the a.ailabilit) of the re+uest. !f an) interrupt re+uest is pending* the processor enters the interrupt ac/nowledge c)cle. This can be internall) mas/ed b) resulting the interrupt enable flag. This signal is acti.e high and internall) s)nchroni:ed. )% ) This input is e$amined b) a R=A!TS instruction. !f the T,5T pin goes low* e$ecution will continue* else the processor remains in an idle state. The input is s)nchroni:ed internall) during each cloc/ c)cle on leading edge of cloc/. C*>" -loc/ !nput: The cloc/ input pro.ides the basic timing for processor operation and bus control acti.it). !ts an as)mmetric s+uare wa.e with Q dut) c)cle. M(, M1 : The logic le.el at this pin decides whether the processor is to operate in either minimum or ma$imum mode. I)$e follo#ing pin functions are for t$e minimum mode operation of 8683? M, IO F Memory,IO: This is a status line logicall) e+ui.alent to 52 in ma$imum mode. =hen it is low* it indicates the ->0 is ha.ing an !/? operation* and when it is high* it indicates that the ->0 is ha.ing a memor) operation. This line becomes acti.e high in the pre.ious T# and remains acti.e till final T# of the current c)cle. !t is tristated during local bus Thold ac/nowledge T. I(). Interrupt .ckno#ledge: This signal is used as a read strobe for interrupt ac/nowledge c)cles. i.e. when it goes low* the processor has accepted the interrupt. .*% F .ddress *atc$ %na&le: This output signal indicates the a.ailabilit) of the .alid address on the address/data lines* and is connected to latch enable input of latches. This signal is acti.e high and is ne.er tristated. -), ' F -ata )ransmit,'eceive: This output is used to decide the direction of data flow through the transrecei.ers %bidirectional buffers&. =hen the processor sends out data* this signal is high and when the processor is recei.ing data* this signal is low. -%( F -ata %na&le: This signal indicates the a.ailabilit) of .alid data o.er the address/data lines. !t is used to enable the transrecei.ers % bidirectional buffers & to separate the data from the multiple$ed address/data signal. !t is acti.e from the middle of T2 until the middle of T#. This is tristated during R hold ac/nowledgeS c)cle. 0O*-/ 0*-.B .ckno#ledge: =hen the C?L@ line goes high* it indicates to the processor that another master is re+uesting the bus access. The processor* after recei.ing the C?L@ re+uest* issues the hold ac/nowledge signal on CL@A pin* in the middle of the ne$t cloc/ c)cle after completing the current bus c)cle.At the same time* the processor floats the local bus and control lines. =hen the processor detects the C?L@ line low* it lowers the CL@A signal. C?L@ is an as)nchronous input* and is should be e$ternall) s)nchroni:ed. !f the @MA re+uest is made while the ->0 is performing a memor) or !/? c)cle* it will release the local bus during T# pro.ided: 1.The re+uest occurs on or before T2 state of the current c)cle. 2.The current c)cle is not operating o.er the lower b)te of a word. .The current c)cle is not the first ac/nowledge of an interrupt ac/nowledge se+uence.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/2#
#. A Loc/ instruction is not being e$ecuted. he following pin function are applica!le for ma"imum mode operation of #$#%. 2/ 1/ 6 F tatus *ines : These are the status lines which reflect the t)pe of operation* being carried out b) the processor. These become acti.it) during T# of the pre.ious c)cle and acti.e during T1 and T2 of the current bus c)cles.
2 1 6
6 6 6 6 1
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*OC> This output pin indicates that other s)stem bus master will be pre.ented from gaining the s)stem bus* while the L?-4 signal is low. The L?-4 signal is acti.ated b) the RL?-4S prefi$ instruction and remains acti.e until the completion of the ne$t instruction. =hen the ->0 is e$ecuting a critical instruction which re+uires the s)stem bus* the L?-4 prefi$ instruction ensures that other processors connected in the s)stem will not gain the control of the bus. The 292(* while e$ecuting the prefi$ed instruction* asserts the bus loc/ signal output* which ma) be connected to an e$ternal bus controller.
IG 1/ G 6 F Gueue tatus: These lines gi.e information about the status of the code"
prefetch +ueue. These are acti.e during the -L4 c)cle after while the +ueue operation is performed. IThis modification in a simple fetch and e$ecute architecture of a con.entional microprocessor offers an added ad.antage of pipelined processing of the instructions. IThe 292( architecture has ("b)te instruction prefetch +ueue. Thus e.en the largest %( " b)tes& instruction can be prefetched from the memor) and stored in the prefetch. This results in a faster e$ecution of the instructions. I!n 292' an instruction is fetched* decoded and e$ecuted and onl) after the e$ecution of this instruction* the ne$t one is fetched. 6) prefetching the instruction* there is a considerable speeding up in instruction e$ecution in 292(. This is /nown as instruction pipelining. At the starting the -5:!> is loaded with the re+uired address from which the e$ecution is to be started. !nitiall)* the +ueue will be empt) an the microprocessor starts a fetch operation to bring one b)te %the first b)te& of instruction code* if the -5:!> address is odd or two b)tes at a time* if the -5:!> address is e.en. The first b)te is a complete opcode in case of some instruction %one b)te opcode instruction& and is a part of opcode* in case of some instructions % two b)te opcode instructions&* the remaining part of code lie in second b)te. The second b)te is then decoded in continuation with the first b)te to decide the instruction length and the number of subse+uent b)tes to be treated as instruction data.
M. 4rishna 4umar/!!5c. 6angalore
M1/71/8une 9#/2'
The +ueue is updated after e.er) b)te is read from the +ueue but the fetch c)cle is initiated b) 6!0 onl) if at least two b)tes of the +ueue are empt) and the ,0 ma) be concurrentl) e$ecuting the fetched instructions. The ne$t b)te after the instruction is completed is again the first opcode b)te of the ne$t instruction. A similar procedure is repeated till the complete e$ecution of the program.The fetch operation of the ne$t instruction is o.erlapped with the e$ecution of the current instruction. As in the architecture* there are two separate units* namel) ,$ecution unit and 6us interface unit. =hile the e$ecution unit is bus) in e$ecuting an instruction* after it is completel) decoded* the bus interface unit ma) be fetching the b)tes of the ne$t instruction from memor)* depending upon the +ueue status.
G
6 6
1
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'G , 7)6 / 'G , 7)1 F 'eHuest,7rant: These pins are used b) the other local bus master in ma$imum mode* to force the processor to release the local bus at the end of the processor current bus c)cle. ,ach of the pin is bidirectional with AU/FT9 ha.ing higher priorit) than AU/FT1. AU/FT pins ha.e internal pull"up resistors and ma) be left unconnected. 'eHuest,7rant seHuence is as follo#s: 1.A pulse of one cloc/ wide from another bus master re+uests the bus access to 292(. 2.@uring T#%current& or T1%ne$t& cloc/ c)cle* a pulse one cloc/ wide from 292( to the re+uesting master* indicates that the 292( has allowed the local bus to float and that it will enter the Rhold ac/nowledgeS state at ne$t c)cle. The ->0 bus interface unit is li/el) to be disconnected from the local bus of the s)stem. .A one cloc/ wide pulse from the another master indicates to the 292( that the hold re+uest is about to end and the 292( ma) regain control of the local bus at the ne$t cloc/ c)cle. Thus each master to master e$change of the local bus is a se+uence of pulses. There must be at least one dead cloc/ c)cle after each bus e$change. The re+uest and grant pulses are acti.e low. 3or the bus re+uest those are recei.ed while 292( is performing memor) or !/? c)cle* the granting of the bus is go.erned b) the rules as in case of C?L@ and CL@A in minimum mode. 7eneral "us Operation: The 292( has a combined address and data bus commonl) referred as a time multiple$ed address and data bus. The main reason behind multiple$ing address and data o.er the same pins is the ma$imum utilisation of processor pins and it facilitates the use of #9 pin standard @!> pac/age.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/2(
The bus can be demultiple$ed using a few latches and transrecei.ers* when e.er re+uired. 6asicall)* all the processor bus c)cles consist of at least four cloc/ c)cles. These are referred to as T1* T2* T * T#. The address is transmitted b) the processor during T1. !t is present on the bus onl) for one c)cle. The negati.e edge of this AL, pulse is used to separate the address and the data or status information. !n ma$imum mode* the status lines 59* 51 and 52 are used to indicate the t)pe of operation. 5tatus bits 5 to 51 are multiple$ed with higher order address bits and the 6C, signal. Address is .alid during T1 while status bits 5 to 51 are .alid during T2 through T#.
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Minimum Mode 8683 ystem !n a minimum mode 292( s)stem* the microprocessor 292( is operated in minimum mode b) strapping its MN/MB pin to logic 1.
!n this mode* all the control signals are gi.en out b) the microprocessor chip itself. There is a single microprocessor in the minimum mode s)stem. The remaining components in the s)stem are latches* transrecei.ers* cloc/ generator* memor) and !/? de.ices. 5ome t)pe of chip selection logic ma) be re+uired for selecting memor) or !/? de.ices* depending upon the address map of the s)stem. Latches are generall) buffered output @"t)pe flip"flops li/e 1#L5 1 or 2222. The) are used for separating the .alid address from the multiple$ed address/data signals and are controlled b) the AL, signal generated b) 292(.
Transrecei.ers are the bidirectional buffers and some times the) are called as data amplifiers. The) are re+uired to separate the .alid data from the time multiple$ed address/data signals. The) are controlled b) two signals namel)* @,N and @T/A. The @,N signal indicates the direction of data* i.e. from or to the processor. The s)stem contains memor) for the monitor and users program storage. 0suall)* ,>A?M are used for monitor storage* while AAM for users program storage. A s)stem ma) contain !/? de.ices. The wor/ing of the minimum mode configuration s)stem can be better described in terms of the timing diagrams rather than +ualitati.el) describing the operations. The opcode fetch and read c)cles are similar. Cence the timing diagram can be categori:ed in two parts* the first is the timing diagram for read c)cle and the second is the timing diagram for write c)cle. The read c)cle begins in T1 with the assertion of address latch enable %AL,& signal and also M / !? signal. @uring the negati.e going edge of this signal* the .alid address is latched on the local bus. The 6C, and A9 signals address low* high or both b)tes. 3rom T1 to T# * the M/!? signal indicates a memor) or !/? operation. At T2* the address is remo.ed from the local bus and is sent to the output. The bus is then tristated. The read %A@& control signal is also acti.ated in T2. The read %A@& signal causes the address de.ice to enable its data bus dri.ers. After A@ goes low* the .alid data is a.ailable on the data bus. The addressed de.ice will dri.e the A,A@P line high. =hen the processor returns the read signal to high le.el* the addressed de.ice will again tristate its bus dri.ers. A write c)cle also begins with the assertion of AL, and the emission of the address. The M/!? signal is again asserted to indicate a memor) or !/? operation. !n T2* after sending the address in T1* the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T# state. The =A becomes acti.e at the beginning of T2 %unli/e A@ is somewhat dela)ed in T2 to pro.ide time for floating&. The 6C, and A9 signals are used to select the proper b)te or b)tes of memor) or !/? word to be read or write. The M/!?* A@ and =A signals indicate the t)pe of data transfer as specified in table below.
M1/71/8une 9#/22
M. 4rishna 4umar/!!5c. 6angalore
Lecture Notes
) )1 Clk .*% "0% .1< F .13

=
)2
)W
)5
)1
.-- , ).)U .-- , -.). W ' -%(
.1; F .6
:alid data -1; F -6
-) , '
=rite -)cle Timing @iagram for Minimum Mode

Hold &esponse se'uence: The C?L@ pin is chec/ed at leading edge of each cloc/ pulse. !f it is recei.ed acti.e b) the processor before T# of the pre.ious c)cle or during T1 state of the current c)cle* the ->0 acti.ates CL@A in the ne$t cloc/ c)cle and for succeeding bus c)cles* the bus will be gi.en to another re+uesting master. The control of the bus is not regained b) the processor until the re+uesting master does not drop the C?L@ pin low. =hen the re+uest is dropped b) the re+uesting master* the CL@A is dropped b) the processor at the trailing edge of the ne$t cloc/.
Clk
0O*-
0*-.
6us Ae+uest and 6us Frant Timings in Minimum Mode 5)stem

M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/2E
Ma9imum Mode 8683 ystem !n the ma$imum mode* the 292( is operated b) strapping the MN/MB pin to ground. !n this mode* the processor deri.es the status signal 52* 51* 59. Another chip called bus controller deri.es the control signal using this status information. !n the ma$imum mode* there ma) be more than one microprocessor in the s)stem configuration. The components in the s)stem are same as in the minimum mode s)stem. The basic function of the bus controller chip !-2222* is to deri.e control signals li/e A@ and =A % for memor) and !/? de.ices&* @,N* @T/A* AL, etc. using the information b) the processor on the status lines. The bus controller chip has input lines 52* 51* 59 and -L4. These inputs to 2222 are dri.en b) ->0. !t deri.es the outputs AL,* @,N* @T/A* MA@-* M=T-* AM=-* !?A-* !?=- and A!?=-. The A,N* !?6 and -,N pins are speciall) useful for multiprocessor s)stems. A,N and !?6 are generall) grounded. -,N pin is usuall) tied to M'7. The significance of the M-,/>@,N output depends upon the status of the !?6 pin. !f !?6 is grounded* it acts as master cascade enable to control cascade 22'EA* else it acts as peripheral data enable used in the multiple bus configurations. !NTA pin used to issue two interrupt ac/nowledge pulses to the interrupt controller or to an interrupting de.ice. !?A-* !?=- are !/? read command and !/? write command signals respecti.el). These signals enable an !? interface to read or write the data from or to the address port. The MA@-* M=T- are memor) read command and memor) write command signals respecti.el) and ma) be used as memor) read or write signals. All these command signals instructs the memor) to accept or send data from or to the bus. 3or both of these write command signals* the ad.anced signals namel) A!?=- and AM=T- are a.ailable. Cere the onl) difference between in timing diagram between minimum mode and ma$imum mode is the status signals used and the a.ailable control and ad.anced command signals.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/ 9

Cl k
6 1 2
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'eset
Clk
'eset
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1 2
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'eady 8683 .-3B.-1; .13B.1< .,-
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.ddress &us . dd &u
C 60 C 6* '-
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&uffer
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Perip$era l
Ma$imum Mode 292( 5)stem.

A9* 51* 52 are set at the beginning of bus c)cle.2222 bus controller will output a pulse as on the AL, and appl) a re+uired signal to its @T / A pin during T1. !n T2* 2222 will set @,NL1 thus enabling transcei.ers* and for an input it will acti.ate MA@- or !?A-. These signals are acti.ated until T#. 3or an output* the AM=- or A!?=is acti.ated from T2 to T# and M=T- or !?=- is acti.ated from T to T#. The status bit 59 to 52 remains acti.e until T and become passi.e during T and T # ? !f reader input is not acti.ated before T * wait state will be inserted between T and T#. )imings for 'G, 7) ignals: The re+uest/grant response se+uence contains a series of three pulses. The re+uest/grant pins are chec/ed at each rising pulse of cloc/ input. =hen a re+uest is detected and if the condition for C?L@ re+uest are satisfied* the processor issues a grant pulse o.er the AU/FT pin immediatel) during T# %current& or T1 %ne$t& state. =hen the re+uesting master recei.es this pulse* it accepts the control of the bus* it sends a release pulse to the processor using AU/FT pin.
Clk .*%
2
)1
Memor) Aead Timing in Ma$imum Mode
.dd, tatus .dd,-ata M'-C -) , '
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5c. 6angalore M1/71/8une 9#/ 2
M. 4r is hn a 4 u m ar/ !!
Microprocessors and Microcontrollers/Architecture of Microprocessors One &us cycle )

1
Lecture Notes
)
2
) )4
5
)
1
Clk .*%
F
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Inactive
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Memor) =rite Timing in Ma$imum mode.
Clk
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.not$er master CPU grant &us
Master releases
reHuest &us access
'G,7) )imings in Ma9imum Mode?

Minimum Mode Interface =hen the Minimum mode operation is selected* the 292( pro.ides all control signals needed to implement the memor) and !/? interface.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/
The minimum mode signal can be di.ided into the following basic groups: address/data bus* status* control* interrupt and @MA. .ddress,-ata "us: these lines ser.e two functions. As an address bus is 29 bits long and consists of signal lines A9 through A1E. A1E represents the M56 and A9 L56. A 29bit address gi.es the 292( a 1Mb)te memor) address space. More o.er it has an independent !/? address space which is (#4 b)tes in length. The 1( data bus lines @9 through @1' are actuall) multiple$ed with address lines A9 through A1' respecti.el). 6) multiple$ed we mean that the bus wor/ as an address bus during first machine c)cle and as a data bus during ne$t machine c)cles. @1' is the M56 and @9 L56. =hen acting as a data bus* the) carr) read/write data for memor)* input/output data for !/? de.ices* and interrupt t)pe codes from an interrupt controller.
: c c I()' .6B.1;/.13, I(). Interrupt .ddress , data &us interface
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4
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Memory I,O controls
0O*-M. interface 0*-. ' W ' :cc Mode select M( , M1 C*> clock -%( '%.-+
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6loc/ @iagram of the Minimum Mode 292( M>0

tatus signal: The four most significant address lines A1E through A1( are also multiple$ed but in this case with status signals 5( through 5 . These status bits are output on the bus at the same time that data are transferred o.er the other bus lines.
6it 5# and 5 together from a 2 bit binar) code that identifies which of the 292( internal segment registers are used to generate the ph)sical address that was output on the address bus during the current bus c)cle. -ode 5#5 L 99 identifies a register /nown as e"tra segment register as the source of the segment address.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/ #
5tatus line 5' reflects the status of another internal characteristic of the 292(. !t is the logic le.el of the internal enable flag. The last status bit 5( is alwa)s at the logic 9 le.el.
egment 'egister %9tra tack Code , none -ata
6 6 1 1
6 1 6 1
Memor) segment status codes.

Control ignals: The control signals are pro.ided to support the 292( memor) !/? interfaces. The) control functions such as when the bus is to carr) a .alid address in which direction data are to be transferred o.er the bus* when .alid write data are on the bus and when to put read data on the s)stem bus. AL, is a pulse to logic 1 that signals e$ternal circuitr) when a .alid address word is on the bus. This address must be latched in e$ternal circuitr) on the 1"to"9 edge of the pulse at AL,. Another control signal that is produced during the bus c)cle is 6C, ban/ high enable. Logic 9 on this used as a memor) enable signal for the most significant b)te half of the data bus @2 through @1. These lines also ser.es a second function* which is as the 5 1 status line. 0sing the M/!? and @T/A lines* the 292( signals which t)pe of bus c)cle is in progress and in which direction data are to be transferred o.er the bus. The logic le.el of M/!? tells e$ternal circuitr) whether a memor) or !/? transfer is ta/ing place o.er the bus. Logic 1 at this output signals a memor) operation and logic 9 an !/? operation. The direction of data transfer o.er the bus is signaled b) the logic le.el output at @T/A. =hen this line is logic 1 during the data transfer part of a bus c)cle* the bus is in the transmit mode. Therefore* data are either written into memor) or output to an !/? de.ice.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/ '
?n the other hand* logic 9 at @T/A signals that the bus is in the recei.e mode. This corresponds to reading data from memor) or input of data from an input port. The signal read A@ and write =A indicates that a read bus c)cle or a write bus c)cle is in progress. The 292( switches =A to logic 9 to signal e$ternal de.ice that .alid write or output data are on the bus. ?n the other hand* A@ indicates that the 292( is performing a read of data of the bus. @uring read operations* one other control signal is also supplied. This is @,N % data enable& and it signals e$ternal de.ices when the) should put data on the bus. There is one other control signal that is in.ol.ed with the memor) and !/? interface. This is the A,A@P signal. A,A@P signal is used to insert wait states into the bus c)cle such that it is e$tended b) a number of cloc/ periods. This signal is pro.ided b) an e$ternal cloc/ generator de.ice and can be supplied b) the memor) or !/? sub"s)stem to signal the 292( when the) are read) to permit the data transfer to be completed. Interrupt signals: The /e) interrupt interface signals are interrupt re+uest %!NTA& and interrupt ac/nowledge % !NTA&. !NTA is an input to the 292( that can be used b) an e$ternal de.ice to signal that it need to be ser.iced. Logic 1 at !NTA represents an acti.e interrupt re+uest. =hen an interrupt re+uest has been recogni:ed b) the 292(* it indicates this fact to e$ternal circuit with pulse to logic 9 at the !NTA output. The T,5T input is also related to the e$ternal interrupt interface. ,$ecution of a =A!T instruction causes the 292( to chec/ the logic le.el at the T,5T input. !f the logic 1 is found* the M>0 suspend operation and goes into the idle state. The 292( no longer e$ecutes instructions* instead it repeatedl) chec/s the logic le.el of the T,5T input waiting for its transition bac/ to logic 9. As T,5T switches to 9* e$ecution resume with the ne$t instruction in the program. This feature can be used to s)nchroni:e the operation of the 292( to an e.ent in e$ternal hardware. There are two more inputs in the interrupt interface: the nonmas/able interrupt NM! and the reset interrupt A,5,T. ?n the 9"to "1 transition of NM! control is passed to a nonmas/able interrupt ser.ice routine. The A,5,T input is used to pro.ide a hardware reset for the 292(. 5witching A,5,T to logic 9 initiali:es the internal register of the 292( and initiates a reset ser.ice routine. -M. Interface signals:The direct memor) access @MA interface of the 292( minimum mode consist of the C?L@ and CL@A signals. =hen an e$ternal de.ice wants to ta/e control of the s)stem bus* it signals to the 292( b) switching C?L@ to the logic 1 le.el. At the completion of the current bus c)cle* the 292( enters the hold state. !n the hold state* signal lines A@9 through A@1'* A1(/5 through A1E/5(* 6C,* M/!?* @T/A* A@* =A* @,N and !NTA are all in the high N state. The 292( signals e$ternal de.ice that it is in this state b) switching its CL@A output to logic 1 le.el. Ma9imum Mode Interface =hen the 292( is set for the ma$imum"mode configuration* it pro.ides signals for implementing a multiprocessor / coprocessor s)stem en.ironment.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/ (
6) multiprocessor en.ironment we mean that one microprocessor e$ists in the s)stem and that each processor is e$ecuting its own program. 0suall) in this t)pe of s)stem en.ironment* there are some s)stem resources that are common to all processors. The) are called as glo!al resources. There are also other resources that are assigned to specific processors. These are /nown as local or private resources. -oprocessor also means that there is a second processor in the s)stem. !n this two processor does not access the bus at the same time. ?ne passes the control of the s)stem bus to the other and then ma) suspend its operation. !n the ma$imum"mode 292( s)stem* facilities are pro.ided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.
I(I) Multi "us
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8683 MPU
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MC% , P-%(
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" 0 %
' '%.+ G 1/ G 6 *ocal &us control 'G , 7)1 'G , 7)6
292( Ma$imum mode 6loc/ @iagram
8288 "us Controller F "us Command and Control ignals : 292( does not directl) pro.ide all the signals that are re+uired to control the memor)* !/? and interrupt interfaces. 5peciall) the =A* M/!?* @T/A* @,N* AL, and !NTA* signals are no longer produced b) the 292(. !nstead it outputs three status signals 59* 51* 52 prior to the initiation of each bus c)cle. This " bit bus status code identifies which t)pe of bus c)cle is to follow. 525159 are input to the e$ternal bus controller de.ice* the bus controller generates the appropriatel) timed command and control signals.
Lecture Notes
tatus Inputs CPU Cycles

2
1
8288 Command I(). IO 'C IOW C/ (o ne M' -C M' -C MW )C/ (on e .M WC
6 6 6 6 1
6 6 1 1 6
6 1 6 1 6
Interrupt .ckno#ledge
'ead I,O Port Write I,O Port 0alt Instruction Cetc$
.IO WC
1 1 1
'ead Memory Write Memory Passive
1 1
6 1
"us tatus Codes

The 2222 produces one or two of these eight command signals for each bus c)cles. 3or instance* when the 292( outputs the code 525159 e+uals 991* it indicates that an I() read cycle is to be performed. !n the code 111 is output b) the 292(* it is signaling that no bus acti.it) is to ta/e place. The control outputs produced b) the 2222 are @,N* @T/A and AL,. These signals pro.ide the same functions as those described for the minimum s)stem mode. This set of bus commands and control signals is compatible with the Multibus and industr) standard for interfacing microprocessor s)stems. he output of #*#+ are !us ar!itration signals: !us busy %605P&* common bus re"uest %-6AU&* bus priority out %6>A?&* bus priority in %6>AN&* bus re"uest %6A,U& and bus clock %6-L4&. The) correspond to the bus e$change signals of the Multibus and are used to loc/ other processor off the s)stem bus during the e$ecution of an instruction b) the 292(. !n this wa) the processor can be assured of uninterrupted access to common s)stem resources such as glo!al memory. Gueue tatus ignals: Two new signals that are produced b) the 292( in the ma$imum"
mode s)stem are +ueue status outputs U59 and U51. Together the) form a 2"bit +ueue status code* U51U59. 3ollowing table shows the four different +ueue status.
Lecture Notes
G G 1 6 (lo#)
6
Gueue tatus (o Operation? -uring t$e last clock cycle/ not$ing #as taken from t$e Hueue? Cirst "yte? )$e &yte taken from t$e Hueue #as t$e first &yte of t$e instruction? Gueue %mpty? )$e Hueue $as &een reinitialiJed as a result of t$e e9ecution of a transfer instruction? u&seHuent "yte? )$e &yte taken from t$e Hueue #as a su&seHuent &yte of t$e instruction?
6 1 ($ig$)
Uueue status codes

*ocal "us Control ignal F 'eHuest , 7rant ignals: !n a ma$imum mode configuration* the minimum mode C?L@* CL@A interface is also changed. These two are replaced b) re+uest/grant lines AU/ FT9 and AU/ FT1* respecti.el). The) pro.ide a prioriti:ed bus access mechanism for accessing the local bus. Internal 'egisters of 8683 The 292( has four groups of the user accessible internal registers. The) are the instruction pointer* four data registers* four pointer and inde$ register* four segment registers. The 292( has a total of fourteen 1("bit registers including a 1( bit register called the status register* with E of bits implemented for status and control flags. Most of the registers contain data/instruction offsets within (# 46 memor) segment. There are four different (# 46 segments for instructions* stac/* data and e$tra data. To specif) where in 1 M6 of processor memor) these # segments are located the processor uses four segment registers: Code segment %-5& is a 1("bit register containing address of (# 46 segment with processor instructions. The processor uses -5 segment for all accesses to instructions referenced b) instruction pointer %!>& register. -5 register cannot be changed directl). The -5 register is automaticall) updated during far Dump* far call and far return instructions. tack segment %55& is a 1("bit register containing address of (#46 segment with program stac/. 6) default* the processor assumes that all data referenced b) the stac/ pointer %5>& and base pointer %6>& registers is located in the stac/ segment. 55 register can be changed directl) using >?> instruction. -ata segment %@5& is a 1("bit register containing address of (#46 segment with program data. 6) default* the processor assumes that all data referenced b) general registers %AB* 6B* -B* @B& and inde$ register %5!* @!& is located in the data segment. @5 register can be changed directl) using >?> and L@5 instructions.
.ccumulator register consists of two 2"bit registers AL and AC* which can be combined together and used as a 1("bit register AB. AL in this case contains the low" order b)te of the word* and AC contains the high"order b)te. Accumulator can be used for !/? operations and string manipulation.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/ E
"ase register consists of two 2"bit registers 6L and 6C* which can be combined together and used as a 1(" bit register 6B. 6L in this case contains the low"order b)te of the word* and 6C contains the high"order b)te. 6B register usuall) contains a data pointer used for based* based inde$ed or register indirect addressing. Count register consists of two 2"bit registers -L and -C* which can be combined together and used as a 1("bit register -B. =hen combined* -L register contains the low " order b)te of the word* and -C contains the high "order b)te. -ount register can be used in Loop* shift/rotate instructions and as a counter in string manipulation*. -ata register consists of two 2"bit registers @L and @C* which can be combined together and used as a 1("bit register @B. =hen combined* @L register contains the low" order b)te of the word* and @C contains the high "order b)te. @ata register can be used as a port number in !/? operations. !n integer 2" bit multipl) and di.ide instruction the @B register contains high"order word of the initial or resulting number. I)$e follo#ing registers are &ot$ general and inde9 registers: tack Pointer %5>& is a 1("bit register pointing to program stac/. "ase Pointer %6>& is a 1("bit register pointing to data in stac/ segment. 6> register is usuall) used for based* based inde$ed or register indirect addressing. ource Inde9 %5!& is a 1(" bit register. 5! is used for inde$ed* based inde$ed and register indirect addressing* as well as a source data address in string manipulation instructions. -estination Inde9 %@!& is a 1("bit register. @! is used for inde$ed* based inde$ed and register indirect addressing* as well as a destination data address in string manipulation instructions. Ot$er registers: Instruction Pointer %!>& is a 1("bit register. Clags is a 1("bit register containing E one bit flags. Overflo# Clag %?3& " set if the result is too large positi.e number* or is too small negati.e number to fit into destination operand. -irection Clag %@3& " if set then string manipulation instructions will auto "decrement inde$ registers. !f cleared then the inde$ registers will be auto" incremented. InterruptBena&le Clag %!3& " setting this bit enables mas/able interrupts. ingleBstep Clag %T3& " if set then single"step interrupt will occur after the ne$t instruction. ign Clag %53& " set if the most significant bit of the result is set. Dero Clag %N3& " set if the result is :ero. .u9iliary carry Clag %A3& " set if there was a carr) from or borrow to bits 9" in the AL register. Parity Clag %>3& " set if parit) %the number of ;1; bits& in the low"order b)te of the result is e.en. Carry Clag %-3& " set if there was a carr) from or borrow to the most significant bit during last result calculation. .ddressing Modes Implied " the data .alue/data address is implicitl) associated with the instruction. 'egister " references the data in a register or in a register pair. Immediate " the data is pro.ided in the instruction. -irect " the instruction operand specifies the memor) address where data is located.
M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/#9
'egister indirect " instruction specifies a register containing an address* where data is located. This addressing mode wor/s with 5!* @!* 6B and 6> registers. "ased :" 2"bit or 1("bit instruction operand is added to the contents of a base register %6B or 6>&* the resulting .alue is a pointer to location where data resides. Inde9ed:" 2"bit or 1("bit instruction operand is added to the contents of an inde$ register %5! or @!&* the resulting .alue is a pointer to location where data resides "ased Inde9ed: " the contents of a base register %6B or 6>& is added to the contents of an inde$ register %5! or @!&* the resulting .alue is a pointer to location where data resides. "ased Inde9ed #it$ displacement:" 2"bit or 1("bit instruction operand is added to the contents of a base register %6B or 6>& and inde$ register %5! or @!&* the resulting .alue is a pointer to location where data resides. Memory >rogram* data and stac/ memories occup) the same memor) space. As the most of the processor instructions use 1("bit pointers the processor can effecti.el) address onl) (# 46 of memor). To access memor) outside of (# 46 the ->0 uses special segment registers to specif) where the code* stac/ and data (# 46 segments are positioned within 1 M6 of memor) %see the ;Aegisters; section below&. 1("bit pointers and data are stored as: address: low"order b)te addressM1: high"order b)te Program memory " program can be located an)where in memor). 8ump and call instructions can be used for short Dumps within currentl) selected (# 46 code segment* as well as for far Dumps an)where within 1 M6 of memor). All conditional Dump instructions can be used to Dump within appro$imatel) M121 to " 121 b)tes from current instruction. -ata memory " the processor can access data in an) one out of # a.ailable segments* which limits the si:e of accessible memor) to 2'( 46 %if all four segments point to different (# 46 bloc/s&. Accessing data from the @ata* -ode* 5tac/ or ,$tra segments can be usuall) done b) prefi$ing instructions with the @5:* -5:* 55: or ,5: %some registers and instructions b) default ma) use the ,5 or 55 segments instead of @5 segment&. =ord data can be located at odd or e.en b)te boundaries. The processor uses two memor) accesses to read 1("bit word located at odd b)te boundaries. Aeading word data from e.en b)te boundaries re+uires onl) one memor) access. tack memory can be placed an)where in memor). The stac/ can be located at odd memor) addresses* but it is not recommended for performance reasons %see ;@ata Memor); abo.e&. 'eserved locations: 9999h " 9 33h are reser.ed for interrupt .ectors. ,ach interrupt .ector is a 2"bit pointer in format segment: offset. 33339h " 33333h " after A,5,T the processor alwa)s starts program e$ecution at the 33339h address. Interrupts The processor has the following interrupts:
I()' is a mas/able hardware interrupt. The interrupt can be enabled/disabled using 5T!/-L! instructions or using more complicated method of updating the 3LAF5 register with the help of the >?>3 instruction. =hen an interrupt occurs* the processor stores 3LAF5 register into stac/* disables further interrupts* fetches from the bus one b)te representing interrupt t)pe* and Dumps to interrupt processing routine address of which is stored in location # O Vinterrupt t)peH. !nterrupt processing routine should return with the !A,T instruction. (MI is a non"mas/able interrupt. !nterrupt is processed in the same wa) as the !NTA interrupt. !nterrupt t)pe of the NM! is 2* i.e. the address of the NM! processing routine is stored in location 9992h. This interrupt has higher priorit) then the mas/able interrupt. oft#are interrupts can be caused b): !NT instruction " brea/point interrupt. This is a t)pe interrupt. !NT Vinterrupt numberH instruction " an) one interrupt from a.ailable 2'( interrupts. !NT? instruction " interrupt on o.erflow 5ingle"step interrupt " generated if the T3 flag is set. This is a t)pe 1 interrupt. =hen the ->0 processes this interrupt it clears T3 flag before calling the interrupt processing routine. Processor e9ceptions: @i.ide ,rror %T)pe 9&* 0nused ?pcode %t)pe (& and ,scape opcode %t)pe 1&. 5oftware interrupt processing is the same as for the hardware interrupts.

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